clk: msm: mdss: update PLL configuration to clear precalibrated values

Before going for full PLL enable sequence, we need to clear out the
override bit and precalibrated values of VCO_TUNE and KVCO_CODE, as
these registers might be storing values for old VCO rate. This will
cause the DSI PLL to be in a bad state and hence PLL unlock errors
might occur during use case like resolution switch. So always clear
the precalibrated values first in PLL configuration sequence.

Change-Id: I407920d63b4600b610794141e5b7ceb5a33980c1
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>

diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
index f6c85cf..5f779ec 100644 (file)
--- a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
+++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
@@ -685,6 +685,10 @@ static void pll_db_commit_8996(struct mdss_pll_resources *pll,
        MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, 0);
        wmb();  /* make sure register committed */
 
+       MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_VCO_TUNE, 0);
+       MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_CODE, 0);
+       wmb(); /* make sure register committed */
+
        data = pdb->in.dsiclk_sel; /* set dsiclk_sel = 1  */
        MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CLK_CFG1, data);