if((rawdata & 0x8000) == 0) {
in_signal = false;
+ this->write_signal(SIG_DATAREC_OUT, 0x00, 0x01);
} else {
in_signal = true;
+ this->write_signal(SIG_DATAREC_OUT, 0x01, 0x01);
}
usec = (double)(rawdata & 0x7fff);
usec = usec * 9;
}
break;
case FM7_MAINIO_CMTIN: // fd02
+ cmt_rdata = val_b;
return;
case FM7_MAINIO_TIMERIRQ: //
set_irq_timer(val_b);
return (uint32) read_kanjidata_right();
break;
case 0x37: // Multi page
- return (uint32)subio->read_signal(0x37);
+ return (uint32)display->read_data8(DISPLAY_ADDR_MULTIPAGE);
break;
default:
break;
}
if((addr < 0x40) && (addr >= 0x38)) {
- return (uint32) subio->read_signal(addr);
+ addr = (addr - 0x38) + DISPLAY_ADDR_DPALETTE;
+ return (uint32) display->read_data8(addr);
}
// Another:
return 0xff;
return write_kanjiaddr_lo((uint8)data);
break;
case 0x37: // Multi page
- return subio->set_signal(0x37, (uint8)data);
+ return display->write_data8(DISPLAY_ADDR_MULTIPAGE, (uint8)data);
break;
default:
break;
}
if((addr < 0x40) && (addr >= 0x38)) {
- subio->set_signal(addr, (uint8)data);
+ addr = (addr - 0x38) + DISPLAY_ADDR_DPALETTE;
+ display->write_data8(addr, (uint8)data);
return;
}
// Another:
void VM::connect_bus(void)
{
- int i;
-
- /*
- * CLASS CONSTRUCTION
- *
- * VM
- * |-> MAINCPU -> MAINMEM -> MAINIO -> MAIN DEVICES
- * | | |
- * | -> SUBCPU -> SUBMEM -> SUBIO -> SUB DEVICES
- * | -> DISPLAY
- * | -> KEYBOARD
- *
- * MAINMEM can access SUBMEM/IO, when SUBCPU is halted.
- * MAINMEM and SUBMEM can access DISPLAY and KEYBOARD with exclusive.
- * MAINCPU can access MAINMEM.
- * SUBCPU can access SUBMEM.
- * DISPLAY : R/W from MAINCPU and SUBCPU.
- * KEYBOARD : R/W
- *
- */
- event->set_context_cpu(maincpu);
- event->set_context_cpu(subcpu);
-
- if((!opn_psg_77av) || (!opn_connected)) {
- event->set_context_sound(psg);
- }
- if(opn_connected) {
- event->set_context_sound(opn[0]);
- }
- if(whg_connected) {
- event->set_context_sound(opn[1]);
- }
- if(thg_connected) {
- event->set_context_sound(opn[2]);
- }
- // CMT
- cmt->set_context_out(mainio, SIG_FM7_CMTIN, 0x0001);
-
- // keyboard->set_context_break_key(mainio, SIG_FM7_BREAKKEY, 0x0080);
+ int i;
+
+ /*
+ * CLASS CONSTRUCTION
+ *
+ * VM
+ * |-> MAINCPU -> MAINMEM -> MAINIO -> MAIN DEVICES
+ * | | |
+ * | -> SUBCPU -> SUBMEM -> SUBIO -> SUB DEVICES
+ * | -> DISPLAY
+ * | -> KEYBOARD
+ *
+ * MAINMEM can access SUBMEM/IO, when SUBCPU is halted.
+ * MAINMEM and SUBMEM can access DISPLAY and KEYBOARD with exclusive.
+ * MAINCPU can access MAINMEM.
+ * SUBCPU can access SUBMEM.
+ * DISPLAY : R/W from MAINCPU and SUBCPU.
+ * KEYBOARD : R/W
+ *
+ */
+ event->set_context_cpu(maincpu);
+ event->set_context_cpu(subcpu);
+
+ if((!opn_psg_77av) || (!opn_connected)) {
+ event->set_context_sound(psg);
+ }
+ if(opn_connected) {
+ event->set_context_sound(opn[0]);
+ }
+ if(whg_connected) {
+ event->set_context_sound(opn[1]);
+ }
+ if(thg_connected) {
+ event->set_context_sound(opn[2]);
+ }
+ // CMT
+ cmt->set_context_out(mainio, FM7_MAINIO_CMTIN, 0x0001);
- keyboard->set_context_mainio(mainio);
- keyboard->set_context_subio(subio);
- keyboard->set_context_interrupt(mainio, SIG_FM7_MAIN_KEYIRQ, 0x0080);
- keyboard->set_context_interrupt(subio, SIG_FM7_SUB_KEYFIRQ, 0x0080);
+ keyboard->set_context_mainio(mainio);
+ keyboard->set_context_subio(subio);
+ //keyboard->set_context_interrupt(mainio, SIG_FM7_MAIN_KEYIRQ, 0x0080);
+ //keyboard->set_context_interrupt(subio, SIG_FM7_SUB_KEYFIRQ, 0x0080);
- mainmem->set_context_submem(submem);
- // mainmem->set_context_cpu(maincpu);
+ mainmem->set_context_submem(submem);
+ // mainmem->set_context_cpu(maincpu);
- mainio->set_context_mem(mainmem);
-
- //submem->set_context_cpu(subcpu);
- subio->set_context_mem(submem);
-
- // subio->set_context_mainsub(mainio, SIG_FM7_KEYPRESS, 0x01ff);
- subio->set_context_bus(mainio, SIG_FM7_SUB_ATTENTION, 0xff);
+ mainio->set_context_maincpu(maincpu);
+ mainio->set_context_subcpu(subcpu);
- // subio->set_context_bus(mainio, SIG_FM7_SUB_KEYIN, 0x1ff);
- subio->set_context_bus(mainio, SIG_FM7_SUB_READY, 0xff);
+ subio->set_context_maincpu(maincpu);
+ subio->set_context_subcpu(subcpu);
- mainio->set_context_bus(subio, SIG_FM7_SUB_HALTREQ, 0xff);
- mainio->set_context_bus(subcpu, SIG_CPU_BUSREQ, 0xff); // HALT
+ // Palette, VSYNC, HSYNC, Multi-page, display mode.
+ mainio->set_context_display(display);
+ subio->set_context_display(display);
+ display->set_context_submem(submem); // For VRAM?
+ display->set_context_subcpu(subcpu); // For VRAM?
-
- // Palette, VSYNC, HSYNC, Multi-page, display mode.
- mainio->set_context_display(display);
- subio->set_context_display(display);
- display->set_context_submem(submem); // For VRAM?
-
-
- subio->set_context_display(display, SIG_FM7_SUB_ANALOG_PALETTE_ADDRESS, 0xfff);
- subio->set_context_display(display, SIG_FM7_SUB_ANALOG_PALETTE_DATA, 0xfff);
-
- subio->set_context_mainsub(display, SIG_FM7_DISPLAY_MODE, 0xff);
- fdc->set_context_irq(mainio, SIG_FM7_FDC_IRQ, 0xffffffff);
- fdc->set_context_drq(mainio, SIG_FM7_FDC_DRQ, 0xffffffff);
+ fdc->set_context_irq(mainio, SIG_FM7_FDC_IRQ, 0xffffffff);
+ fdc->set_context_drq(mainio, SIG_FM7_FDC_DRQ, 0xffffffff);
- psg->set_context_irq(mainio, SIG_FM7_PSG_IRQ, 0xffffffff);
- opn[0]->set_context_irq(mainio, SIG_FM7_OPN_IRQ, 0xffffffff);
- opn[1]->set_context_irq(mainio, SIG_FM7_WHG_IRQ, 0xffffffff);
- opn[2]->set_context_irq(mainio, SIG_FM7_THG_IRQ, 0xffffffff);
+ psg->set_context_irq(mainio, SIG_FM7_PSG_IRQ, 0xffffffff);
+ opn[0]->set_context_irq(mainio, SIG_FM7_OPN_IRQ, 0xffffffff);
+ opn[1]->set_context_irq(mainio, SIG_FM7_WHG_IRQ, 0xffffffff);
+ opn[2]->set_context_irq(mainio, SIG_FM7_THG_IRQ, 0xffffffff);
- opn[0]->set_context_port_a(mainio, SIG_FM7_OPN_JOY_A, 0xff);
- opn[0]->set_context_port_b(mainio, SIG_FM7_OPN_JOY_B, 0xff);
+ opn[0]->set_context_port_a(mainio, SIG_FM7_OPN_JOY_A, 0xff);
+ opn[0]->set_context_port_b(mainio, SIG_FM7_OPN_JOY_B, 0xff);
- maincpu->set_context_mem(mainmem);
- subcpu->set_context_mem(submem);
+ maincpu->set_context_mem(mainmem);
+ subcpu->set_context_mem(submem);
}
#define _VM_FM7_MAINIO_H_
#include "../device.h"
+#include "./kanjirom.h"
enum {
- FM7_MAINCLOCK_SLOW,
- FM7_MAINCLOCK_HIGH,
- FM7_MAINCLOCK_MMRSLOW,
- FM7_MAINCLOCK_MMRHIGH
+ FM7_MAINCLOCK_SLOW = 0,
+ FM7_MAINCLOCK_HIGH,
+ FM7_MAINCLOCK_MMRSLOW,
+ FM7_MAINCLOCK_MMRHIGH
};
+enum {
+ FM7_MAINIO_CLOCKMODE = 0x1000,
+ FM7_MAINIO_CMTIN, // Input data changed
+ FM7_MAINIO_TIMERIRQ, // Timer from SUB.
+ FM7_MAINIO_LPTIRQ,
+ FM7_MAINIO_KEYBOARDIRQ,
+ FM7_MAINIO_PUSH_KEYBOARD,
+ FM7_MAINIO_PUSH_BREAK, // FIRQ
+ FM7_MAINIO_SUB_ATTENTION, // FIRQ
+ FM7_MAINIO_EXTDET,
+ FM7_MAINIO_BEEP, // BEEP From sub
+ FM7_MAINIO_OPNPORTA_CHANGED, // Joystick
+ FM7_MAINIO_OPNPORTB_CHANGED, // Joystick
+ FM7_MAINIO_FDC_DRQ,
+ FM7_MAINIO_FDC_IRQ,
+ FM7_MAINIO_MPUCLOCK
+};
class YM2203;
class BEEP;
class MB8877;
class IO;
class DEVICE;
+class MEMORY;
class FM7_CMT : public DATAREC
{
class FM7_MAINIO : public MEMORY {
protected:
- int waitcount = 0;
+ int waitcount;
/* FD00: R */
- bool clock_fast = true; // bit0 : maybe dummy
+ bool clock_fast; // bit0 : maybe dummy
uint8 kbd_bit8; // bit7
/* FD00: W */
bool lpt_strobe; // bit6 : maybe dummy entry
// 2 : TIMER
// 1 : PRINTER
// 0 : KEYBOARD
- bool irqmask_mfd = false; // bit4: "0" = mask.
- bool irqmask_timer = false; // bit2: "0" = mask.
- bool irqmask_printer = false; // bit1: "0" = mask.
- bool irqmask_keyboard = false; // bit0: "0" = mask.
+ bool irqmask_mfd; // bit4: "0" = mask.
+ bool irqmask_timer; // bit2: "0" = mask.
+ bool irqmask_printer; // bit1: "0" = mask.
+ bool irqmask_keyboard; // bit0: "0" = mask.
/* FD03: R */
uint8 irqstat_reg0 = 0xff; // bit 3-0, '0' is happened, '1' is not happened.
/* FD03 : W , '1' = ON*/
/* FD04 : R */
- bool stat_fdmode_2hd = false; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
- bool stat_kanjirom = true; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
- bool stat_400linecard = false;// R/W : bit4, '0' = connected. FM-77 Only.
- bool stat_400linemode = false; // R/W : bit3, '0' = 400line, '1' = 200line.
- bool firq_break_key = false; // bit1, ON = '0'.
- bool firq_sub_attention = false; // bit0, ON = '0'.
+ bool stat_fdmode_2hd; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
+ bool stat_kanjirom; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
+ bool stat_400linecard;// R/W : bit4, '0' = connected. FM-77 Only.
+ bool stat_400linemode; // R/W : bit3, '0' = 400line, '1' = 200line.
+ bool firq_break_key; // bit1, ON = '0'.
+ bool firq_sub_attention; // bit0, ON = '0'.
/* FD04 : W */
- bool intmode_fdc = false; // bit2, '0' = normal, '1' = SFD.
+ bool intmode_fdc; // bit2, '0' = normal, '1' = SFD.
/* FD05 : R */
- bool sub_busy = false; // bit7 : '0' = READY '1' = BUSY.
- bool extdet_neg = false; // bit0 : '1' = none , '0' = exists.
+ bool sub_busy; // bit7 : '0' = READY '1' = BUSY.
+ bool extdet_neg; // bit0 : '1' = none , '0' = exists.
/* FD05 : W */
- bool sub_haltreq = false; // bit7 : '1' = HALT, maybe dummy.
- bool sub_cansel = false; // bit6 : '1' Cansel req.
- bool z80_sel = false; // bit0 : '1' = Z80. Maybe only FM-7/77.
+ bool sub_haltreq; // bit7 : '1' = HALT, maybe dummy.
+ bool sub_cansel; // bit6 : '1' Cansel req.
+ bool z80_sel; // bit0 : '1' = Z80. Maybe only FM-7/77.
/* FD06 : R/W : RS-232C */
/* FD07 : R/W : RS-232C */
/* FD09 : Grafic pen, not implemented */
/* FD0A : Grafic pen, not implemented */
/* FD0B : R */
- bool stat_bootsw_basic = true; // bit0 : '0' = BASIC '1' = DOS. Only 77AV/20/40.
+ bool stat_bootsw_basic; // bit0 : '0' = BASIC '1' = DOS. Only 77AV/20/40.
/* FD0D : W */
- uint8 psg_cmdreg = 0b11111100; // PSG Register, Only bit 0-1 at FM-7/77 , 3-0 at FM-77AV series. Maybe dummy.
+ uint8 psg_cmdreg; // PSG Register, Only bit 0-1 at FM-7/77 , 3-0 at FM-77AV series. Maybe dummy.
/* FD0E : R */
uint8 psg_statreg; // PSG data. maybe dummy.
- uint32 psg_address = 0x00;
- uint32 psg_data = 0x00;
- bool psg_bus_high = false; // true when bus = high inpedance.
+ uint32 psg_address;
+ uint32 psg_data;
+ bool psg_bus_high; // true when bus = high inpedance.
/* FD0F : R/W */
- bool stat_romrammode = true; // R(true) = ROM, W(false) = RAM.
+ bool stat_romrammode; // R(true) = ROM, W(false) = RAM.
/* FD15 / FD46 / FD51 : W */
- bool connect_opn = false; // [0]
- bool connect_whg = false; // [1]
- bool connect_thg = false; // [2]
- uint32 opn_address[3] = {0x00, 0x00, 0x00};
- uint32 opn_data[3] = {0x00, 0x00, 0x00};
- uint8 opn_cmdreg[3] = {0b11110000, 0b11110000, 0b11110000}; // OPN register, bit 3-0, maybe dummy.
+ bool connect_opn; // [0]
+ bool connect_whg; // [1]
+ bool connect_thg; // [2]
+ bool psg_shared_opn;
+ uint32 opn_address[3];
+ uint32 opn_data[3];
+ uint8 opn_cmdreg[3]; // OPN register, bit 3-0, maybe dummy.
/* OPN Joystick */
- uint32 opnport_a = 0;
- uint32 opnport_b = 0;
+ uint32 opnport_a;
+ uint32 opnport_b;
/* FD47 */
- bool intstat_whg = false; // bit3 : OPN interrupt. '0' = happened.
+ bool intstat_whg; // bit3 : OPN interrupt. '0' = happened.
/* FD53 */
- bool intstat_thg = false; // bit3 : OPN interrupt. '0' = happened.
+ bool intstat_thg; // bit3 : OPN interrupt. '0' = happened.
- /* FD16 / FD46 / FD52 : R/W */
- uint8 opn_data[3]; // OPN data, maybe dummy.
/* FD17 : R */
- bool intstat_opn = false; // bit3 : OPN interrupt. '0' = happened.
- bool intstat_mouse = false; // bit2 : Mouse interrupt (not OPN-Mouse?), '0' = happened.
- bool intstat_opn = false; // bit3 : OPN interrupt. '0' = happened.
+ bool intstat_opn; // bit3 : OPN interrupt. '0' = happened.
+ bool intstat_mouse; // bit2 : Mouse interrupt (not OPN-Mouse?), '0' = happened.
/* FD17 : W */
- bool mouse_enable = false; // bit2 : '1' = enable.
+ bool mouse_enable; // bit2 : '1' = enable.
/* FD18 : R */
bool connect_fdc = false;
uint8 fdc_headreg; // bit0, '0' = side0, '1' = side1
/* FD1D : R/W */
- bool fdc_motor = false; // bit7 : '1' = ON, '0' = OFF
+ bool fdc_motor; // bit7 : '1' = ON, '0' = OFF
uint8 fdc_drvsel; // bit 1-0
/* FD1F : R */
- bool fdc_drq = false; // bit7 : '1' = ON
- bool fdc_irq = false; // bit6 : '1' = ON
- uint8 irqstat_fdc = 0;
+ bool fdc_drq; // bit7 : '1' = ON
+ bool fdc_irq; // bit6 : '1' = ON
+ uint8 irqstat_fdc;
/* FD20,FD21 : W */
- bool connect_kanjiroml1 = false;
+ bool connect_kanjiroml1;
uint8 kaddress_hi; // FD20 : ADDRESS OF HIGH.
uint8 kaddress_lo; // FD21 : ADDRESS OF LOW.
/* FD20, FD21 : R */
- uint8 kdata_left; // FD20 DATA OF LEFT. Maybe dummy.
- uint8 kdata_right; // FD21 DATA OF RIGHT. Maybe dummy.
/* FD37 : W */
uint8 multipage_disp; // bit6-4 : to display : GRB. '1' = disable, '0' = enable.
/* Devices */
YM2203* opn[3]; // 0=OPN 1=WHG 2=THG
YM2203* psg; // FM-7/77 ONLY
+
class FM7_CMT* cmt;
BEEP* beep;
MB8877* fdc;
- FM7_KEYBOARD *keyboard; // 7/77 compatible
//FM7_PRINTER *printer;
//FM7_RS232C *rs232c;
/* */
- FM7_SUBIO* subio; // event?
+ KANJIROM *kanjiclass1;
+ DISPLAY *display;
+ MC6809 *maincpu;
+ MC6809 *subcpu;
+ Z80 *z80;
public:
FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : MEMORY(parent_vm, parent_emu)
- {
- }
+ {
+ int i;
+ waitcount = 0;
+ // FD00
+ clock_fast = true;
+ kbd_bit8 = 0; // bit7
+ lpt_strobe = false;
+ lpt_slctin = false;
+ // FD01
+ kbd_bit7_0 = 0x00;
+ lpt_outdata = 0x00;
+ // FD02
+ cmt_rdada = false;
+ lpt_det2 = false;
+ lpt_det1 = false;
+ lpt_pe = false;
+ lpt_ackng_inv = false;
+ lpt_error_inv = false;
+ lpt_busy = false;
+ irqmask_reg0 = 0x00;
+ // FD03
+ irqmask_mfd = false;
+ irqmask_timer = false;
+ irqmask_printer = false;
+ irqmask_keyboard = false;
+ irqstat_reg0 = 0xff;
+ // FD04
+ stat_fdmode_2hd = false; // R/W : bit6, '0' = 2HD, '1' = 2DD. FM-77 Only.
+ stat_kanjirom = true; // R/W : bit5, '0' = sub, '1' = main. FM-77 Only.
+ stat_400linecard = false;// R/W : bit4, '0' = connected. FM-77 Only.
+ stat_400linemode = false; // R/W : bit3, '0' = 400line, '1' = 200line.
+ firq_break_key = false; // bit1, ON = '0'.
+ firq_sub_attention = false; // bit0, ON = '0'.
+ intmode_fdc = false; // bit2, '0' = normal, '1' = SFD.
+ // FD05
+ sub_busy = false;
+ extdet_neg = false;
+ sub_haltreq = false;
+ sub_cansel = false; // bit6 : '1' Cansel req.
+ z80_sel = false; // bit0 : '1' = Z80. Maybe only FM-7/77.
+ // FD06,07
+ intstat_syndet = false;
+ intstat_rxrdy = false;
+ intstat_txrdy = false;
+ // FD0B
+ stat_bootsw_basic = true; // bit0 : '0' = BASIC '1' = DOS. Only 77AV/20/40.
+ // FD0D
+ psg_cmdreg = 0b11111100;
+ psg_statreg = 0x00;
+ psg_address = 0x00;
+ psg_data = 0x00;
+ psg_bus_high = false;
+ // FD0F
+ stat_romrammode = true; // ROM ON
+ // FD15/ FD46 / FD51
+ connect_opn = false;
+ connect_whg = false;
+ connect_thg = false;
+ psg_shared_opn = false;
+
+ for(i = 0; i < 3; i++) {
+ opn_address[i] = 0x00;
+ opn_data[i] = 0x00;
+ opn_cmdreg[i] = 0b11110000;
+ }
+ opnport_a = 0x00;
+ opnport_b = 0x00;
+
+ intstat_whg = false;
+ intstat_thg = false;
+ // FD17
+ intstat_opn = false;
+ intstat_mouse = false;
+ mouse_enable = false;
+ // FD18-FD1F
+ connect_fdc = false;
+ fdc_statreg = 0x00;
+ fdc_cmdreg = 0x00;
+ fdc_trackreg = 0x00;
+ fdc_sectreg = 0x00;
+ fdc_datareg = 0x00;
+ fdc_headreg = 0x00;
+ fdc_drvsel = 0x00;
+ fdc_motor = false;
+ fdc_drq = false;
+ fdc_irq = false;
+ irqstat_fdc = 0;
+ // FD20, FD21
+ connect_kanjirom1 = false;
+
+ }
~FM7_MAINIO(){}
- virtual void set_clockmode(uint8 flags);
- virtual uint8 get_clockmode(void);
- void set_cmt_motor(uint8 flag);
- bool get_cmt_motor(void);
-
- virtual uint8 get_port_fd00(void);
- virtual void set_port_fd00(uint8 data);
- virtual uint32 get_keyboard(void); // FD01
- virtual uint8 get_port_fd02(void);
+ virtual void set_clockmode(uint8 flags);
+ virtual uint8 get_clockmode(void);
+ void set_cmt_motor(uint8 flag);
+ bool get_cmt_motor(void);
+
+ virtual uint8 get_port_fd00(void);
+ virtual void set_port_fd00(uint8 data);
+ virtual uint32 get_keyboard(void); // FD01
+ virtual uint8 get_port_fd02(void);
- virtual void set_beep(uint32 data); // fd03
+ virtual void set_beep(uint32 data); // fd03
- void do_irq(bool flag);
- void set_irq_timer(bool flag);
- void set_irq_printer(bool flag);
- void set_irq_keyboard(bool flag);
- void set_irq_opn(bool flag);
- virtual void set_keyboard(uint32 data);
+ void do_irq(bool flag);
+ void set_irq_timer(bool flag);
+ void set_irq_printer(bool flag);
+ void set_irq_keyboard(bool flag);
+ void set_irq_opn(bool flag);
+ virtual void set_keyboard(uint32 data);
- // FD04
- void do_firq(bool flag);
+ // FD04
+ void do_firq(bool flag);
- void set_break_key(bool pressed);
- void set_sub_attention(bool flag);
+ void set_break_key(bool pressed);
+ void set_sub_attention(bool flag);
- uint8 get_fd04(void);
- void set_fd04(uint8 val);
- uint8 get_fd05(void);
- void set_fd05(uint8 val);
-
- virtual void set_extdet(bool flag);
- // FD0D
- void set_psg(uint8 val);
- uint8 get_psg(void);
- // FD0E
- void set_psg_cmd(uint32 cmd);
- uint8 get_psg_cmd(void);
-
- void write_fd0f(void) {
- stat_romrammode = false;
- }
- uint8 read_fd0f(void) {
+ uint8 get_fd04(void);
+ void set_fd04(uint8 val);
+ uint8 get_fd05(void);
+ void set_fd05(uint8 val);
+
+ virtual void set_extdet(bool flag);
+ // FD0D
+ void set_psg(uint8 val);
+ uint8 get_psg(void);
+ // FD0E
+ void set_psg_cmd(uint32 cmd);
+ uint8 get_psg_cmd(void);
+
+ void write_fd0f(void) {
+ stat_romrammode = false;
+ }
+ uint8 read_fd0f(void) {
stat_romrammode = true;
return 0xff;
- }
- bool get_rommode_fd0f(void) {
+ }
+ bool get_rommode_fd0f(void) {
return stat_romrammode;
- }
- virtual uint8 get_extirq_fd17(void);
- virtual void set_ext_fd17(uint8 data);
+ }
+ virtual uint8 get_extirq_fd17(void);
+ virtual void set_ext_fd17(uint8 data);
- // OPN
- void set_opn(uint8 val);
- uint8 get_opn(void);
- void set_opn_cmd(uint32 cmd);
- uint8 get_opn_cmd(void);
+ // OPN
+ void set_opn(uint8 val);
+ uint8 get_opn(void);
+ void set_opn_cmd(uint32 cmd);
+ uint8 get_opn_cmd(void);
- void set_whg(uint8 val);
- uint8 get_whg(void);
- void set_whg_cmd(uint32 cmd);
- uint8 get_whg_cmd(void);
-
- void set_thg(uint8 val);
- uint8 get_thg(void);
- void set_thg_cmd(uint32 cmd);
- uint8 get_thg_cmd(void);
-
- void write_kanjiaddr_lo(uint8 addr);
- void write_kanjiaddr_hi(uint8 addr);
- uint8 read_kanjidata_left(void);
- uint8 read_kanjidata_right(void);
+ void set_whg(uint8 val);
+ uint8 get_whg(void);
+ void set_whg_cmd(uint32 cmd);
+ uint8 get_whg_cmd(void);
+
+ void set_thg(uint8 val);
+ uint8 get_thg(void);
+ void set_thg_cmd(uint32 cmd);
+ uint8 get_thg_cmd(void);
+
+ void write_kanjiaddr_lo(uint8 addr);
+ void write_kanjiaddr_hi(uint8 addr);
+ uint8 read_kanjidata_left(void);
+ uint8 read_kanjidata_right(void);
// FDC
- uint8 get_fdc_fd1c(void);
- void set_fdc_fd1c(uint8 val);
- void set_fdc_fd1d(uint8 val);
-
- uint8 get_fdc_stat(void);
- void set_fdc_stat(uint8 val);
+ uint8 get_fdc_fd1c(void);
+ void set_fdc_fd1c(uint8 val);
+ void set_fdc_fd1d(uint8 val);
+
+ uint8 get_fdc_stat(void);
+ void set_fdc_stat(uint8 val);
- virtual void set_fdc_track(uint8 val);
- virtual uint8 get_fdc_track(void);
+ virtual void set_fdc_track(uint8 val);
+ virtual uint8 get_fdc_track(void);
- uint8 get_fdc_motor(void);
+ uint8 get_fdc_motor(void);
- void set_fdc_sector(uint8 val);
+ void set_fdc_sector(uint8 val);
- uint8 get_fdc_sector(void);
+ uint8 get_fdc_sector(void);
- void set_fdc_data(uint8 val);
- uint8 get_fdc_data(void);
+ void set_fdc_data(uint8 val);
+ uint8 get_fdc_data(void);
- bool fdc_motor = false; // bit7 : '1' = ON, '0' = OFF
- uint8 fdc_drvsel; // bit 1-0
- virtual void write_memory_mapped_io8(uint32 addr, uint32 data);
- virtual uint32 read_memory_mapped_io8(uint32 addr);
+ virtual void write_memory_mapped_io8(uint32 addr, uint32 data);
+ virtual uint32 read_memory_mapped_io8(uint32 addr);
+
+ void write_signals(int id, uint32 data, uint32 mask);
+ void set_context_kanjirom_class1(KANJIROM *p)
+ {
+ kanjiclass1 = p;
+ }
+ void set_context_beep(BEEP *p)
+ {
+ beep = p;
+ }
+ void set_context_fdc(MB8877 *p){
+ fdc = p;
+ }
+ void set_context_display(DISPLAY *p){
+ display = p;
+ }
+ void set_context_maincpu(MC6809 *p){
+ maincpu = p;
+ }
+ void set_context_subcpu(MC6809 *p){
+ subcpu = p;
+ }
+ void set_context_z80cpu(Z80 *p){
+ z80 = p;
+ }
+ void set_context_cmt(class FM7_CMT *p){
+ cmt = p;
+ }
- void write_signals(int id, uint32 data, uint32 mask);
-
}
#endif
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