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[X86] Add VPSRLWZrr to skylake server scheduler model.
author
Craig Topper
<craig.topper@intel.com>
Sun, 10 Dec 2017 17:42:38 +0000
(17:42 +0000)
committer
Craig Topper
<craig.topper@intel.com>
Sun, 10 Dec 2017 17:42:38 +0000
(17:42 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320315
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86SchedSkylakeServer.td
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diff --git
a/lib/Target/X86/X86SchedSkylakeServer.td
b/lib/Target/X86/X86SchedSkylakeServer.td
index
8b46cb8
..
388df27
100755
(executable)
--- a/
lib/Target/X86/X86SchedSkylakeServer.td
+++ b/
lib/Target/X86/X86SchedSkylakeServer.td
@@
-3000,6
+3000,7
@@
def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLQZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLQZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLWYrr")>;
def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLWZ256rr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup53], (instregex "VPSRLWZrr(b?)(k?)(z?)")>;
def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
let Latency = 4;