- bit ok.

- cmp bug fix
- cpy supported.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index ac00167..b4facbe 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -122,7 +122,6 @@ signal v : std_logic;
 
 signal arith_reg_in : std_logic_vector (dsize - 1 downto 0);
 signal arith_reg : std_logic_vector (dsize - 1 downto 0);
-signal arith_buf_we : std_logic;
 
 begin
 
@@ -141,8 +140,8 @@ begin
     ----------------------------------------
      -- arithmatic operation instances ----
     ----------------------------------------
-    arith_buf : d_flip_flop generic map (dsize) 
-            port map(clk, '1', '1', arith_buf_we, arith_reg_in, arith_reg);
+--    arith_buf : d_flip_flop generic map (dsize) 
+--            port map(clk, '1', '1', arith_buf_we, arith_reg_in, arith_reg);
 
     alu_inst : alu_core generic map (dsize)
             port map (sel, d1, d2, d_out, c_in, n, z, c, v);
@@ -205,10 +204,16 @@ use std.textio.all;
 use ieee.std_logic_textio.all;
 variable out_l : line;
 begin
-    write(out_l, msg);
-    writeline(output, out_l);
+--    write(out_l, msg);
+--    writeline(output, out_l);
 end  procedure;
 
+procedure set_nz is
+begin
+    negative <= n;
+    zero <= z;
+end procedure;
+
     begin
 
     if (pcl_inc_n = '0') then
@@ -435,36 +440,25 @@ end  procedure;
     -------------------------------
     if (arith_en_n = '0') then
 
-        arith_buf_we <= '0';
-
         if instruction = conv_std_logic_vector(16#ca#, dsize) then
             --d_print("dex");
             sel <= ALU_DEC;
             d1 <= index_bus;
-            c_in <= '0';
-
-            negative <= n;
-            zero <= z;
+            set_nz;
             output_d_bus;
 
         elsif instruction = conv_std_logic_vector(16#88#, dsize) then
             --d_print("dey");
             sel <= ALU_DEC;
             d1 <= index_bus;
-            c_in <= '0';
-
-            negative <= n;
-            zero <= z;
+            set_nz;
             output_d_bus;
 
         elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
             --d_print("inx");
             sel <= ALU_INC;
             d1 <= index_bus;
-            c_in <= '0';
-
-            negative <= n;
-            zero <= z;
+            set_nz;
             output_d_bus;
 
         elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
@@ -486,8 +480,7 @@ end  procedure;
                 sel <= ALU_CMP;
                 d1 <= acc_out;
                 d2 <= int_d_bus;
-                negative <= n;
-                zero <= z;
+                set_nz;
                 carry_out <= c;
 
             elsif instruction (7 downto 5) = "111" then
@@ -510,21 +503,31 @@ end  procedure;
         elsif instruction (1 downto 0) = "00" then
             if instruction (7 downto 5) = "001" then
                 d_print("bit");
+                sel <= ALU_BIT;
+                d1 <= acc_out;
+                d2 <= int_d_bus;
+                set_nz;
+                overflow <= v;
             elsif instruction (7 downto 5) = "110" then
-                d_print("cpy");
+                --d_print("cpy");
+                sel <= ALU_CMP;
+                d1 <= index_bus;
+                d2 <= int_d_bus;
+                set_nz;
+                carry_out <= c;
+
             elsif instruction (7 downto 5) = "111" then
                -- d_print("cpx");
                 sel <= ALU_CMP;
                 d1 <= index_bus;
                 d2 <= int_d_bus;
-                negative <= n;
-                zero <= z;
+                set_nz;
                 carry_out <= c;
 
             end if; --if instruction (7 downto 5) = "001" then
         end if; --if instruction = conv_std_logic_vector(16#ca#, dsize) 
     else
-        arith_buf_we <= '1';
+
     end if; -- if (arith_en_n = '0') then
     end process;
 
@@ -675,7 +678,12 @@ end procedure;
     elsif sel = ALU_OR then
         res := d1 or d2;
     elsif sel = ALU_BIT then
-        ----
+        --transfer bit 7 and 6  of memory data to n, v flag.
+        negative <= d2(7);
+        overflow <= d2(6);
+        ----zero bit after A and M.
+        res(dsize - 1 downto 0) := d1 and d2;
+        set_z(res(dsize - 1 downto 0));
     elsif sel = ALU_ADC then
         res := ('0' & d1) + ('0' & d2) + carry_in;
         d_out <= res(dsize - 1 downto 0);
@@ -686,6 +694,8 @@ end procedure;
         else
             overflow <= '0';
         end if;
+        set_n(res(dsize - 1 downto 0));
+        set_z(res(dsize - 1 downto 0));
 
     elsif sel = ALU_SBC then
         ----
@@ -707,14 +717,16 @@ end procedure;
     elsif sel = ALU_INC then
         res := ('0' & d1) + "000000001";
         d_out <= res(dsize - 1 downto 0);
-        carry_out <= res(dsize);
+        set_n(res(dsize - 1 downto 0));
+        set_z(res(dsize - 1 downto 0));
+
     elsif sel = ALU_DEC then
         res := ('0' & d1) - "000000001";
         d_out <= res(dsize - 1 downto 0);
-        carry_out <= res(dsize);
+        set_n(res(dsize - 1 downto 0));
+        set_z(res(dsize - 1 downto 0));
+
     end if;
-    set_n(res(dsize - 1 downto 0));
-    set_z(res(dsize - 1 downto 0));
 
     end process;
 

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index d0be12a..1a37628 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -261,12 +261,20 @@ begin
     stat_bus_nz_n <= '0';
 end  procedure;
 
---procedure set_nz_from_alu is
---begin
---end  procedure;
---
 procedure set_nzc_from_alu is
 begin
+    --status register n/z/c bit update.
+    stat_alu_we_n <= '0';
+    stat_dec_oe_n <= '1';
+    status_reg <= "10000011";
+end  procedure;
+
+procedure set_nzv_from_alu is
+begin
+    --status register n/z/v bit update.
+    stat_alu_we_n <= '0';
+    stat_dec_oe_n <= '1';
+    status_reg <= "11000010";
 end  procedure;
 
 --flag on/off instruction
@@ -754,6 +762,11 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#2c#, dsize) then
                     --abs
                     d_print("bit");
+                    a2_abs;
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        set_nzv_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#c9#, dsize) then
                     --imm

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index ef24436..f060bb8 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -247,7 +247,6 @@ end component;
                     
     signal alu_n : std_logic;
     signal alu_z : std_logic;
-    signal alu_c_in : std_logic;
     signal alu_c : std_logic;
     signal alu_v : std_logic;
 
@@ -406,7 +405,7 @@ begin
                     abh,
                     pcl_inc_carry(0),
                     ea_carry,
-                    alu_c_in,
+                    status_reg(0),
                     alu_n,
                     alu_z,
                     alu_c,