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+libfpu_a_SOURCES = fpu.cpp fpu_instructions.h \
+ fpu_instructions_x86.h
all: all-am
.SUFFIXES:
+.SUFFIXES: .cpp .o .obj
$(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
exit 1;; \
esac; \
done; \
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+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu src/fpu/Makefile'; \
$(am__cd) $(top_srcdir) && \
- $(AUTOMAKE) --gnu src/cpu/core_normal/Makefile
+ $(AUTOMAKE) --gnu src/fpu/Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \
*config.status*) \
cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
$(am__aclocal_m4_deps):
+clean-noinstLIBRARIES:
+ -test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES)
+
+libfpu.a: $(libfpu_a_OBJECTS) $(libfpu_a_DEPENDENCIES) $(EXTRA_libfpu_a_DEPENDENCIES)
+ $(AM_V_at)-rm -f libfpu.a
+ $(AM_V_AR)$(libfpu_a_AR) libfpu.a $(libfpu_a_OBJECTS) $(libfpu_a_LIBADD)
+ $(AM_V_at)$(RANLIB) libfpu.a
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu.Po@am__quote@ # am--include-marker
+
+$(am__depfiles_remade):
+ @$(MKDIR_P) $(@D)
+ @echo '# dummy' >$@-t && $(am__mv) $@-t $@
+
+am--depfiles: $(am__depfiles_remade)
+
+.cpp.o:
+@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ $(AM_V_CXX)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(AM_V_CXX@am__nodep@)$(CXXCOMPILE) -c -o $@ $<
+
+.cpp.obj:
+@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ $(AM_V_CXX)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(AM_V_CXX@am__nodep@)$(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
ID: $(am__tagged_files)
$(am__define_uniq_tagged_files); mkid -fID $$unique
tags: tags-am
done
check-am: all-am
check: check-am
-all-am: Makefile $(HEADERS)
+all-am: Makefile $(LIBRARIES)
installdirs:
install: install-am
install-exec: install-exec-am
@echo "it deletes files that may require special tools to rebuild."
clean: clean-am
-clean-am: clean-generic mostlyclean-am
+clean-am: clean-generic clean-noinstLIBRARIES mostlyclean-am
distclean: distclean-am
+ -rm -f ./$(DEPDIR)/fpu.Po
-rm -f Makefile
-distclean-am: clean-am distclean-generic distclean-tags
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
dvi: dvi-am
installcheck-am:
maintainer-clean: maintainer-clean-am
+ -rm -f ./$(DEPDIR)/fpu.Po
-rm -f Makefile
maintainer-clean-am: distclean-am maintainer-clean-generic
mostlyclean: mostlyclean-am
-mostlyclean-am: mostlyclean-generic
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
pdf: pdf-am
.MAKE: install-am install-strip
-.PHONY: CTAGS GTAGS TAGS all all-am check check-am clean clean-generic \
- cscopelist-am ctags ctags-am distclean distclean-generic \
+.PHONY: CTAGS GTAGS TAGS all all-am am--depfiles check check-am clean \
+ clean-generic clean-noinstLIBRARIES cscopelist-am ctags \
+ ctags-am distclean distclean-compile distclean-generic \
distclean-tags distdir dvi dvi-am html html-am info info-am \
install install-am install-data install-data-am install-dvi \
install-dvi-am install-exec install-exec-am install-html \
install-pdf install-pdf-am install-ps install-ps-am \
install-strip installcheck installcheck-am installdirs \
maintainer-clean maintainer-clean-generic mostlyclean \
- mostlyclean-generic pdf pdf-am ps ps-am tags tags-am uninstall \
- uninstall-am
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
.PRECIOUS: Makefile
--- /dev/null
+/*
+ * Copyright (C) 2002-2015 The DOSBox Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+
+#include "dosbox.h"
+#if C_FPU
+
+#include <math.h>
+#include <float.h>
+#include "cross.h"
+#include "mem.h"
+#include "fpu.h"
+#include "cpu.h"
+
+FPU_rec fpu;
+
+void FPU_FLDCW(PhysPt addr){
+ Bit16u temp = mem_readw(addr);
+ FPU_SetCW(temp);
+}
+
+Bit16u FPU_GetTag(void){
+ Bit16u tag=0;
+ for(Bitu i=0;i<8;i++)
+ tag |= ( (fpu.tags[i]&3) <<(2*i));
+ return tag;
+}
+
+#if C_FPU_X86
+#include "fpu_instructions_x86.h"
+#else
+#include "fpu_instructions.h"
+#endif
+
+/* WATCHIT : ALWAYS UPDATE REGISTERS BEFORE AND AFTER USING THEM
+ STATUS WORD => FPU_SET_TOP(TOP) BEFORE a read
+ TOP=FPU_GET_TOP() after a write;
+ */
+
+static void EATREE(Bitu _rm){
+ Bitu group=(_rm >> 3) & 7;
+ switch(group){
+ case 0x00: /* FADD */
+ FPU_FADD_EA(TOP);
+ break;
+ case 0x01: /* FMUL */
+ FPU_FMUL_EA(TOP);
+ break;
+ case 0x02: /* FCOM */
+ FPU_FCOM_EA(TOP);
+ break;
+ case 0x03: /* FCOMP */
+ FPU_FCOM_EA(TOP);
+ FPU_FPOP();
+ break;
+ case 0x04: /* FSUB */
+ FPU_FSUB_EA(TOP);
+ break;
+ case 0x05: /* FSUBR */
+ FPU_FSUBR_EA(TOP);
+ break;
+ case 0x06: /* FDIV */
+ FPU_FDIV_EA(TOP);
+ break;
+ case 0x07: /* FDIVR */
+ FPU_FDIVR_EA(TOP);
+ break;
+ default:
+ break;
+ }
+}
+
+void FPU_ESC0_EA(Bitu rm,PhysPt addr) {
+ /* REGULAR TREE WITH 32 BITS REALS */
+ FPU_FLD_F32_EA(addr);
+ EATREE(rm);
+}
+
+void FPU_ESC0_Normal(Bitu rm) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch (group){
+ case 0x00: /* FADD ST,STi */
+ FPU_FADD(TOP,STV(sub));
+ break;
+ case 0x01: /* FMUL ST,STi */
+ FPU_FMUL(TOP,STV(sub));
+ break;
+ case 0x02: /* FCOM STi */
+ FPU_FCOM(TOP,STV(sub));
+ break;
+ case 0x03: /* FCOMP STi */
+ FPU_FCOM(TOP,STV(sub));
+ FPU_FPOP();
+ break;
+ case 0x04: /* FSUB ST,STi */
+ FPU_FSUB(TOP,STV(sub));
+ break;
+ case 0x05: /* FSUBR ST,STi */
+ FPU_FSUBR(TOP,STV(sub));
+ break;
+ case 0x06: /* FDIV ST,STi */
+ FPU_FDIV(TOP,STV(sub));
+ break;
+ case 0x07: /* FDIVR ST,STi */
+ FPU_FDIVR(TOP,STV(sub));
+ break;
+ default:
+ break;
+ }
+}
+
+void FPU_ESC1_EA(Bitu rm,PhysPt addr) {
+// floats
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /* FLD float*/
+ FPU_PREP_PUSH();
+ FPU_FLD_F32(addr,TOP);
+ break;
+ case 0x01: /* UNKNOWN */
+ LOG(LOG_FPU,LOG_WARN)("ESC EA 1:Unhandled group %d subfunction %d",group,sub);
+ break;
+ case 0x02: /* FST float*/
+ FPU_FST_F32(addr);
+ break;
+ case 0x03: /* FSTP float*/
+ FPU_FST_F32(addr);
+ FPU_FPOP();
+ break;
+ case 0x04: /* FLDENV */
+ FPU_FLDENV(addr);
+ break;
+ case 0x05: /* FLDCW */
+ FPU_FLDCW(addr);
+ break;
+ case 0x06: /* FSTENV */
+ FPU_FSTENV(addr);
+ break;
+ case 0x07: /* FNSTCW*/
+ mem_writew(addr,fpu.cw);
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC EA 1:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+}
+
+void FPU_ESC1_Normal(Bitu rm) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch (group){
+ case 0x00: /* FLD STi */
+ {
+ Bitu reg_from=STV(sub);
+ FPU_PREP_PUSH();
+ FPU_FST(reg_from, TOP);
+ break;
+ }
+ case 0x01: /* FXCH STi */
+ FPU_FXCH(TOP,STV(sub));
+ break;
+ case 0x02: /* FNOP */
+ FPU_FNOP();
+ break;
+ case 0x03: /* FSTP STi */
+ FPU_FST(TOP,STV(sub));
+ FPU_FPOP();
+ break;
+ case 0x04:
+ switch(sub){
+ case 0x00: /* FCHS */
+ FPU_FCHS();
+ break;
+ case 0x01: /* FABS */
+ FPU_FABS();
+ break;
+ case 0x02: /* UNKNOWN */
+ case 0x03: /* ILLEGAL */
+ LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
+ break;
+ case 0x04: /* FTST */
+ FPU_FTST();
+ break;
+ case 0x05: /* FXAM */
+ FPU_FXAM();
+ break;
+ case 0x06: /* FTSTP (cyrix)*/
+ case 0x07: /* UNKNOWN */
+ LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
+ break;
+ }
+ break;
+ case 0x05:
+ switch(sub){
+ case 0x00: /* FLD1 */
+ FPU_FLD1();
+ break;
+ case 0x01: /* FLDL2T */
+ FPU_FLDL2T();
+ break;
+ case 0x02: /* FLDL2E */
+ FPU_FLDL2E();
+ break;
+ case 0x03: /* FLDPI */
+ FPU_FLDPI();
+ break;
+ case 0x04: /* FLDLG2 */
+ FPU_FLDLG2();
+ break;
+ case 0x05: /* FLDLN2 */
+ FPU_FLDLN2();
+ break;
+ case 0x06: /* FLDZ*/
+ FPU_FLDZ();
+ break;
+ case 0x07: /* ILLEGAL */
+ LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
+ break;
+ }
+ break;
+ case 0x06:
+ switch(sub){
+ case 0x00: /* F2XM1 */
+ FPU_F2XM1();
+ break;
+ case 0x01: /* FYL2X */
+ FPU_FYL2X();
+ break;
+ case 0x02: /* FPTAN */
+ FPU_FPTAN();
+ break;
+ case 0x03: /* FPATAN */
+ FPU_FPATAN();
+ break;
+ case 0x04: /* FXTRACT */
+ FPU_FXTRACT();
+ break;
+ case 0x05: /* FPREM1 */
+ FPU_FPREM1();
+ break;
+ case 0x06: /* FDECSTP */
+ TOP = (TOP - 1) & 7;
+ break;
+ case 0x07: /* FINCSTP */
+ TOP = (TOP + 1) & 7;
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
+ break;
+ }
+ break;
+ case 0x07:
+ switch(sub){
+ case 0x00: /* FPREM */
+ FPU_FPREM();
+ break;
+ case 0x01: /* FYL2XP1 */
+ FPU_FYL2XP1();
+ break;
+ case 0x02: /* FSQRT */
+ FPU_FSQRT();
+ break;
+ case 0x03: /* FSINCOS */
+ FPU_FSINCOS();
+ break;
+ case 0x04: /* FRNDINT */
+ FPU_FRNDINT();
+ break;
+ case 0x05: /* FSCALE */
+ FPU_FSCALE();
+ break;
+ case 0x06: /* FSIN */
+ FPU_FSIN();
+ break;
+ case 0x07: /* FCOS */
+ FPU_FCOS();
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
+ break;
+ }
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
+ }
+}
+
+
+void FPU_ESC2_EA(Bitu rm,PhysPt addr) {
+ /* 32 bits integer operants */
+ FPU_FLD_I32_EA(addr);
+ EATREE(rm);
+}
+
+void FPU_ESC2_Normal(Bitu rm) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x05:
+ switch(sub){
+ case 0x01: /* FUCOMPP */
+ FPU_FUCOM(TOP,STV(1));
+ FPU_FPOP();
+ FPU_FPOP();
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 2:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 2:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+}
+
+
+void FPU_ESC3_EA(Bitu rm,PhysPt addr) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /* FILD */
+ FPU_PREP_PUSH();
+ FPU_FLD_I32(addr,TOP);
+ break;
+ case 0x01: /* FISTTP */
+ LOG(LOG_FPU,LOG_WARN)("ESC 3 EA:Unhandled group %d subfunction %d",group,sub);
+ break;
+ case 0x02: /* FIST */
+ FPU_FST_I32(addr);
+ break;
+ case 0x03: /* FISTP */
+ FPU_FST_I32(addr);
+ FPU_FPOP();
+ break;
+ case 0x05: /* FLD 80 Bits Real */
+ FPU_PREP_PUSH();
+ FPU_FLD_F80(addr);
+ break;
+ case 0x07: /* FSTP 80 Bits Real */
+ FPU_FST_F80(addr);
+ FPU_FPOP();
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 3 EA:Unhandled group %d subfunction %d",group,sub);
+ }
+}
+
+void FPU_ESC3_Normal(Bitu rm) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch (group) {
+ case 0x04:
+ switch (sub) {
+ case 0x00: //FNENI
+ case 0x01: //FNDIS
+ LOG(LOG_FPU,LOG_ERROR)("8087 only fpu code used esc 3: group 4: subfuntion :%d",sub);
+ break;
+ case 0x02: //FNCLEX FCLEX
+ FPU_FCLEX();
+ break;
+ case 0x03: //FNINIT FINIT
+ FPU_FINIT();
+ break;
+ case 0x04: //FNSETPM
+ case 0x05: //FRSTPM
+// LOG(LOG_FPU,LOG_ERROR)("80267 protected mode (un)set. Nothing done");
+ FPU_FNOP();
+ break;
+ default:
+ E_Exit("ESC 3:ILLEGAL OPCODE group %d subfunction %d",group,sub);
+ }
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 3:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+ return;
+}
+
+
+void FPU_ESC4_EA(Bitu rm,PhysPt addr) {
+ /* REGULAR TREE WITH 64 BITS REALS */
+ FPU_FLD_F64_EA(addr);
+ EATREE(rm);
+}
+
+void FPU_ESC4_Normal(Bitu rm) {
+ /* LOOKS LIKE number 6 without popping */
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /* FADD STi,ST*/
+ FPU_FADD(STV(sub),TOP);
+ break;
+ case 0x01: /* FMUL STi,ST*/
+ FPU_FMUL(STV(sub),TOP);
+ break;
+ case 0x02: /* FCOM*/
+ FPU_FCOM(TOP,STV(sub));
+ break;
+ case 0x03: /* FCOMP*/
+ FPU_FCOM(TOP,STV(sub));
+ FPU_FPOP();
+ break;
+ case 0x04: /* FSUBR STi,ST*/
+ FPU_FSUBR(STV(sub),TOP);
+ break;
+ case 0x05: /* FSUB STi,ST*/
+ FPU_FSUB(STV(sub),TOP);
+ break;
+ case 0x06: /* FDIVR STi,ST*/
+ FPU_FDIVR(STV(sub),TOP);
+ break;
+ case 0x07: /* FDIV STi,ST*/
+ FPU_FDIV(STV(sub),TOP);
+ break;
+ default:
+ break;
+ }
+}
+
+void FPU_ESC5_EA(Bitu rm,PhysPt addr) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /* FLD double real*/
+ FPU_PREP_PUSH();
+ FPU_FLD_F64(addr,TOP);
+ break;
+ case 0x01: /* FISTTP longint*/
+ LOG(LOG_FPU,LOG_WARN)("ESC 5 EA:Unhandled group %d subfunction %d",group,sub);
+ break;
+ case 0x02: /* FST double real*/
+ FPU_FST_F64(addr);
+ break;
+ case 0x03: /* FSTP double real*/
+ FPU_FST_F64(addr);
+ FPU_FPOP();
+ break;
+ case 0x04: /* FRSTOR */
+ FPU_FRSTOR(addr);
+ break;
+ case 0x06: /* FSAVE */
+ FPU_FSAVE(addr);
+ break;
+ case 0x07: /*FNSTSW NG DISAGREES ON THIS*/
+ FPU_SET_TOP(TOP);
+ mem_writew(addr,fpu.sw);
+ //seems to break all dos4gw games :)
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 5 EA:Unhandled group %d subfunction %d",group,sub);
+ }
+}
+
+void FPU_ESC5_Normal(Bitu rm) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /* FFREE STi */
+ fpu.tags[STV(sub)]=TAG_Empty;
+ break;
+ case 0x01: /* FXCH STi*/
+ FPU_FXCH(TOP,STV(sub));
+ break;
+ case 0x02: /* FST STi */
+ FPU_FST(TOP,STV(sub));
+ break;
+ case 0x03: /* FSTP STi*/
+ FPU_FST(TOP,STV(sub));
+ FPU_FPOP();
+ break;
+ case 0x04: /* FUCOM STi */
+ FPU_FUCOM(TOP,STV(sub));
+ break;
+ case 0x05: /*FUCOMP STi */
+ FPU_FUCOM(TOP,STV(sub));
+ FPU_FPOP();
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 5:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+}
+
+void FPU_ESC6_EA(Bitu rm,PhysPt addr) {
+ /* 16 bit (word integer) operants */
+ FPU_FLD_I16_EA(addr);
+ EATREE(rm);
+}
+
+void FPU_ESC6_Normal(Bitu rm) {
+ /* all P variants working only on registers */
+ /* get top before switch and pop afterwards */
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /*FADDP STi,ST*/
+ FPU_FADD(STV(sub),TOP);
+ break;
+ case 0x01: /* FMULP STi,ST*/
+ FPU_FMUL(STV(sub),TOP);
+ break;
+ case 0x02: /* FCOMP5*/
+ FPU_FCOM(TOP,STV(sub));
+ break; /* TODO IS THIS ALLRIGHT ????????? */
+ case 0x03: /*FCOMPP*/
+ if(sub != 1) {
+ LOG(LOG_FPU,LOG_WARN)("ESC 6:Unhandled group %d subfunction %d",group,sub);
+ return;
+ }
+ FPU_FCOM(TOP,STV(1));
+ FPU_FPOP(); /* extra pop at the bottom*/
+ break;
+ case 0x04: /* FSUBRP STi,ST*/
+ FPU_FSUBR(STV(sub),TOP);
+ break;
+ case 0x05: /* FSUBP STi,ST*/
+ FPU_FSUB(STV(sub),TOP);
+ break;
+ case 0x06: /* FDIVRP STi,ST*/
+ FPU_FDIVR(STV(sub),TOP);
+ break;
+ case 0x07: /* FDIVP STi,ST*/
+ FPU_FDIV(STV(sub),TOP);
+ break;
+ default:
+ break;
+ }
+ FPU_FPOP();
+}
+
+
+void FPU_ESC7_EA(Bitu rm,PhysPt addr) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch(group){
+ case 0x00: /* FILD Bit16s */
+ FPU_PREP_PUSH();
+ FPU_FLD_I16(addr,TOP);
+ break;
+ case 0x01:
+ LOG(LOG_FPU,LOG_WARN)("ESC 7 EA:Unhandled group %d subfunction %d",group,sub);
+ break;
+ case 0x02: /* FIST Bit16s */
+ FPU_FST_I16(addr);
+ break;
+ case 0x03: /* FISTP Bit16s */
+ FPU_FST_I16(addr);
+ FPU_FPOP();
+ break;
+ case 0x04: /* FBLD packed BCD */
+ FPU_PREP_PUSH();
+ FPU_FBLD(addr,TOP);
+ break;
+ case 0x05: /* FILD Bit64s */
+ FPU_PREP_PUSH();
+ FPU_FLD_I64(addr,TOP);
+ break;
+ case 0x06: /* FBSTP packed BCD */
+ FPU_FBST(addr);
+ FPU_FPOP();
+ break;
+ case 0x07: /* FISTP Bit64s */
+ FPU_FST_I64(addr);
+ FPU_FPOP();
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 7 EA:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+}
+
+void FPU_ESC7_Normal(Bitu rm) {
+ Bitu group=(rm >> 3) & 7;
+ Bitu sub=(rm & 7);
+ switch (group){
+ case 0x00: /* FFREEP STi*/
+ fpu.tags[STV(sub)]=TAG_Empty;
+ FPU_FPOP();
+ break;
+ case 0x01: /* FXCH STi*/
+ FPU_FXCH(TOP,STV(sub));
+ break;
+ case 0x02: /* FSTP STi*/
+ case 0x03: /* FSTP STi*/
+ FPU_FST(TOP,STV(sub));
+ FPU_FPOP();
+ break;
+ case 0x04:
+ switch(sub){
+ case 0x00: /* FNSTSW AX*/
+ FPU_SET_TOP(TOP);
+ reg_ax = fpu.sw;
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 7:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+ break;
+ default:
+ LOG(LOG_FPU,LOG_WARN)("ESC 7:Unhandled group %d subfunction %d",group,sub);
+ break;
+ }
+}
+
+
+void FPU_Init(Section*) {
+ FPU_FINIT();
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2002-2015 The DOSBox Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+
+
+static void FPU_FINIT(void) {
+ FPU_SetCW(0x37F);
+ fpu.sw = 0;
+ TOP=FPU_GET_TOP();
+ fpu.tags[0] = TAG_Empty;
+ fpu.tags[1] = TAG_Empty;
+ fpu.tags[2] = TAG_Empty;
+ fpu.tags[3] = TAG_Empty;
+ fpu.tags[4] = TAG_Empty;
+ fpu.tags[5] = TAG_Empty;
+ fpu.tags[6] = TAG_Empty;
+ fpu.tags[7] = TAG_Empty;
+ fpu.tags[8] = TAG_Valid; // is only used by us
+}
+
+static void FPU_FCLEX(void){
+ fpu.sw &= 0x7f00; //should clear exceptions
+}
+
+static void FPU_FNOP(void){
+ return;
+}
+
+static void FPU_PREP_PUSH(void){
+ TOP = (TOP - 1) &7;
+ if (GCC_UNLIKELY(fpu.tags[TOP] != TAG_Empty)) E_Exit("FPU stack overflow");
+ fpu.tags[TOP] = TAG_Valid;
+}
+
+static void FPU_PUSH(double in){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = in;
+// LOG(LOG_FPU,LOG_ERROR)("Pushed at %d %g to the stack",newtop,in);
+ return;
+}
+
+
+static void FPU_FPOP(void){
+ if (GCC_UNLIKELY(fpu.tags[TOP] == TAG_Empty)) E_Exit("FPU stack underflow");
+ fpu.tags[TOP]=TAG_Empty;
+ //maybe set zero in it as well
+ TOP = ((TOP+1)&7);
+// LOG(LOG_FPU,LOG_ERROR)("popped from %d %g off the stack",top,fpu.regs[top].d);
+ return;
+}
+
+static double FROUND(double in){
+ switch(fpu.round){
+ case ROUND_Nearest:
+ if (in-floor(in)>0.5) return (floor(in)+1);
+ else if (in-floor(in)<0.5) return (floor(in));
+ else return (((static_cast<Bit64s>(floor(in)))&1)!=0)?(floor(in)+1):(floor(in));
+ break;
+ case ROUND_Down:
+ return (floor(in));
+ break;
+ case ROUND_Up:
+ return (ceil(in));
+ break;
+ case ROUND_Chop:
+ return in; //the cast afterwards will do it right maybe cast here
+ break;
+ default:
+ return in;
+ break;
+ }
+}
+
+#define BIAS80 16383
+#define BIAS64 1023
+
+static Real64 FPU_FLD80(PhysPt addr) {
+ struct {
+ Bit16s begin;
+ FPU_Reg eind;
+ } test;
+ test.eind.l.lower = mem_readd(addr);
+ test.eind.l.upper = mem_readd(addr+4);
+ test.begin = mem_readw(addr+8);
+
+ Bit64s exp64 = (((test.begin&0x7fff) - BIAS80));
+ Bit64s blah = ((exp64 >0)?exp64:-exp64)&0x3ff;
+ Bit64s exp64final = ((exp64 >0)?blah:-blah) +BIAS64;
+
+ Bit64s mant64 = (test.eind.ll >> 11) & LONGTYPE(0xfffffffffffff);
+ Bit64s sign = (test.begin&0x8000)?1:0;
+ FPU_Reg result;
+ result.ll = (sign <<63)|(exp64final << 52)| mant64;
+
+ if(test.eind.l.lower == 0 && test.eind.l.upper == 0x80000000 && (test.begin&0x7fff) == 0x7fff) {
+ //Detect INF and -INF (score 3.11 when drawing a slur.)
+ result.d = sign?-HUGE_VAL:HUGE_VAL;
+ }
+ return result.d;
+
+ //mant64= test.mant80/2***64 * 2 **53
+}
+
+static void FPU_ST80(PhysPt addr,Bitu reg) {
+ struct {
+ Bit16s begin;
+ FPU_Reg eind;
+ } test;
+ Bit64s sign80 = (fpu.regs[reg].ll&LONGTYPE(0x8000000000000000))?1:0;
+ Bit64s exp80 = fpu.regs[reg].ll&LONGTYPE(0x7ff0000000000000);
+ Bit64s exp80final = (exp80>>52);
+ Bit64s mant80 = fpu.regs[reg].ll&LONGTYPE(0x000fffffffffffff);
+ Bit64s mant80final = (mant80 << 11);
+ if(fpu.regs[reg].d != 0){ //Zero is a special case
+ // Elvira wants the 8 and tcalc doesn't
+ mant80final |= LONGTYPE(0x8000000000000000);
+ //Ca-cyber doesn't like this when result is zero.
+ exp80final += (BIAS80 - BIAS64);
+ }
+ test.begin = (static_cast<Bit16s>(sign80)<<15)| static_cast<Bit16s>(exp80final);
+ test.eind.ll = mant80final;
+ mem_writed(addr,test.eind.l.lower);
+ mem_writed(addr+4,test.eind.l.upper);
+ mem_writew(addr+8,test.begin);
+}
+
+
+static void FPU_FLD_F32(PhysPt addr,Bitu store_to) {
+ union {
+ float f;
+ Bit32u l;
+ } blah;
+ blah.l = mem_readd(addr);
+ fpu.regs[store_to].d = static_cast<Real64>(blah.f);
+}
+
+static void FPU_FLD_F64(PhysPt addr,Bitu store_to) {
+ fpu.regs[store_to].l.lower = mem_readd(addr);
+ fpu.regs[store_to].l.upper = mem_readd(addr+4);
+}
+
+static void FPU_FLD_F80(PhysPt addr) {
+ fpu.regs[TOP].d = FPU_FLD80(addr);
+}
+
+static void FPU_FLD_I16(PhysPt addr,Bitu store_to) {
+ Bit16s blah = mem_readw(addr);
+ fpu.regs[store_to].d = static_cast<Real64>(blah);
+}
+
+static void FPU_FLD_I32(PhysPt addr,Bitu store_to) {
+ Bit32s blah = mem_readd(addr);
+ fpu.regs[store_to].d = static_cast<Real64>(blah);
+}
+
+static void FPU_FLD_I64(PhysPt addr,Bitu store_to) {
+ FPU_Reg blah;
+ blah.l.lower = mem_readd(addr);
+ blah.l.upper = mem_readd(addr+4);
+ fpu.regs[store_to].d = static_cast<Real64>(blah.ll);
+}
+
+static void FPU_FBLD(PhysPt addr,Bitu store_to) {
+ Bit64u val = 0;
+ Bitu in = 0;
+ Bit64u base = 1;
+ for(Bitu i = 0;i < 9;i++){
+ in = mem_readb(addr + i);
+ val += ( (in&0xf) * base); //in&0xf shouldn't be higher then 9
+ base *= 10;
+ val += ((( in>>4)&0xf) * base);
+ base *= 10;
+ }
+
+ //last number, only now convert to float in order to get
+ //the best signification
+ Real64 temp = static_cast<Real64>(val);
+ in = mem_readb(addr + 9);
+ temp += ( (in&0xf) * base );
+ if(in&0x80) temp *= -1.0;
+ fpu.regs[store_to].d = temp;
+}
+
+
+static INLINE void FPU_FLD_F32_EA(PhysPt addr) {
+ FPU_FLD_F32(addr,8);
+}
+static INLINE void FPU_FLD_F64_EA(PhysPt addr) {
+ FPU_FLD_F64(addr,8);
+}
+static INLINE void FPU_FLD_I32_EA(PhysPt addr) {
+ FPU_FLD_I32(addr,8);
+}
+static INLINE void FPU_FLD_I16_EA(PhysPt addr) {
+ FPU_FLD_I16(addr,8);
+}
+
+
+static void FPU_FST_F32(PhysPt addr) {
+ union {
+ float f;
+ Bit32u l;
+ } blah;
+ //should depend on rounding method
+ blah.f = static_cast<float>(fpu.regs[TOP].d);
+ mem_writed(addr,blah.l);
+}
+
+static void FPU_FST_F64(PhysPt addr) {
+ mem_writed(addr,fpu.regs[TOP].l.lower);
+ mem_writed(addr+4,fpu.regs[TOP].l.upper);
+}
+
+static void FPU_FST_F80(PhysPt addr) {
+ FPU_ST80(addr,TOP);
+}
+
+static void FPU_FST_I16(PhysPt addr) {
+ mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[TOP].d)));
+}
+
+static void FPU_FST_I32(PhysPt addr) {
+ mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[TOP].d)));
+}
+
+static void FPU_FST_I64(PhysPt addr) {
+ FPU_Reg blah;
+ blah.ll = static_cast<Bit64s>(FROUND(fpu.regs[TOP].d));
+ mem_writed(addr,blah.l.lower);
+ mem_writed(addr+4,blah.l.upper);
+}
+
+static void FPU_FBST(PhysPt addr) {
+ FPU_Reg val = fpu.regs[TOP];
+ bool sign = false;
+ if(fpu.regs[TOP].ll & LONGTYPE(0x8000000000000000)) { //sign
+ sign=true;
+ val.d=-val.d;
+ }
+ //numbers from back to front
+ Real64 temp=val.d;
+ Bitu p;
+ for(Bitu i=0;i<9;i++){
+ val.d=temp;
+ temp = static_cast<Real64>(static_cast<Bit64s>(floor(val.d/10.0)));
+ p = static_cast<Bitu>(val.d - 10.0*temp);
+ val.d=temp;
+ temp = static_cast<Real64>(static_cast<Bit64s>(floor(val.d/10.0)));
+ p |= (static_cast<Bitu>(val.d - 10.0*temp)<<4);
+
+ mem_writeb(addr+i,p);
+ }
+ val.d=temp;
+ temp = static_cast<Real64>(static_cast<Bit64s>(floor(val.d/10.0)));
+ p = static_cast<Bitu>(val.d - 10.0*temp);
+ if(sign)
+ p|=0x80;
+ mem_writeb(addr+9,p);
+}
+
+static void FPU_FADD(Bitu op1, Bitu op2){
+ fpu.regs[op1].d+=fpu.regs[op2].d;
+ //flags and such :)
+ return;
+}
+
+static void FPU_FSIN(void){
+ fpu.regs[TOP].d = sin(fpu.regs[TOP].d);
+ FPU_SET_C2(0);
+ //flags and such :)
+ return;
+}
+
+static void FPU_FSINCOS(void){
+ Real64 temp = fpu.regs[TOP].d;
+ fpu.regs[TOP].d = sin(temp);
+ FPU_PUSH(cos(temp));
+ FPU_SET_C2(0);
+ //flags and such :)
+ return;
+}
+
+static void FPU_FCOS(void){
+ fpu.regs[TOP].d = cos(fpu.regs[TOP].d);
+ FPU_SET_C2(0);
+ //flags and such :)
+ return;
+}
+
+static void FPU_FSQRT(void){
+ fpu.regs[TOP].d = sqrt(fpu.regs[TOP].d);
+ //flags and such :)
+ return;
+}
+static void FPU_FPATAN(void){
+ fpu.regs[STV(1)].d = atan2(fpu.regs[STV(1)].d,fpu.regs[TOP].d);
+ FPU_FPOP();
+ //flags and such :)
+ return;
+}
+static void FPU_FPTAN(void){
+ fpu.regs[TOP].d = tan(fpu.regs[TOP].d);
+ FPU_PUSH(1.0);
+ FPU_SET_C2(0);
+ //flags and such :)
+ return;
+}
+static void FPU_FDIV(Bitu st, Bitu other){
+ fpu.regs[st].d= fpu.regs[st].d/fpu.regs[other].d;
+ //flags and such :)
+ return;
+}
+
+static void FPU_FDIVR(Bitu st, Bitu other){
+ fpu.regs[st].d= fpu.regs[other].d/fpu.regs[st].d;
+ // flags and such :)
+ return;
+}
+
+static void FPU_FMUL(Bitu st, Bitu other){
+ fpu.regs[st].d*=fpu.regs[other].d;
+ //flags and such :)
+ return;
+}
+
+static void FPU_FSUB(Bitu st, Bitu other){
+ fpu.regs[st].d = fpu.regs[st].d - fpu.regs[other].d;
+ //flags and such :)
+ return;
+}
+
+static void FPU_FSUBR(Bitu st, Bitu other){
+ fpu.regs[st].d= fpu.regs[other].d - fpu.regs[st].d;
+ //flags and such :)
+ return;
+}
+
+static void FPU_FXCH(Bitu st, Bitu other){
+ FPU_Tag tag = fpu.tags[other];
+ FPU_Reg reg = fpu.regs[other];
+ fpu.tags[other] = fpu.tags[st];
+ fpu.regs[other] = fpu.regs[st];
+ fpu.tags[st] = tag;
+ fpu.regs[st] = reg;
+}
+
+static void FPU_FST(Bitu st, Bitu other){
+ fpu.tags[other] = fpu.tags[st];
+ fpu.regs[other] = fpu.regs[st];
+}
+
+
+static void FPU_FCOM(Bitu st, Bitu other){
+ if(((fpu.tags[st] != TAG_Valid) && (fpu.tags[st] != TAG_Zero)) ||
+ ((fpu.tags[other] != TAG_Valid) && (fpu.tags[other] != TAG_Zero))){
+ FPU_SET_C3(1);FPU_SET_C2(1);FPU_SET_C0(1);return;
+ }
+ if(fpu.regs[st].d == fpu.regs[other].d){
+ FPU_SET_C3(1);FPU_SET_C2(0);FPU_SET_C0(0);return;
+ }
+ if(fpu.regs[st].d < fpu.regs[other].d){
+ FPU_SET_C3(0);FPU_SET_C2(0);FPU_SET_C0(1);return;
+ }
+ // st > other
+ FPU_SET_C3(0);FPU_SET_C2(0);FPU_SET_C0(0);return;
+}
+
+static void FPU_FUCOM(Bitu st, Bitu other){
+ //does atm the same as fcom
+ FPU_FCOM(st,other);
+}
+
+static void FPU_FRNDINT(void){
+ Bit64s temp= static_cast<Bit64s>(FROUND(fpu.regs[TOP].d));
+ fpu.regs[TOP].d=static_cast<double>(temp);
+}
+
+static void FPU_FPREM(void){
+ Real64 valtop = fpu.regs[TOP].d;
+ Real64 valdiv = fpu.regs[STV(1)].d;
+ Bit64s ressaved = static_cast<Bit64s>( (valtop/valdiv) );
+// Some backups
+// Real64 res=valtop - ressaved*valdiv;
+// res= fmod(valtop,valdiv);
+ fpu.regs[TOP].d = valtop - ressaved*valdiv;
+ FPU_SET_C0(static_cast<Bitu>(ressaved&4));
+ FPU_SET_C3(static_cast<Bitu>(ressaved&2));
+ FPU_SET_C1(static_cast<Bitu>(ressaved&1));
+ FPU_SET_C2(0);
+}
+
+static void FPU_FPREM1(void){
+ Real64 valtop = fpu.regs[TOP].d;
+ Real64 valdiv = fpu.regs[STV(1)].d;
+ double quot = valtop/valdiv;
+ double quotf = floor(quot);
+ Bit64s ressaved;
+ if (quot-quotf>0.5) ressaved = static_cast<Bit64s>(quotf+1);
+ else if (quot-quotf<0.5) ressaved = static_cast<Bit64s>(quotf);
+ else ressaved = static_cast<Bit64s>((((static_cast<Bit64s>(quotf))&1)!=0)?(quotf+1):(quotf));
+ fpu.regs[TOP].d = valtop - ressaved*valdiv;
+ FPU_SET_C0(static_cast<Bitu>(ressaved&4));
+ FPU_SET_C3(static_cast<Bitu>(ressaved&2));
+ FPU_SET_C1(static_cast<Bitu>(ressaved&1));
+ FPU_SET_C2(0);
+}
+
+static void FPU_FXAM(void){
+ if(fpu.regs[TOP].ll & LONGTYPE(0x8000000000000000)) //sign
+ {
+ FPU_SET_C1(1);
+ }
+ else
+ {
+ FPU_SET_C1(0);
+ }
+ if(fpu.tags[TOP] == TAG_Empty)
+ {
+ FPU_SET_C3(1);FPU_SET_C2(0);FPU_SET_C0(1);
+ return;
+ }
+ if(fpu.regs[TOP].d == 0.0) //zero or normalized number.
+ {
+ FPU_SET_C3(1);FPU_SET_C2(0);FPU_SET_C0(0);
+ }
+ else
+ {
+ FPU_SET_C3(0);FPU_SET_C2(1);FPU_SET_C0(0);
+ }
+}
+
+
+static void FPU_F2XM1(void){
+ fpu.regs[TOP].d = pow(2.0,fpu.regs[TOP].d) - 1;
+ return;
+}
+
+static void FPU_FYL2X(void){
+ fpu.regs[STV(1)].d*=log(fpu.regs[TOP].d)/log(static_cast<Real64>(2.0));
+ FPU_FPOP();
+ return;
+}
+
+static void FPU_FYL2XP1(void){
+ fpu.regs[STV(1)].d*=log(fpu.regs[TOP].d+1.0)/log(static_cast<Real64>(2.0));
+ FPU_FPOP();
+ return;
+}
+
+static void FPU_FSCALE(void){
+ fpu.regs[TOP].d *= pow(2.0,static_cast<Real64>(static_cast<Bit64s>(fpu.regs[STV(1)].d)));
+ return; //2^x where x is chopped.
+}
+
+static void FPU_FSTENV(PhysPt addr){
+ FPU_SET_TOP(TOP);
+ if(!cpu.code.big) {
+ mem_writew(addr+0,static_cast<Bit16u>(fpu.cw));
+ mem_writew(addr+2,static_cast<Bit16u>(fpu.sw));
+ mem_writew(addr+4,static_cast<Bit16u>(FPU_GetTag()));
+ } else {
+ mem_writed(addr+0,static_cast<Bit32u>(fpu.cw));
+ mem_writed(addr+4,static_cast<Bit32u>(fpu.sw));
+ mem_writed(addr+8,static_cast<Bit32u>(FPU_GetTag()));
+ }
+}
+
+static void FPU_FLDENV(PhysPt addr){
+ Bit16u tag;
+ Bit32u tagbig;
+ Bitu cw;
+ if(!cpu.code.big) {
+ cw = mem_readw(addr+0);
+ fpu.sw = mem_readw(addr+2);
+ tag = mem_readw(addr+4);
+ } else {
+ cw = mem_readd(addr+0);
+ fpu.sw = (Bit16u)mem_readd(addr+4);
+ tagbig = mem_readd(addr+8);
+ tag = static_cast<Bit16u>(tagbig);
+ }
+ FPU_SetTag(tag);
+ FPU_SetCW(cw);
+ TOP = FPU_GET_TOP();
+}
+
+static void FPU_FSAVE(PhysPt addr){
+ FPU_FSTENV(addr);
+ Bitu start = (cpu.code.big?28:14);
+ for(Bitu i = 0;i < 8;i++){
+ FPU_ST80(addr+start,STV(i));
+ start += 10;
+ }
+ FPU_FINIT();
+}
+
+static void FPU_FRSTOR(PhysPt addr){
+ FPU_FLDENV(addr);
+ Bitu start = (cpu.code.big?28:14);
+ for(Bitu i = 0;i < 8;i++){
+ fpu.regs[STV(i)].d = FPU_FLD80(addr+start);
+ start += 10;
+ }
+}
+
+static void FPU_FXTRACT(void) {
+ // function stores real bias in st and
+ // pushes the significant number onto the stack
+ // if double ever uses a different base please correct this function
+
+ FPU_Reg test = fpu.regs[TOP];
+ Bit64s exp80 = test.ll&LONGTYPE(0x7ff0000000000000);
+ Bit64s exp80final = (exp80>>52) - BIAS64;
+ Real64 mant = test.d / (pow(2.0,static_cast<Real64>(exp80final)));
+ fpu.regs[TOP].d = static_cast<Real64>(exp80final);
+ FPU_PUSH(mant);
+}
+
+static void FPU_FCHS(void){
+ fpu.regs[TOP].d = -1.0*(fpu.regs[TOP].d);
+}
+
+static void FPU_FABS(void){
+ fpu.regs[TOP].d = fabs(fpu.regs[TOP].d);
+}
+
+static void FPU_FTST(void){
+ fpu.regs[8].d = 0.0;
+ FPU_FCOM(TOP,8);
+}
+
+static void FPU_FLD1(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = 1.0;
+}
+
+static void FPU_FLDL2T(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = L2T;
+}
+
+static void FPU_FLDL2E(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = L2E;
+}
+
+static void FPU_FLDPI(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = PI;
+}
+
+static void FPU_FLDLG2(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = LG2;
+}
+
+static void FPU_FLDLN2(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = LN2;
+}
+
+static void FPU_FLDZ(void){
+ FPU_PREP_PUSH();
+ fpu.regs[TOP].d = 0.0;
+ fpu.tags[TOP] = TAG_Zero;
+}
+
+
+static INLINE void FPU_FADD_EA(Bitu op1){
+ FPU_FADD(op1,8);
+}
+static INLINE void FPU_FMUL_EA(Bitu op1){
+ FPU_FMUL(op1,8);
+}
+static INLINE void FPU_FSUB_EA(Bitu op1){
+ FPU_FSUB(op1,8);
+}
+static INLINE void FPU_FSUBR_EA(Bitu op1){
+ FPU_FSUBR(op1,8);
+}
+static INLINE void FPU_FDIV_EA(Bitu op1){
+ FPU_FDIV(op1,8);
+}
+static INLINE void FPU_FDIVR_EA(Bitu op1){
+ FPU_FDIVR(op1,8);
+}
+static INLINE void FPU_FCOM_EA(Bitu op1){
+ FPU_FCOM(op1,8);
+}
+
--- /dev/null
+/*
+ * Copyright (C) 2002-2015 The DOSBox Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+
+
+// #define WEAK_EXCEPTIONS
+
+
+#if defined (_MSC_VER)
+
+#ifdef WEAK_EXCEPTIONS
+#define clx
+#else
+#define clx fclex
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_LOAD(op,szI,szA) \
+ __asm { \
+ __asm mov ebx, store_to \
+ __asm shl ebx, 4 \
+ __asm op szI PTR fpu.p_regs[128].m1 \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ }
+#else
+#define FPUD_LOAD(op,szI,szA) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, 8 \
+ __asm shl eax, 4 \
+ __asm mov ebx, store_to \
+ __asm shl ebx, 4 \
+ __asm fclex \
+ __asm op szI PTR fpu.p_regs[eax].m1 \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_LOAD_EA(op,szI,szA) \
+ __asm { \
+ __asm op szI PTR fpu.p_regs[128].m1 \
+ }
+#else
+#define FPUD_LOAD_EA(op,szI,szA) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, 8 \
+ __asm shl eax, 4 \
+ __asm fclex \
+ __asm op szI PTR fpu.p_regs[eax].m1 \
+ __asm fnstsw new_sw \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_STORE(op,szI,szA) \
+ Bit16u save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm mov eax, TOP \
+ __asm fldcw fpu.cw_mask_all \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm op szI PTR fpu.p_regs[128].m1 \
+ __asm fldcw save_cw \
+ }
+#else
+#define FPUD_STORE(op,szI,szA) \
+ Bit16u new_sw,save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm fldcw fpu.cw_mask_all \
+ __asm mov eax, TOP \
+ __asm shl eax, 4 \
+ __asm mov ebx, 8 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm op szI PTR fpu.p_regs[ebx].m1 \
+ __asm fnstsw new_sw \
+ __asm fldcw save_cw \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fsin,fcos,f2xm1,fchs,fabs
+#define FPUD_TRIG(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm op \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fsincos
+#define FPUD_SINCOS() \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm dec ebx \
+ __asm and ebx, 7 \
+ __asm shl eax, 4 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm fsincos \
+ __asm fnstsw new_sw \
+ __asm mov cx, new_sw \
+ __asm and ch, 0x04 \
+ __asm jnz argument_too_large1 \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm jmp end_sincos \
+ __asm argument_too_large1: \
+ __asm fstp st(0) \
+ __asm end_sincos: \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
+
+// handles fptan
+#define FPUD_PTAN() \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm dec ebx \
+ __asm and ebx, 7 \
+ __asm shl eax, 4 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm fptan \
+ __asm fnstsw new_sw \
+ __asm mov cx, new_sw \
+ __asm and ch, 0x04 \
+ __asm jnz argument_too_large2 \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm jmp end_ptan \
+ __asm argument_too_large2: \
+ __asm fstp st(0) \
+ __asm end_ptan: \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
+
+// handles fxtract
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_XTRACT \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm dec ebx \
+ __asm and ebx, 7 \
+ __asm shl eax, 4 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fxtract \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ } \
+ FPU_PREP_PUSH();
+#else
+#define FPUD_XTRACT \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm dec ebx \
+ __asm and ebx, 7 \
+ __asm shl eax, 4 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fclex \
+ __asm fxtract \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
+ FPU_PREP_PUSH();
+#endif
+
+// handles fadd,fmul,fsub,fsubr
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_ARITH1(op) \
+ Bit16u save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm mov eax, op1 \
+ __asm shl eax, 4 \
+ __asm fldcw fpu.cw_mask_all \
+ __asm mov ebx, op2 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm op st(1), st(0) \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ }
+#else
+#define FPUD_ARITH1(op) \
+ Bit16u new_sw,save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm fldcw fpu.cw_mask_all \
+ __asm mov eax, op1 \
+ __asm shl eax, 4 \
+ __asm mov ebx, op2 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm clx \
+ __asm op st(1), st(0) \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fadd,fmul,fsub,fsubr
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_ARITH1_EA(op) \
+ Bit16u save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm mov eax, op1 \
+ __asm fldcw fpu.cw_mask_all \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fxch \
+ __asm op st(1), st(0) \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ }
+#else
+#define FPUD_ARITH1_EA(op) \
+ Bit16u new_sw,save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm fldcw fpu.cw_mask_all \
+ __asm mov eax, op1 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fxch \
+ __asm clx \
+ __asm op st(1), st(0) \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fsqrt,frndint
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_ARITH2(op) \
+ Bit16u save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm mov eax, TOP \
+ __asm fldcw fpu.cw_mask_all \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm op \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ }
+#else
+#define FPUD_ARITH2(op) \
+ Bit16u new_sw,save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm fldcw fpu.cw_mask_all \
+ __asm mov eax, TOP \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm op \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fdiv,fdivr
+// (This is identical to FPUD_ARITH1 but without a WEAK_EXCEPTIONS variant)
+#define FPUD_ARITH3(op) \
+ Bit16u new_sw,save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm fldcw fpu.cw_mask_all \
+ __asm mov eax, op1 \
+ __asm shl eax, 4 \
+ __asm mov ebx, op2 \
+ __asm shl ebx, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fclex \
+ __asm op st(1), st(0) \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+
+// handles fdiv,fdivr
+// (This is identical to FPUD_ARITH1_EA but without a WEAK_EXCEPTIONS variant)
+#define FPUD_ARITH3_EA(op) \
+ Bit16u new_sw,save_cw; \
+ __asm { \
+ __asm fnstcw save_cw \
+ __asm mov eax, op1 \
+ __asm fldcw fpu.cw_mask_all \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fxch \
+ __asm fclex \
+ __asm op st(1), st(0) \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fldcw save_cw \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+
+// handles fprem,fprem1,fscale
+#define FPUD_REMAINDER(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm inc ebx \
+ __asm and ebx, 7 \
+ __asm shl ebx, 4 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fclex \
+ __asm op \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fstp st(0) \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+
+// handles fcom,fucom
+#define FPUD_COMPARE(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov ebx, op2 \
+ __asm mov eax, op1 \
+ __asm shl ebx, 4 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm op \
+ __asm fnstsw new_sw \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+#define FPUD_COMPARE_EA(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, op1 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm op \
+ __asm fnstsw new_sw \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fxam,ftst
+#define FPUD_EXAMINE(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm clx \
+ __asm op \
+ __asm fnstsw new_sw \
+ __asm fstp st(0) \
+ } \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fpatan,fyl2xp1
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_WITH_POP(op) \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm inc ebx \
+ __asm and ebx, 7 \
+ __asm shl ebx, 4 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm op \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ } \
+ FPU_FPOP();
+#else
+#define FPUD_WITH_POP(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm inc ebx \
+ __asm and ebx, 7 \
+ __asm shl ebx, 4 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fclex \
+ __asm op \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
+ FPU_FPOP();
+#endif
+
+// handles fyl2x
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_FYL2X(op) \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm inc ebx \
+ __asm and ebx, 7 \
+ __asm shl ebx, 4 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm op \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ } \
+ FPU_FPOP();
+#else
+#define FPUD_FYL2X(op) \
+ Bit16u new_sw; \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm mov ebx, eax \
+ __asm inc ebx \
+ __asm and ebx, 7 \
+ __asm shl ebx, 4 \
+ __asm shl eax, 4 \
+ __asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
+ __asm fld TBYTE PTR fpu.p_regs[eax].m1 \
+ __asm fclex \
+ __asm op \
+ __asm fnstsw new_sw \
+ __asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
+ } \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
+ FPU_FPOP();
+#endif
+
+// load math constants
+#define FPUD_LOAD_CONST(op) \
+ FPU_PREP_PUSH(); \
+ __asm { \
+ __asm mov eax, TOP \
+ __asm shl eax, 4 \
+ __asm clx \
+ __asm op \
+ __asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
+ } \
+
+#else
+
+// !defined _MSC_VER
+
+#ifdef WEAK_EXCEPTIONS
+#define clx
+#else
+#define clx "fclex"
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_LOAD(op,szI,szA) \
+ __asm__ volatile ( \
+ #op #szA " %1 \n" \
+ "fstpt %0 " \
+ : "=m" (fpu.p_regs[store_to]) \
+ : "m" (fpu.p_regs[8]) \
+ );
+#else
+#define FPUD_LOAD(op,szI,szA) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fclex \n" \
+ #op #szA " %2 \n" \
+ "fnstsw %0 \n" \
+ "fstpt %1 " \
+ : "=&am" (new_sw), "=m" (fpu.p_regs[store_to]) \
+ : "m" (fpu.p_regs[8]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_LOAD_EA(op,szI,szA) \
+ __asm__ volatile ( \
+ #op #szA " %0 \n" \
+ : \
+ : "m" (fpu.p_regs[8]) \
+ );
+#else
+#define FPUD_LOAD_EA(op,szI,szA) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fclex \n" \
+ #op #szA " %1 \n" \
+ "fnstsw %0 \n" \
+ : "=&am" (new_sw) \
+ : "m" (fpu.p_regs[8]) \
+ : \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_STORE(op,szI,szA) \
+ Bit16u save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %0 \n" \
+ "fldcw %3 \n" \
+ "fldt %2 \n" \
+ #op #szA " %1 \n" \
+ "fldcw %0 " \
+ : "=m" (save_cw), "=m" (fpu.p_regs[8]) \
+ : "m" (fpu.p_regs[TOP]), "m" (fpu.cw_mask_all) \
+ );
+#else
+#define FPUD_STORE(op,szI,szA) \
+ Bit16u new_sw,save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %1 \n" \
+ "fldcw %4 \n" \
+ "fldt %3 \n" \
+ "fclex \n" \
+ #op #szA " %2 \n" \
+ "fnstsw %0 \n" \
+ "fldcw %1 " \
+ : "=&am" (new_sw), "=m" (save_cw), "=m" (fpu.p_regs[8]) \
+ : "m" (fpu.p_regs[TOP]), "m" (fpu.cw_mask_all) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fsin,fcos,f2xm1,fchs,fabs
+#define FPUD_TRIG(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ clx" \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %1 " \
+ : "=&am" (new_sw), "+m" (fpu.p_regs[TOP]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fsincos
+#define FPUD_SINCOS() \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ clx" \n" \
+ "fsincos \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "movw %0, %%ax \n" \
+ "sahf \n" \
+ "jp 1f \n" \
+ "fstpt %1 \n" \
+ "1: " \
+ : "=m" (new_sw), "+m" (fpu.p_regs[TOP]), \
+ "=m" (fpu.p_regs[(TOP-1)&7]) \
+ : \
+ : "ax", "cc" \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
+
+// handles fptan
+#define FPUD_PTAN() \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ clx" \n" \
+ "fptan \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "movw %0, %%ax \n" \
+ "sahf \n" \
+ "jp 1f \n" \
+ "fstpt %1 \n" \
+ "1: " \
+ : "=m" (new_sw), "+m" (fpu.p_regs[TOP]), \
+ "=m" (fpu.p_regs[(TOP-1)&7]) \
+ : \
+ : "ax", "cc" \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
+
+// handles fxtract
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_XTRACT \
+ __asm__ volatile ( \
+ "fldt %0 \n" \
+ "fxtract \n" \
+ "fstpt %1 \n" \
+ "fstpt %0 " \
+ : "+m" (fpu.p_regs[TOP]), "=m" (fpu.p_regs[(TOP-1)&7]) \
+ ); \
+ FPU_PREP_PUSH();
+#else
+#define FPUD_XTRACT \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ "fclex \n" \
+ "fxtract \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "fstpt %1 " \
+ : "=&am" (new_sw), "+m" (fpu.p_regs[TOP]), \
+ "=m" (fpu.p_regs[(TOP-1)&7]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ FPU_PREP_PUSH();
+#endif
+
+// handles fadd,fmul,fsub,fsubr
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_ARITH1(op) \
+ Bit16u save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %0 \n" \
+ "fldcw %3 \n" \
+ "fldt %2 \n" \
+ "fldt %1 \n" \
+ #op" \n" \
+ "fstpt %1 \n" \
+ "fldcw %0 " \
+ : "=m" (save_cw), "+m" (fpu.p_regs[op1]) \
+ : "m" (fpu.p_regs[op2]), "m" (fpu.cw_mask_all) \
+ );
+#else
+#define FPUD_ARITH1(op) \
+ Bit16u new_sw,save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %1 \n" \
+ "fldcw %4 \n" \
+ "fldt %3 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "fldcw %1 " \
+ : "=&am" (new_sw), "=m" (save_cw), "+m" (fpu.p_regs[op1]) \
+ : "m" (fpu.p_regs[op2]), "m" (fpu.cw_mask_all) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fadd,fmul,fsub,fsubr
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_ARITH1_EA(op) \
+ Bit16u save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %0 \n" \
+ "fldcw %2 \n" \
+ "fldt %1 \n" \
+ #op" \n" \
+ "fstpt %1 \n" \
+ "fldcw %0 " \
+ : "=m" (save_cw), "+m" (fpu.p_regs[op1]) \
+ : "m" (fpu.cw_mask_all) \
+ );
+#else
+#define FPUD_ARITH1_EA(op) \
+ Bit16u new_sw,save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %1 \n" \
+ "fldcw %3 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "fldcw %1 " \
+ : "=&am" (new_sw), "=m" (save_cw), "+m" (fpu.p_regs[op1]) \
+ : "m" (fpu.cw_mask_all) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fsqrt,frndint
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_ARITH2(op) \
+ Bit16u save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %0 \n" \
+ "fldcw %2 \n" \
+ "fldt %1 \n" \
+ #op" \n" \
+ "fstpt %1 \n" \
+ "fldcw %0 " \
+ : "=m" (save_cw), "+m" (fpu.p_regs[TOP]) \
+ : "m" (fpu.cw_mask_all) \
+ );
+#else
+#define FPUD_ARITH2(op) \
+ Bit16u new_sw,save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %1 \n" \
+ "fldcw %3 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "fldcw %1 " \
+ : "=&am" (new_sw), "=m" (save_cw), "+m" (fpu.p_regs[TOP]) \
+ : "m" (fpu.cw_mask_all) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+#endif
+
+// handles fdiv,fdivr
+// (This is identical to FPUD_ARITH1 but without a WEAK_EXCEPTIONS variant)
+#define FPUD_ARITH3(op) \
+ Bit16u new_sw,save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %1 \n" \
+ "fldcw %4 \n" \
+ "fldt %3 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "fldcw %1 " \
+ : "=&am" (new_sw), "=m" (save_cw), "+m" (fpu.p_regs[op1]) \
+ : "m" (fpu.p_regs[op2]), "m" (fpu.cw_mask_all) \
+ ); \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+
+// handles fdiv,fdivr
+// (This is identical to FPUD_ARITH1_EA but without a WEAK_EXCEPTIONS variant)
+#define FPUD_ARITH3_EA(op) \
+ Bit16u new_sw,save_cw; \
+ __asm__ volatile ( \
+ "fnstcw %1 \n" \
+ "fldcw %3 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %2 \n" \
+ "fldcw %1 " \
+ : "=&am" (new_sw), "=m" (save_cw), "+m" (fpu.p_regs[op1]) \
+ : "m" (fpu.cw_mask_all) \
+ ); \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+
+// handles fprem,fprem1,fscale
+#define FPUD_REMAINDER(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %2 \n" \
+ "fldt %1 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %1 \n" \
+ "fstp %%st(0) " \
+ : "=&am" (new_sw), "+m" (fpu.p_regs[TOP]) \
+ : "m" (fpu.p_regs[(TOP+1)&7]) \
+ ); \
+ fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
+
+// handles fcom,fucom
+#define FPUD_COMPARE(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %2 \n" \
+ "fldt %1 \n" \
+ clx" \n" \
+ #op" \n" \
+ "fnstsw %0 " \
+ : "=&am" (new_sw) \
+ : "m" (fpu.p_regs[op1]), "m" (fpu.p_regs[op2]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fcom,fucom
+#define FPUD_COMPARE_EA(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ clx" \n" \
+ #op" \n" \
+ "fnstsw %0 " \
+ : "=&am" (new_sw) \
+ : "m" (fpu.p_regs[op1]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fxam,ftst
+#define FPUD_EXAMINE(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ clx" \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstp %%st(0) " \
+ : "=&am" (new_sw) \
+ : "m" (fpu.p_regs[TOP]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
+
+// handles fpatan,fyl2xp1
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_WITH_POP(op) \
+ __asm__ volatile ( \
+ "fldt %0 \n" \
+ "fldt %1 \n" \
+ #op" \n" \
+ "fstpt %0 \n" \
+ : "+m" (fpu.p_regs[(TOP+1)&7]) \
+ : "m" (fpu.p_regs[TOP]) \
+ ); \
+ FPU_FPOP();
+#else
+#define FPUD_WITH_POP(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %1 \n" \
+ : "=&am" (new_sw), "+m" (fpu.p_regs[(TOP+1)&7]) \
+ : "m" (fpu.p_regs[TOP]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ FPU_FPOP();
+#endif
+
+// handles fyl2x
+#ifdef WEAK_EXCEPTIONS
+#define FPUD_FYL2X(op) \
+ __asm__ volatile ( \
+ "fldt %0 \n" \
+ "fldt %1 \n" \
+ #op" \n" \
+ "fstpt %0 \n" \
+ : "+m" (fpu.p_regs[(TOP+1)&7]) \
+ : "m" (fpu.p_regs[TOP]) \
+ ); \
+ FPU_FPOP();
+#else
+#define FPUD_FYL2X(op) \
+ Bit16u new_sw; \
+ __asm__ volatile ( \
+ "fldt %1 \n" \
+ "fldt %2 \n" \
+ "fclex \n" \
+ #op" \n" \
+ "fnstsw %0 \n" \
+ "fstpt %1 \n" \
+ : "=&am" (new_sw), "+m" (fpu.p_regs[(TOP+1)&7]) \
+ : "m" (fpu.p_regs[TOP]) \
+ ); \
+ fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
+ FPU_FPOP();
+#endif
+
+// load math constants
+#define FPUD_LOAD_CONST(op) \
+ FPU_PREP_PUSH(); \
+ __asm__ volatile ( \
+ clx" \n" \
+ #op" \n" \
+ "fstpt %0 \n" \
+ : "=m" (fpu.p_regs[TOP]) \
+ );
+
+#endif
+
+#ifdef WEAK_EXCEPTIONS
+const Bit16u exc_mask=0x7f00;
+#else
+const Bit16u exc_mask=0xffbf;
+#endif
+
+static void FPU_FINIT(void) {
+ FPU_SetCW(0x37F);
+ fpu.sw=0;
+ TOP=FPU_GET_TOP();
+ fpu.tags[0]=TAG_Empty;
+ fpu.tags[1]=TAG_Empty;
+ fpu.tags[2]=TAG_Empty;
+ fpu.tags[3]=TAG_Empty;
+ fpu.tags[4]=TAG_Empty;
+ fpu.tags[5]=TAG_Empty;
+ fpu.tags[6]=TAG_Empty;
+ fpu.tags[7]=TAG_Empty;
+ fpu.tags[8]=TAG_Valid; // is only used by us
+}
+
+static void FPU_FCLEX(void){
+ fpu.sw&=0x7f00; //should clear exceptions
+}
+
+static void FPU_FNOP(void){
+}
+
+static void FPU_PREP_PUSH(void){
+ TOP = (TOP - 1) &7;
+ if (GCC_UNLIKELY(fpu.tags[TOP] != TAG_Empty)) E_Exit("FPU stack overflow");
+ fpu.tags[TOP] = TAG_Valid;
+}
+
+static void FPU_FPOP(void){
+ if (GCC_UNLIKELY(fpu.tags[TOP] == TAG_Empty)) E_Exit("FPU stack underflow");
+ fpu.tags[TOP] = TAG_Empty;
+ TOP = ((TOP+1)&7);
+}
+
+static void FPU_FLD_F32(PhysPt addr,Bitu store_to) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ FPUD_LOAD(fld,DWORD,s)
+}
+
+static void FPU_FLD_F32_EA(PhysPt addr) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ FPUD_LOAD_EA(fld,DWORD,s)
+}
+
+static void FPU_FLD_F64(PhysPt addr,Bitu store_to) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ fpu.p_regs[8].m2 = mem_readd(addr+4);
+ FPUD_LOAD(fld,QWORD,l)
+}
+
+static void FPU_FLD_F64_EA(PhysPt addr) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ fpu.p_regs[8].m2 = mem_readd(addr+4);
+ FPUD_LOAD_EA(fld,QWORD,l)
+}
+
+static void FPU_FLD_F80(PhysPt addr) {
+ fpu.p_regs[TOP].m1 = mem_readd(addr);
+ fpu.p_regs[TOP].m2 = mem_readd(addr+4);
+ fpu.p_regs[TOP].m3 = mem_readw(addr+8);
+ FPU_SET_C1(0);
+}
+
+static void FPU_FLD_I16(PhysPt addr,Bitu store_to) {
+ fpu.p_regs[8].m1 = (Bit32u)mem_readw(addr);
+ FPUD_LOAD(fild,WORD,s)
+}
+
+static void FPU_FLD_I16_EA(PhysPt addr) {
+ fpu.p_regs[8].m1 = (Bit32u)mem_readw(addr);
+ FPUD_LOAD_EA(fild,WORD,s)
+}
+
+static void FPU_FLD_I32(PhysPt addr,Bitu store_to) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ FPUD_LOAD(fild,DWORD,l)
+}
+
+static void FPU_FLD_I32_EA(PhysPt addr) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ FPUD_LOAD_EA(fild,DWORD,l)
+}
+
+static void FPU_FLD_I64(PhysPt addr,Bitu store_to) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ fpu.p_regs[8].m2 = mem_readd(addr+4);
+ FPUD_LOAD(fild,QWORD,q)
+}
+
+static void FPU_FBLD(PhysPt addr,Bitu store_to) {
+ fpu.p_regs[8].m1 = mem_readd(addr);
+ fpu.p_regs[8].m2 = mem_readd(addr+4);
+ fpu.p_regs[8].m3 = mem_readw(addr+8);
+ FPUD_LOAD(fbld,TBYTE,)
+}
+
+static void FPU_FST_F32(PhysPt addr) {
+ FPUD_STORE(fstp,DWORD,s)
+ mem_writed(addr,fpu.p_regs[8].m1);
+}
+
+static void FPU_FST_F64(PhysPt addr) {
+ FPUD_STORE(fstp,QWORD,l)
+ mem_writed(addr,fpu.p_regs[8].m1);
+ mem_writed(addr+4,fpu.p_regs[8].m2);
+}
+
+static void FPU_FST_F80(PhysPt addr) {
+ mem_writed(addr,fpu.p_regs[TOP].m1);
+ mem_writed(addr+4,fpu.p_regs[TOP].m2);
+ mem_writew(addr+8,fpu.p_regs[TOP].m3);
+ FPU_SET_C1(0);
+}
+
+static void FPU_FST_I16(PhysPt addr) {
+ FPUD_STORE(fistp,WORD,s)
+ mem_writew(addr,(Bit16u)fpu.p_regs[8].m1);
+}
+
+static void FPU_FST_I32(PhysPt addr) {
+ FPUD_STORE(fistp,DWORD,l)
+ mem_writed(addr,fpu.p_regs[8].m1);
+}
+
+static void FPU_FST_I64(PhysPt addr) {
+ FPUD_STORE(fistp,QWORD,q)
+ mem_writed(addr,fpu.p_regs[8].m1);
+ mem_writed(addr+4,fpu.p_regs[8].m2);
+}
+
+static void FPU_FBST(PhysPt addr) {
+ FPUD_STORE(fbstp,TBYTE,)
+ mem_writed(addr,fpu.p_regs[8].m1);
+ mem_writed(addr+4,fpu.p_regs[8].m2);
+ mem_writew(addr+8,fpu.p_regs[8].m3);
+}
+
+
+static void FPU_FSIN(void){
+ FPUD_TRIG(fsin)
+}
+
+static void FPU_FSINCOS(void){
+ FPUD_SINCOS()
+}
+
+static void FPU_FCOS(void){
+ FPUD_TRIG(fcos)
+}
+
+static void FPU_FSQRT(void){
+ FPUD_ARITH2(fsqrt)
+}
+
+static void FPU_FPATAN(void){
+ FPUD_WITH_POP(fpatan)
+}
+
+static void FPU_FPTAN(void){
+ FPUD_PTAN()
+}
+
+
+static void FPU_FADD(Bitu op1, Bitu op2){
+ FPUD_ARITH1(faddp)
+}
+
+static void FPU_FADD_EA(Bitu op1){
+ FPUD_ARITH1_EA(faddp)
+}
+
+static void FPU_FDIV(Bitu op1, Bitu op2){
+ FPUD_ARITH3(fdivp)
+}
+
+static void FPU_FDIV_EA(Bitu op1){
+ FPUD_ARITH3_EA(fdivp)
+}
+
+static void FPU_FDIVR(Bitu op1, Bitu op2){
+ FPUD_ARITH3(fdivrp)
+}
+
+static void FPU_FDIVR_EA(Bitu op1){
+ FPUD_ARITH3_EA(fdivrp)
+}
+
+static void FPU_FMUL(Bitu op1, Bitu op2){
+ FPUD_ARITH1(fmulp)
+}
+
+static void FPU_FMUL_EA(Bitu op1){
+ FPUD_ARITH1_EA(fmulp)
+}
+
+static void FPU_FSUB(Bitu op1, Bitu op2){
+ FPUD_ARITH1(fsubp)
+}
+
+static void FPU_FSUB_EA(Bitu op1){
+ FPUD_ARITH1_EA(fsubp)
+}
+
+static void FPU_FSUBR(Bitu op1, Bitu op2){
+ FPUD_ARITH1(fsubrp)
+}
+
+static void FPU_FSUBR_EA(Bitu op1){
+ FPUD_ARITH1_EA(fsubrp)
+}
+
+static void FPU_FXCH(Bitu stv, Bitu other){
+ FPU_Tag tag = fpu.tags[other];
+ fpu.tags[other] = fpu.tags[stv];
+ fpu.tags[stv] = tag;
+
+ Bit32u m1s = fpu.p_regs[other].m1;
+ Bit32u m2s = fpu.p_regs[other].m2;
+ Bit16u m3s = fpu.p_regs[other].m3;
+ fpu.p_regs[other].m1 = fpu.p_regs[stv].m1;
+ fpu.p_regs[other].m2 = fpu.p_regs[stv].m2;
+ fpu.p_regs[other].m3 = fpu.p_regs[stv].m3;
+ fpu.p_regs[stv].m1 = m1s;
+ fpu.p_regs[stv].m2 = m2s;
+ fpu.p_regs[stv].m3 = m3s;
+
+ FPU_SET_C1(0);
+}
+
+static void FPU_FST(Bitu stv, Bitu other){
+ fpu.tags[other] = fpu.tags[stv];
+
+ fpu.p_regs[other].m1 = fpu.p_regs[stv].m1;
+ fpu.p_regs[other].m2 = fpu.p_regs[stv].m2;
+ fpu.p_regs[other].m3 = fpu.p_regs[stv].m3;
+
+ FPU_SET_C1(0);
+}
+
+
+static void FPU_FCOM(Bitu op1, Bitu op2){
+ FPUD_COMPARE(fcompp)
+}
+
+static void FPU_FCOM_EA(Bitu op1){
+ FPUD_COMPARE_EA(fcompp)
+}
+
+static void FPU_FUCOM(Bitu op1, Bitu op2){
+ FPUD_COMPARE(fucompp)
+}
+
+static void FPU_FRNDINT(void){
+ FPUD_ARITH2(frndint)
+}
+
+static void FPU_FPREM(void){
+ FPUD_REMAINDER(fprem)
+}
+
+static void FPU_FPREM1(void){
+ FPUD_REMAINDER(fprem1)
+}
+
+static void FPU_FXAM(void){
+ FPUD_EXAMINE(fxam)
+ // handle empty registers (C1 set to sign in any way!)
+ if(fpu.tags[TOP] == TAG_Empty) {
+ FPU_SET_C3(1);FPU_SET_C2(0);FPU_SET_C0(1);
+ return;
+ }
+}
+
+static void FPU_F2XM1(void){
+ FPUD_TRIG(f2xm1)
+}
+
+static void FPU_FYL2X(void){
+ FPUD_FYL2X(fyl2x)
+}
+
+static void FPU_FYL2XP1(void){
+ FPUD_WITH_POP(fyl2xp1)
+}
+
+static void FPU_FSCALE(void){
+ FPUD_REMAINDER(fscale)
+}
+
+
+static void FPU_FSTENV(PhysPt addr){
+ FPU_SET_TOP(TOP);
+ if(!cpu.code.big) {
+ mem_writew(addr+0,static_cast<Bit16u>(fpu.cw));
+ mem_writew(addr+2,static_cast<Bit16u>(fpu.sw));
+ mem_writew(addr+4,static_cast<Bit16u>(FPU_GetTag()));
+ } else {
+ mem_writed(addr+0,static_cast<Bit32u>(fpu.cw));
+ mem_writed(addr+4,static_cast<Bit32u>(fpu.sw));
+ mem_writed(addr+8,static_cast<Bit32u>(FPU_GetTag()));
+ }
+}
+
+static void FPU_FLDENV(PhysPt addr){
+ Bit16u tag;
+ Bit32u tagbig;
+ Bitu cw;
+ if(!cpu.code.big) {
+ cw = mem_readw(addr+0);
+ fpu.sw = mem_readw(addr+2);
+ tag = mem_readw(addr+4);
+ } else {
+ cw = mem_readd(addr+0);
+ fpu.sw = (Bit16u)mem_readd(addr+4);
+ tagbig = mem_readd(addr+8);
+ tag = static_cast<Bit16u>(tagbig);
+ }
+ FPU_SetTag(tag);
+ FPU_SetCW(cw);
+ TOP=FPU_GET_TOP();
+}
+
+static void FPU_FSAVE(PhysPt addr){
+ FPU_FSTENV(addr);
+ Bitu start=(cpu.code.big?28:14);
+ for(Bitu i=0;i<8;i++){
+ mem_writed(addr+start,fpu.p_regs[STV(i)].m1);
+ mem_writed(addr+start+4,fpu.p_regs[STV(i)].m2);
+ mem_writew(addr+start+8,fpu.p_regs[STV(i)].m3);
+ start+=10;
+ }
+ FPU_FINIT();
+}
+
+static void FPU_FRSTOR(PhysPt addr){
+ FPU_FLDENV(addr);
+ Bitu start=(cpu.code.big?28:14);
+ for(Bitu i=0;i<8;i++){
+ fpu.p_regs[STV(i)].m1 = mem_readd(addr+start);
+ fpu.p_regs[STV(i)].m2 = mem_readd(addr+start+4);
+ fpu.p_regs[STV(i)].m3 = mem_readw(addr+start+8);
+ start+=10;
+ }
+}
+
+
+static void FPU_FXTRACT(void) {
+ FPUD_XTRACT
+}
+
+static void FPU_FCHS(void){
+ FPUD_TRIG(fchs)
+}
+
+static void FPU_FABS(void){
+ FPUD_TRIG(fabs)
+}
+
+static void FPU_FTST(void){
+ FPUD_EXAMINE(ftst)
+}
+
+static void FPU_FLD1(void){
+ FPUD_LOAD_CONST(fld1)
+}
+
+static void FPU_FLDL2T(void){
+ FPUD_LOAD_CONST(fldl2t)
+}
+
+static void FPU_FLDL2E(void){
+ FPUD_LOAD_CONST(fldl2e)
+}
+
+static void FPU_FLDPI(void){
+ FPUD_LOAD_CONST(fldpi)
+}
+
+static void FPU_FLDLG2(void){
+ FPUD_LOAD_CONST(fldlg2)
+}
+
+static void FPU_FLDLN2(void){
+ FPUD_LOAD_CONST(fldln2)
+}
+
+static void FPU_FLDZ(void){
+ FPUD_LOAD_CONST(fldz)
+ fpu.tags[TOP]=TAG_Zero;
+}
+++ /dev/null
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