[X86][RDSEED] Split off i64 intrinsic tests and test i16/i32 on 32-bit target as...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306961 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/rdseed-x86_64.ll b/test/CodeGen/X86/rdseed-x86_64.ll
new file mode 100644 (file)
index 0000000..b0d9748
--- /dev/null
+++ b/test/CodeGen/X86/rdseed-x86_64.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s
+
+declare {i64, i32} @llvm.x86.rdseed.64()
+
+define i32 @_rdseed64_step(i64* %random_val) {
+; CHECK-LABEL: _rdseed64_step:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    rdseedq %rcx
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovael %ecx, %eax
+; CHECK-NEXT:    movq %rcx, (%rdi)
+; CHECK-NEXT:    retq
+  %call = call {i64, i32} @llvm.x86.rdseed.64()
+  %randval = extractvalue {i64, i32} %call, 0
+  store i64 %randval, i64* %random_val
+  %isvalid = extractvalue {i64, i32} %call, 1
+  ret i32 %isvalid
+}

diff --git a/test/CodeGen/X86/rdseed.ll b/test/CodeGen/X86/rdseed.ll
index c219b4a..b22e3e7 100644 (file)
--- a/test/CodeGen/X86/rdseed.ll
+++ b/test/CodeGen/X86/rdseed.ll
@@ -1,48 +1,56 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s --check-prefix=X64
 
 declare {i16, i32} @llvm.x86.rdseed.16()
 declare {i32, i32} @llvm.x86.rdseed.32()
-declare {i64, i32} @llvm.x86.rdseed.64()
 
 define i32 @_rdseed16_step(i16* %random_val) {
+; X86-LABEL: _rdseed16_step:
+; X86:       # BB#0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    rdseedw %ax
+; X86-NEXT:    movzwl %ax, %edx
+; X86-NEXT:    movl $1, %eax
+; X86-NEXT:    cmovael %edx, %eax
+; X86-NEXT:    movw %dx, (%ecx)
+; X86-NEXT:    retl
+;
+; X64-LABEL: _rdseed16_step:
+; X64:       # BB#0:
+; X64-NEXT:    rdseedw %ax
+; X64-NEXT:    movzwl %ax, %ecx
+; X64-NEXT:    movl $1, %eax
+; X64-NEXT:    cmovael %ecx, %eax
+; X64-NEXT:    movw %cx, (%rdi)
+; X64-NEXT:    retq
   %call = call {i16, i32} @llvm.x86.rdseed.16()
   %randval = extractvalue {i16, i32} %call, 0
   store i16 %randval, i16* %random_val
   %isvalid = extractvalue {i16, i32} %call, 1
   ret i32 %isvalid
-; CHECK-LABEL: _rdseed16_step:
-; CHECK: rdseedw       %ax
-; CHECK: movzwl        %ax, %ecx
-; CHECK: movl  $1, %eax
-; CHECK: cmovael       %ecx, %eax
-; CHECK: movw  %cx, (%r[[A0:di|cx]])
-; CHECK: ret
 }
 
 define i32 @_rdseed32_step(i32* %random_val) {
+; X86-LABEL: _rdseed32_step:
+; X86:       # BB#0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    rdseedl %edx
+; X86-NEXT:    movl $1, %eax
+; X86-NEXT:    cmovael %edx, %eax
+; X86-NEXT:    movl %edx, (%ecx)
+; X86-NEXT:    retl
+;
+; X64-LABEL: _rdseed32_step:
+; X64:       # BB#0:
+; X64-NEXT:    rdseedl %ecx
+; X64-NEXT:    movl $1, %eax
+; X64-NEXT:    cmovael %ecx, %eax
+; X64-NEXT:    movl %ecx, (%rdi)
+; X64-NEXT:    retq
   %call = call {i32, i32} @llvm.x86.rdseed.32()
   %randval = extractvalue {i32, i32} %call, 0
   store i32 %randval, i32* %random_val
   %isvalid = extractvalue {i32, i32} %call, 1
   ret i32 %isvalid
-; CHECK-LABEL: _rdseed32_step:
-; CHECK: rdseedl       %e[[T0:[a-z]+]]
-; CHECK: movl  $1, %eax
-; CHECK: cmovael       %e[[T0]], %eax
-; CHECK: movl  %e[[T0]], (%r[[A0]])
-; CHECK: ret
-}
-
-define i32 @_rdseed64_step(i64* %random_val) {
-  %call = call {i64, i32} @llvm.x86.rdseed.64()
-  %randval = extractvalue {i64, i32} %call, 0
-  store i64 %randval, i64* %random_val
-  %isvalid = extractvalue {i64, i32} %call, 1
-  ret i32 %isvalid
-; CHECK-LABEL: _rdseed64_step:
-; CHECK: rdseedq       %r[[T1:[a-z]+]]
-; CHECK: movl  $1, %eax
-; CHECK: cmovael       %e[[T1]], %eax
-; CHECK: movq  %r[[T1]], (%r[[A0]])
-; CHECK: ret
 }