/* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers */
#ifdef TARGET_ARM
-static inline int regpairs_aligned(void *cpu_env) {
+static inline int regpairs_aligned(void *cpu_env, int num)
+{
return ((((CPUARMState *)cpu_env)->eabi) == 1) ;
}
#elif defined(TARGET_MIPS) && (TARGET_ABI_BITS == 32)
-static inline int regpairs_aligned(void *cpu_env) { return 1; }
+static inline int regpairs_aligned(void *cpu_env, int num) { return 1; }
#elif defined(TARGET_PPC) && !defined(TARGET_PPC64)
/* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs
* of registers which translates to the same as ARM/MIPS, because we start with
* r3 as arg1 */
-static inline int regpairs_aligned(void *cpu_env) { return 1; }
+static inline int regpairs_aligned(void *cpu_env, int num) { return 1; }
+#elif defined(TARGET_SH4)
+/* SH4 doesn't align register pairs, except for p{read,write}64 */
+static inline int regpairs_aligned(void *cpu_env, int num)
+{
+ switch (num) {
+ case TARGET_NR_pread64:
+ case TARGET_NR_pwrite64:
+ return 1;
+
+ default:
+ return 0;
+ }
+}
#else
-static inline int regpairs_aligned(void *cpu_env) { return 0; }
+static inline int regpairs_aligned(void *cpu_env, int num) { return 0; }
#endif
#define ERRNO_TABLE_SIZE 1200
abi_long arg3,
abi_long arg4)
{
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, TARGET_NR_truncate64)) {
arg2 = arg3;
arg3 = arg4;
}
abi_long arg3,
abi_long arg4)
{
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, TARGET_NR_ftruncate64)) {
arg2 = arg3;
arg3 = arg4;
}
#endif
#ifdef TARGET_NR_pread64
case TARGET_NR_pread64:
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, num)) {
arg4 = arg5;
arg5 = arg6;
}
unlock_user(p, arg2, ret);
break;
case TARGET_NR_pwrite64:
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, num)) {
arg4 = arg5;
arg5 = arg6;
}
arg6 = ret;
#else
/* 6 args: fd, offset (high, low), len (high, low), advice */
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, num)) {
/* offset is in (3,4), len in (5,6) and advice in 7 */
arg2 = arg3;
arg3 = arg4;
#ifdef TARGET_NR_fadvise64
case TARGET_NR_fadvise64:
/* 5 args: fd, offset (high, low), len, advice */
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, num)) {
/* offset is in (3,4), len in 5 and advice in 6 */
arg2 = arg3;
arg3 = arg4;
#ifdef TARGET_NR_readahead
case TARGET_NR_readahead:
#if TARGET_ABI_BITS == 32
- if (regpairs_aligned(cpu_env)) {
+ if (regpairs_aligned(cpu_env, num)) {
arg2 = arg3;
arg3 = arg4;
arg4 = arg5;