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net/mlx5: DR, Add misc5 to match_param structs
authorMuhammad Sammar <muhammads@nvidia.com>
Sun, 5 Sep 2021 11:54:59 +0000 (14:54 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 31 Dec 2021 08:17:27 +0000 (00:17 -0800)
Add misc5 match params to enable matching tunnel headers.

Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h

index 12ebb7a..856541a 100644 (file)
@@ -424,6 +424,9 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher,
        if (matcher->match_criteria & DR_MATCHER_CRITERIA_MISC4)
                mask.misc4 = matcher->mask.misc4;
 
+       if (matcher->match_criteria & DR_MATCHER_CRITERIA_MISC5)
+               mask.misc5 = matcher->mask.misc5;
+
        ret = mlx5dr_ste_build_pre_check(dmn, matcher->match_criteria,
                                         &matcher->mask, NULL);
        if (ret)
index 3b4cd31..43e7fe8 100644 (file)
@@ -974,6 +974,16 @@ static bool dr_rule_verify(struct mlx5dr_matcher *matcher,
                        return false;
                }
        }
+
+       if (match_criteria & DR_MATCHER_CRITERIA_MISC5) {
+               s_idx = offsetof(struct mlx5dr_match_param, misc5);
+               e_idx = min(s_idx + sizeof(param->misc5), value_size);
+
+               if (!dr_rule_cmp_value_to_mask(mask_p, param_p, s_idx, e_idx)) {
+                       mlx5dr_err(matcher->tbl->dmn, "Rule misc5 parameters contains a value not specified by mask\n");
+                       return false;
+               }
+       }
        return true;
 }
 
index 219a547..9bf2523 100644 (file)
@@ -880,6 +880,26 @@ static void dr_ste_copy_mask_misc4(char *mask, struct mlx5dr_match_misc4 *spec,
                IFC_GET_CLR(fte_match_set_misc4, mask, prog_sample_field_value_3, clr);
 }
 
+static void dr_ste_copy_mask_misc5(char *mask, struct mlx5dr_match_misc5 *spec, bool clr)
+{
+       spec->macsec_tag_0 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, macsec_tag_0, clr);
+       spec->macsec_tag_1 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, macsec_tag_1, clr);
+       spec->macsec_tag_2 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, macsec_tag_2, clr);
+       spec->macsec_tag_3 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, macsec_tag_3, clr);
+       spec->tunnel_header_0 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, tunnel_header_0, clr);
+       spec->tunnel_header_1 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, tunnel_header_1, clr);
+       spec->tunnel_header_2 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, tunnel_header_2, clr);
+       spec->tunnel_header_3 =
+               IFC_GET_CLR(fte_match_set_misc5, mask, tunnel_header_3, clr);
+}
+
 void mlx5dr_ste_copy_param(u8 match_criteria,
                           struct mlx5dr_match_param *set_param,
                           struct mlx5dr_match_parameters *mask,
@@ -966,6 +986,20 @@ void mlx5dr_ste_copy_param(u8 match_criteria,
                }
                dr_ste_copy_mask_misc4(buff, &set_param->misc4, clr);
        }
+
+       param_location += sizeof(struct mlx5dr_match_misc4);
+
+       if (match_criteria & DR_MATCHER_CRITERIA_MISC5) {
+               if (mask->match_sz < param_location +
+                   sizeof(struct mlx5dr_match_misc5)) {
+                       memcpy(tail_param, data + param_location,
+                              mask->match_sz - param_location);
+                       buff = tail_param;
+               } else {
+                       buff = data + param_location;
+               }
+               dr_ste_copy_mask_misc5(buff, &set_param->misc5, clr);
+       }
 }
 
 void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx,
index 584d2b0..b498782 100644 (file)
@@ -105,7 +105,8 @@ enum mlx5dr_matcher_criteria {
        DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
        DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
        DR_MATCHER_CRITERIA_MISC4 = 1 << 5,
-       DR_MATCHER_CRITERIA_MAX = 1 << 6,
+       DR_MATCHER_CRITERIA_MISC5 = 1 << 6,
+       DR_MATCHER_CRITERIA_MAX = 1 << 7,
 };
 
 enum mlx5dr_action_type {
@@ -762,6 +763,17 @@ struct mlx5dr_match_misc4 {
        u32 reserved_auto1[8];
 };
 
+struct mlx5dr_match_misc5 {
+       u32 macsec_tag_0;
+       u32 macsec_tag_1;
+       u32 macsec_tag_2;
+       u32 macsec_tag_3;
+       u32 tunnel_header_0;
+       u32 tunnel_header_1;
+       u32 tunnel_header_2;
+       u32 tunnel_header_3;
+};
+
 struct mlx5dr_match_param {
        struct mlx5dr_match_spec outer;
        struct mlx5dr_match_misc misc;
@@ -769,6 +781,7 @@ struct mlx5dr_match_param {
        struct mlx5dr_match_misc2 misc2;
        struct mlx5dr_match_misc3 misc3;
        struct mlx5dr_match_misc4 misc4;
+       struct mlx5dr_match_misc5 misc5;
 };
 
 #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \