clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clock

Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.

CRs-Fixed: 1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c
index 3e2eb0d..e9af651 100644 (file)
--- a/drivers/clk/msm/clock-gcc-cobalt.c
+++ b/drivers/clk/msm/clock-gcc-cobalt.c
@@ -1070,16 +1070,6 @@ static struct branch_clk gcc_hdmi_clkref_clk = {
        },
 };
 
-static struct reset_clk gcc_pcie_0_phy_reset = {
-       .reset_reg = GCC_PCIE_0_PHY_BCR,
-       .base = &virt_base,
-       .c = {
-               .dbg_name = "gcc_pcie_0_phy_reset",
-               .ops = &clk_ops_rst,
-               CLK_INIT(gcc_pcie_0_phy_reset.c),
-       },
-};
-
 static struct branch_clk gcc_pcie_clkref_clk = {
        .cbcr_reg = GCC_PCIE_CLKREF_EN,
        .has_sibling = 1,
@@ -1802,14 +1792,15 @@ static struct branch_clk gcc_pcie_0_mstr_axi_clk = {
        },
 };
 
-static struct gate_clk gcc_pcie_0_pipe_clk = {
-       .en_reg = GCC_PCIE_0_PIPE_CBCR,
-       .en_mask = BIT(0),
-       .delay_us = 500,
+static struct branch_clk gcc_pcie_0_pipe_clk = {
+       .cbcr_reg = GCC_PCIE_0_PIPE_CBCR,
+       .bcr_reg = GCC_PCIE_0_PHY_BCR,
+       .has_sibling = 1,
+       .halt_check = DELAY,
        .base = &virt_base,
        .c = {
                .dbg_name = "gcc_pcie_0_pipe_clk",
-               .ops = &clk_ops_gate,
+               .ops = &clk_ops_branch,
                CLK_INIT(gcc_pcie_0_pipe_clk.c),
        },
 };
@@ -2611,7 +2602,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
        CLK_LIST(usb3_phy_aux_clk_src),
        CLK_LIST(hmss_gpll0_clk_src),
        CLK_LIST(qspi_ref_clk_src),
-       CLK_LIST(gcc_pcie_0_phy_reset),
        CLK_LIST(gcc_usb3_phy_reset),
        CLK_LIST(gcc_usb3phy_phy_reset),
        CLK_LIST(gcc_qusb2phy_prim_reset),

diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h
index 99df0d5..607bcfb 100644 (file)
--- a/include/dt-bindings/clock/msm-clocks-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-cobalt.h
@@ -256,7 +256,6 @@
 #define clk_gcc_pcie_clkref_clk                        0xa2e247fa
 #define clk_gcc_rx2_qlink_clkref_clk           0xd0ba986d
 #define clk_gcc_rx1_usb2_clkref_clk            0x53351d25
-#define clk_gcc_pcie_0_phy_reset               0xdc3201c1
 #define clk_gcc_pcie_phy_reset                 0x9bc3c959
 #define clk_gcc_pcie_phy_com_reset             0x8bf513e6
 #define clk_gcc_pcie_phy_nocsr_com_phy_reset   0x0c16a2da