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rtw88: 8822ce: set CLKREQ# signal to low during suspend
authorChin-Yen Lee <timlee@realtek.com>
Tue, 27 Jul 2021 10:05:03 +0000 (18:05 +0800)
committerKalle Valo <kvalo@codeaurora.org>
Sat, 21 Aug 2021 19:18:45 +0000 (22:18 +0300)
We find the power sequence of system suspend flow don't meet
the criteria when using 8822CE-VR chip by rfe-type 6, because the
reference clock form host is sometimes late. To avoid the behavoir,
we keep CLKREQ# signal to low during suspend to make sure the reference
clock arrival in time.

Signed-off-by: Chin-Yen Lee <timlee@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20210727100503.31626-1-pkshih@realtek.com
drivers/net/wireless/realtek/rtw88/pci.c
drivers/net/wireless/realtek/rtw88/pci.h

index e7d17ab..0f95a95 100644 (file)
@@ -1359,6 +1359,25 @@ static void rtw_pci_clkreq_set(struct rtw_dev *rtwdev, bool enable)
        rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
 }
 
+static void rtw_pci_clkreq_pad_low(struct rtw_dev *rtwdev, bool enable)
+{
+       u8 value;
+       int ret;
+
+       ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value);
+       if (ret) {
+               rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret);
+               return;
+       }
+
+       if (enable)
+               value &= ~BIT_CLKREQ_N_PAD;
+       else
+               value |= BIT_CLKREQ_N_PAD;
+
+       rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
+}
+
 static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable)
 {
        u8 value;
@@ -1500,11 +1519,25 @@ static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev)
 
 static int __maybe_unused rtw_pci_suspend(struct device *dev)
 {
+       struct ieee80211_hw *hw = dev_get_drvdata(dev);
+       struct rtw_dev *rtwdev = hw->priv;
+       struct rtw_chip_info *chip = rtwdev->chip;
+       struct rtw_efuse *efuse = &rtwdev->efuse;
+
+       if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6)
+               rtw_pci_clkreq_pad_low(rtwdev, true);
        return 0;
 }
 
 static int __maybe_unused rtw_pci_resume(struct device *dev)
 {
+       struct ieee80211_hw *hw = dev_get_drvdata(dev);
+       struct rtw_dev *rtwdev = hw->priv;
+       struct rtw_chip_info *chip = rtwdev->chip;
+       struct rtw_efuse *efuse = &rtwdev->efuse;
+
+       if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6)
+               rtw_pci_clkreq_pad_low(rtwdev, false);
        return 0;
 }
 
index 0ffae88..66f78eb 100644 (file)
@@ -37,6 +37,7 @@
 #define RTK_PCIE_LINK_CFG      0x0719
 #define BIT_CLKREQ_SW_EN       BIT(4)
 #define BIT_L1_SW_EN           BIT(3)
+#define BIT_CLKREQ_N_PAD       BIT(0)
 #define RTK_PCIE_CLKDLY_CTRL   0x0725
 
 #define BIT_PCI_BCNQ_FLAG      BIT(4)