claim ST(x) registers are 80 bits, which is true. This doesn't affect

codegen yet because these can't be spilled (they don't exist until after RA).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 9d70618..cb376c0 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -488,7 +488,7 @@ def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>
 // Floating point stack registers (these are not allocatable by the
 // register allocator - the floating point stackifier is responsible
 // for transforming FPn allocations to STn registers)
-def RST : RegisterClass<"X86", [f64], 32,
+def RST : RegisterClass<"X86", [f80], 32,
                         [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
     let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;