set_location_assignment PIN_L1 -to base_clk\r
set_location_assignment PIN_R22 -to rst_n\r
set_location_assignment PIN_T18 -to dbg_addr[4]\r
-set_location_assignment PIN_R20 -to dbg_addr[0]\r
+#set_location_assignment PIN_R20 -to dbg_addr[0]\r
set_location_assignment PIN_R19 -to dbg_addr[1]\r
set_location_assignment PIN_U15 -to dbg_addr[2]\r
set_location_assignment PIN_Y19 -to dbg_addr[3]\r
-set_location_assignment PIN_D12 -to base_clk_27mhz\r
+set_location_assignment PIN_A12 -to base_clk_24mhz\r
\r
##DRAM\r
set_location_assignment PIN_W4 -to dram_addr[0]\r
set_location_assignment PIN_M5 -to dram_udqm\r
set_location_assignment PIN_R8 -to dram_we_n\r
\r
+###LED\r
+set_location_assignment PIN_R20 -to red_led\r
+set_location_assignment PIN_U22 -to green_led\r
+\r
+\r
set_global_assignment -name ENABLE_SIGNALTAP ON\r
-set_global_assignment -name USE_SIGNALTAP_FILE stp3.stp\r
+set_global_assignment -name USE_SIGNALTAP_FILE "sdram-test.stp"\r
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to dram_clk -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[0]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[10]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[11]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[12]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[13]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[14]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[15]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[16]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[17]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[18]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[19]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[1]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[20]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[21]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[2]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[3]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[4]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[5]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[6]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[7]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[8]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[9]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "vga_ctl:vga_ctl_inst|wbs_cyc_i" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[0]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[10]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[11]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[12]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[13]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[14]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[15]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[1]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[2]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[3]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[4]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[5]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[6]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[7]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[8]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[9]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "vga_ctl:vga_ctl_inst|wbs_stb_i" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[0]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[1]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[2]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[3]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[4]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[5]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[6]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[7]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "vga_ctl:vga_ctl_inst|wbs_we_i" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[0]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[10]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[11]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[12]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[13]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[14]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[15]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[16]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[17]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[18]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[19]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[1]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[20]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[21]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[2]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[3]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[4]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[5]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[6]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[7]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[8]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[9]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "vga_ctl:vga_ctl_inst|wbs_cyc_i" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[0]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[10]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[11]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[12]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[13]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[14]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[15]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[1]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[2]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[3]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[4]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[5]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[6]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[7]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[8]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[9]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "vga_ctl:vga_ctl_inst|wbs_stb_i" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[0]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[1]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[2]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[3]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[4]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[5]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[6]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[7]" -section_id auto_signaltap_0\r
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "vga_ctl:vga_ctl_inst|wbs_we_i" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=49" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=49" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=168" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=54940" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=17220" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0\r
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0\r
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0\r
+set_global_assignment -name VHDL_FILE vga_clk_gen.vhd\r
+set_global_assignment -name VHDL_FILE sdram_rw.vhd\r
set_global_assignment -name VHDL_FILE sdram_controller.vhd\r
set_global_assignment -name QIP_FILE sdram_write_fifo.qip\r
set_global_assignment -name VHDL_FILE motonesfpga_common.vhd\r
set_global_assignment -name VHDL_FILE clock_divider.vhd\r
set_global_assignment -name VHDL_FILE vga.vhd\r
set_global_assignment -name VHDL_FILE qt_proj_test5.vhd\r
-set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/tools/qt_proj_test5/stp3_auto_stripped.stp"\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to rst_n -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=1" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to green_led -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to red_led -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to rst_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "sdram_rw:sdr_rw|clk_i" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "sdram_rw:sdr_rw|cmd_ack" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "sdram_rw:sdr_rw|cmd_done" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "sdram_rw:sdr_rw|cur_st_o[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "sdram_rw:sdr_rw|cur_st_o[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "sdram_rw:sdr_rw|cur_st_o[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "sdram_rw:sdr_rw|cur_st_o[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "sdram_rw:sdr_rw|sdram_val_o[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "sdram_rw:sdr_rw|sdram_val_o[10]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "sdram_rw:sdr_rw|sdram_val_o[11]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram_rw:sdr_rw|sdram_val_o[12]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram_rw:sdr_rw|sdram_val_o[13]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram_rw:sdr_rw|sdram_val_o[14]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram_rw:sdr_rw|sdram_val_o[15]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram_rw:sdr_rw|sdram_val_o[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram_rw:sdr_rw|sdram_val_o[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram_rw:sdr_rw|sdram_val_o[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram_rw:sdr_rw|sdram_val_o[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram_rw:sdr_rw|sdram_val_o[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram_rw:sdr_rw|sdram_val_o[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram_rw:sdr_rw|sdram_val_o[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram_rw:sdr_rw|sdram_val_o[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram_rw:sdr_rw|sdram_val_o[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram_rw:sdr_rw|wbm_ack_i" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram_rw:sdr_rw|wbm_adr_o[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram_rw:sdr_rw|wbm_adr_o[10]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram_rw:sdr_rw|wbm_adr_o[11]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram_rw:sdr_rw|wbm_adr_o[12]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram_rw:sdr_rw|wbm_adr_o[13]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram_rw:sdr_rw|wbm_adr_o[14]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram_rw:sdr_rw|wbm_adr_o[15]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram_rw:sdr_rw|wbm_adr_o[16]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram_rw:sdr_rw|wbm_adr_o[17]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram_rw:sdr_rw|wbm_adr_o[18]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram_rw:sdr_rw|wbm_adr_o[19]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram_rw:sdr_rw|wbm_adr_o[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram_rw:sdr_rw|wbm_adr_o[20]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram_rw:sdr_rw|wbm_adr_o[21]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram_rw:sdr_rw|wbm_adr_o[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram_rw:sdr_rw|wbm_adr_o[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram_rw:sdr_rw|wbm_adr_o[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram_rw:sdr_rw|wbm_adr_o[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram_rw:sdr_rw|wbm_adr_o[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram_rw:sdr_rw|wbm_adr_o[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram_rw:sdr_rw|wbm_adr_o[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram_rw:sdr_rw|wbm_adr_o[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram_rw:sdr_rw|wbm_cyc_o" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram_rw:sdr_rw|wbm_dat_i[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram_rw:sdr_rw|wbm_dat_i[10]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram_rw:sdr_rw|wbm_dat_i[11]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram_rw:sdr_rw|wbm_dat_i[12]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram_rw:sdr_rw|wbm_dat_i[13]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram_rw:sdr_rw|wbm_dat_i[14]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram_rw:sdr_rw|wbm_dat_i[15]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sdram_rw:sdr_rw|wbm_dat_i[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sdram_rw:sdr_rw|wbm_dat_i[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sdram_rw:sdr_rw|wbm_dat_i[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "sdram_rw:sdr_rw|wbm_dat_i[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "sdram_rw:sdr_rw|wbm_dat_i[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "sdram_rw:sdr_rw|wbm_dat_i[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "sdram_rw:sdr_rw|wbm_dat_i[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "sdram_rw:sdr_rw|wbm_dat_i[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "sdram_rw:sdr_rw|wbm_dat_i[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "sdram_rw:sdr_rw|wbm_dat_o[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "sdram_rw:sdr_rw|wbm_dat_o[10]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "sdram_rw:sdr_rw|wbm_dat_o[11]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "sdram_rw:sdr_rw|wbm_dat_o[12]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "sdram_rw:sdr_rw|wbm_dat_o[13]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "sdram_rw:sdr_rw|wbm_dat_o[14]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "sdram_rw:sdr_rw|wbm_dat_o[15]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "sdram_rw:sdr_rw|wbm_dat_o[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "sdram_rw:sdr_rw|wbm_dat_o[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "sdram_rw:sdr_rw|wbm_dat_o[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "sdram_rw:sdr_rw|wbm_dat_o[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "sdram_rw:sdr_rw|wbm_dat_o[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "sdram_rw:sdr_rw|wbm_dat_o[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "sdram_rw:sdr_rw|wbm_dat_o[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "sdram_rw:sdr_rw|wbm_dat_o[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "sdram_rw:sdr_rw|wbm_dat_o[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "sdram_rw:sdr_rw|wbm_stall_i" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "sdram_rw:sdr_rw|wbm_stb_o" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "sdram_rw:sdr_rw|wbm_tga_o[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "sdram_rw:sdr_rw|wbm_tga_o[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "sdram_rw:sdr_rw|wbm_tga_o[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "sdram_rw:sdr_rw|wbm_tga_o[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "sdram_rw:sdr_rw|wbm_tga_o[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "sdram_rw:sdr_rw|wbm_tga_o[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "sdram_rw:sdr_rw|wbm_tga_o[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "sdram_rw:sdr_rw|wbm_tga_o[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "sdram_rw:sdr_rw|writing" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=110" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=28" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0\r
+set_global_assignment -name SIGNALTAP_FILE "sdram-test.stp"\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to base_clk_24mhz -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "sdram_rw:sdr_rw|mem_val_o[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "sdram_rw:sdr_rw|mem_val_o[10]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "sdram_rw:sdr_rw|mem_val_o[11]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "sdram_rw:sdr_rw|mem_val_o[12]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "sdram_rw:sdr_rw|mem_val_o[13]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "sdram_rw:sdr_rw|mem_val_o[14]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "sdram_rw:sdr_rw|mem_val_o[15]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "sdram_rw:sdr_rw|mem_val_o[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "sdram_rw:sdr_rw|mem_val_o[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "sdram_rw:sdr_rw|mem_val_o[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "sdram_rw:sdr_rw|mem_val_o[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "sdram_rw:sdr_rw|mem_val_o[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "sdram_rw:sdr_rw|mem_val_o[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "sdram_rw:sdr_rw|mem_val_o[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "sdram_rw:sdr_rw|mem_val_o[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "sdram_rw:sdr_rw|mem_val_o[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "sdram_rw:sdr_rw|wbm_we_i" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=15338" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=11008" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/tools/qt_proj_test5/sdram-test_auto_stripped.stp"\r
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
-- All of the components are assembled and instanciated on this board.\r
-- \r
\r
+\r
entity qt_proj_test5 is \r
port (\r
\r
: out std_logic;\r
signal dbg_bst_cnt : out std_logic_vector(7 downto 0);\r
\r
+ signal green_led : out std_logic; --Test passed\r
+ signal red_led : out std_logic; --Test fail\r
+\r
base_clk : in std_logic;\r
- base_clk_27mhz : in std_logic;\r
+ base_clk_24mhz : in std_logic;\r
rst_n : in std_logic;\r
h_sync_n : out std_logic;\r
v_sync_n : out std_logic;\r
\r
architecture rtl of qt_proj_test5 is\r
\r
+component sdram_controller \r
+ generic\r
+ (\r
+ reset_polarity_g : std_logic := '0' --When rst = reset_polarity_g, system is in RESET mode\r
+ );\r
+ port (\r
+ --Clocks and Reset \r
+ clk_i : in std_logic; --Wishbone input clock\r
+ rst : in std_logic; --Reset\r
+ pll_locked : in std_logic; --PLL Locked indication, for CKE (Clock Enable) signal to SDRAM\r
+ \r
+ --SDRAM Signals\r
+ dram_addr : out std_logic_vector (11 downto 0); --Address (12 bit)\r
+ dram_bank : out std_logic_vector (1 downto 0); --Bank\r
+ dram_cas_n : out std_logic; --Column Address is being transmitted\r
+ dram_cke : out std_logic; --Clock Enable\r
+ dram_cs_n : out std_logic; --Chip Select (Here - Mask commands)\r
+ dram_dq : inout std_logic_vector (15 downto 0); --Data in / Data out\r
+ dram_ldqm : out std_logic; --Byte masking\r
+ dram_udqm : out std_logic; --Byte masking\r
+ dram_ras_n : out std_logic; --Row Address is being transmitted\r
+ dram_we_n : out std_logic; --Write Enable\r
+ \r
+ -- Wishbone Slave signals to Read/Write interface\r
+ wbs_adr_i : in std_logic_vector (21 downto 0); --Address (Bank, Row, Col)\r
+ wbs_dat_i : in std_logic_vector (15 downto 0); --Data In (16 bits)\r
+ wbs_we_i : in std_logic; --Write Enable\r
+ wbs_tga_i : in std_logic_vector (7 downto 0); --Address Tag : Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
+ wbs_cyc_i : in std_logic; --Cycle Command from interface\r
+ wbs_stb_i : in std_logic; --Strobe Command from interface\r
+ wbs_dat_o : out std_logic_vector (15 downto 0); --Data Out (16 bits)\r
+ wbs_stall_o : out std_logic; --Slave is not ready to receive new data\r
+ wbs_err_o : out std_logic; --Error flag: OOR Burst. Burst length is greater that 256-column address\r
+ wbs_ack_o : out std_logic; --When Read Burst: DATA bus must be valid in this cycle\r
+ --When Write Burst: Data has been read from SDRAM and is valid\r
+\r
+ --Debug signals\r
+ cmd_ack : out std_logic; --Command has been acknowledged\r
+ cmd_done : out std_logic; --Command has finished (read/write)\r
+ init_st_o : out std_logic_vector (3 downto 0); --Current init state\r
+ main_st_o : out std_logic_vector (3 downto 0) --Current main state\r
+ );\r
+end component;\r
+\r
+component sdram_rw \r
+ generic(\r
+ reset_polarity : std_logic := '0' --When rst = reset_polarity, system at RESET\r
+ );\r
+ port(\r
+ --Clock and Reset\r
+ clk_i : in std_logic; --WISHBONE Clock\r
+ rst : in std_logic; --RESET\r
+ \r
+ --Signals to SDRAM controller\r
+ wbm_adr_o : out std_logic_vector (21 downto 0); --Address to read from / write to\r
+ wbm_dat_i : in std_logic_vector (15 downto 0); --Data out (to SDRAM)\r
+ wbm_dat_o : out std_logic_vector (15 downto 0); --Data in (from SDRAM)\r
+ wbm_we_i : out std_logic; --'1' - Write, '0' - Read\r
+ wbm_tga_o : out std_logic_vector (7 downto 0); --Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
+ wbm_cyc_o : out std_logic; --Transmit command to SDRAM controller\r
+ wbm_stb_o : out std_logic; --Transmit command to SDRAM controller\r
+ wbm_stall_i : in std_logic; --When '1', write data to SDRAM\r
+ wbm_ack_i : in std_logic; --when '1', data is ready to be read from SDRAM\r
+ \r
+ --Debug and test signals\r
+ cmd_ack : in std_logic; --Command has been acknowledged by SDRAM controller\r
+ cmd_done : in std_logic; --Command has finished (read/write)\r
+ green_led : out std_logic; --Test passed\r
+ red_led : out std_logic; --Test fail\r
+ writing : out std_logic; --'1' when writing, '0' when reading\r
+ mem_val_o : out std_logic_vector (15 downto 0); --Memory value written / compared to SDRAM\r
+ sdram_val_o : out std_logic_vector (15 downto 0); --Read value from SDRAM\r
+ cur_st_o : out std_logic_vector (3 downto 0) --Current state\r
+ );\r
+end component;\r
+\r
+component sdram_model\r
+ GENERIC (\r
+ addr_bits : INTEGER := 12;\r
+ data_bits : INTEGER := 16 ;\r
+ col_bits : INTEGER := 8\r
+ );\r
+ PORT (\r
+ Dq : inout std_logic_vector (15 downto 0) := (others => 'Z');\r
+ Addr : in std_logic_vector (11 downto 0) ;-- := (others => '0');\r
+ Ba : in std_logic_vector(1 downto 0);-- := "00";\r
+ Clk : in std_logic ;--:= '0';\r
+ Cke : in std_logic ;--:= '0';\r
+ Cs : in std_logic ;--:= '1';\r
+ Ras : in std_logic ;--:= '0';\r
+ Cas : in std_logic ;--:= '0';\r
+ We : in std_logic ;--:= '0';\r
+ Dqm : in std_logic_vector(1 downto 0)-- := (others => 'Z')\r
+ );\r
+ \r
+END component;\r
+\r
+component vga_clk_gen\r
+ PORT\r
+ (\r
+ inclk0 : IN STD_LOGIC := '0';\r
+ c0 : OUT STD_LOGIC ;\r
+ locked : OUT STD_LOGIC \r
+ );\r
+end component;\r
+\r
+--Clock and Reset\r
+signal clk_133 : std_logic := '0'; --133 MHz\r
+signal rst : std_logic := '0'; --Reset\r
+\r
+----SDRAM Signals\r
+--signal dram_addr : std_logic_vector (11 downto 0);\r
+--signal dram_bank : std_logic_vector (1 downto 0);\r
+--signal dram_cas_n : std_logic;\r
+--signal dram_cke : std_logic;\r
+--signal dram_cs_n : std_logic;\r
+--signal dram_dq : std_logic_vector (15 downto 0);\r
+--signal dram_ldqm : std_logic;\r
+--signal dram_udqm : std_logic;\r
+--signal dram_ras_n : std_logic;\r
+--signal dram_we_n : std_logic;\r
+\r
+--Read / Write signals to SDRAM\r
+signal addr : std_logic_vector (21 downto 0);\r
+signal dat_tb2ram : std_logic_vector (15 downto 0);\r
+signal dat_ram2tb : std_logic_vector (15 downto 0);\r
+signal we_i : std_logic;\r
+signal stall_i : std_logic;\r
+signal cyc_o : std_logic;\r
+signal err_o : std_logic;\r
+signal ack_i : std_logic;\r
+signal stb_o : std_logic;\r
+signal burst_len : std_logic_vector (7 downto 0);\r
+signal cmd_ack : std_logic;\r
+signal cmd_done : std_logic;\r
+\r
+--LEDs\r
+--signal green_led : std_logic;\r
+--signal red_led : std_logic;\r
+signal writing : std_logic;\r
+\r
+--States\r
+signal init_st_o : std_logic_vector (3 downto 0);\r
+signal main_st_o : std_logic_vector (3 downto 0);\r
+\r
+--Debug\r
+signal cur_st_o : std_logic_vector (3 downto 0);\r
+\r
+signal sdram_clk, pll_locked : std_logic;\r
+begin\r
+ --Clock process\r
+ vga_clk_gen_inst : vga_clk_gen\r
+ PORT map\r
+ (\r
+ --sdram_clk = 133.3333 MHz.\r
+ base_clk, sdram_clk, pll_locked\r
+ );\r
+ clk_proc:\r
+ clk_133 <= sdram_clk;\r
+ \r
+ rst_proc:\r
+ rst <= rst_n;\r
+ \r
+ --Componenets:\r
+ sdr_ctrl : sdram_controller generic map (\r
+ reset_polarity_g => '0'\r
+ )\r
+ port map(\r
+ clk_i => clk_133,\r
+ rst => rst,\r
+ pll_locked => pll_locked,\r
+ \r
+ dram_addr => dram_addr, \r
+ dram_bank => dram_bank, \r
+ dram_cas_n => dram_cas_n, \r
+ dram_cke => dram_cke, \r
+ dram_cs_n => dram_cs_n, \r
+ dram_dq => dram_dq, \r
+ dram_ldqm => dram_ldqm, \r
+ dram_udqm => dram_udqm, \r
+ dram_ras_n => dram_ras_n, \r
+ dram_we_n => dram_we_n, \r
+ \r
+ wbs_adr_i => addr, \r
+ wbs_dat_i => dat_tb2ram, \r
+ wbs_we_i => we_i, \r
+ wbs_tga_i => burst_len, \r
+ wbs_cyc_i => cyc_o,\r
+ wbs_stb_i => stb_o, \r
+ wbs_dat_o => dat_ram2tb,\r
+ wbs_stall_o => stall_i,\r
+ wbs_err_o => err_o,\r
+ wbs_ack_o => ack_i,\r
+ \r
+ cmd_ack => cmd_ack,\r
+ cmd_done => cmd_done,\r
+ init_st_o => init_st_o,\r
+ main_st_o => main_st_o\r
+ );\r
+ \r
+ sdr_rw : sdram_rw port map (\r
+ clk_i => clk_133,\r
+ rst => rst,\r
+ \r
+ wbm_adr_o => addr,\r
+ wbm_dat_i => dat_ram2tb,\r
+ wbm_dat_o => dat_tb2ram,\r
+ wbm_we_i => we_i,\r
+ wbm_tga_o => burst_len,\r
+ wbm_cyc_o => cyc_o,\r
+ wbm_stb_o => stb_o,\r
+ wbm_stall_i => stall_i,\r
+ wbm_ack_i => ack_i,\r
+\r
+ cmd_ack => cmd_ack,\r
+ cmd_done => cmd_done,\r
+ green_led => green_led,\r
+ red_led => red_led,\r
+ writing => writing\r
+ );\r
+-- sdram_model_inst : sdram_model port map (\r
+-- Dq => dram_dq, \r
+-- Addr => dram_addr,\r
+-- Ba => dram_bank,\r
+-- Clk => clk_133,\r
+-- Cke => dram_cke,\r
+-- Cs => dram_cs_n,\r
+-- Ras => dram_ras_n,\r
+-- Cas => dram_cas_n,\r
+-- We => dram_we_n,\r
+-- Dqm(0) => dram_ldqm,\r
+-- Dqm(1) => dram_udqm\r
+-- );\r
+ \r
+end architecture rtl;\r
+\r
+--------------------------------------------------------------------\r
+--------------------------------------------------------------------\r
+--------------------------------------------------------------------\r
+--------------------------------------------------------------------\r
+--------------------------------------------------------------------\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.conv_integer;\r
+\r
+entity qt_proj_test5_old is \r
+ port (\r
+\r
+ signal dbg_cpu_clk : out std_logic;\r
+ signal dbg_ppu_clk : out std_logic;\r
+ signal dbg_mem_clk : out std_logic;\r
+ signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);\r
+ signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);\r
+\r
+-- signal dbg_status : out std_logic_vector(7 downto 0);\r
+-- signal dbg_dec_oe_n : out std_logic;\r
+-- signal dbg_dec_val : out std_logic_vector (7 downto 0);\r
+-- signal dbg_int_dbus : out std_logic_vector (7 downto 0);\r
+-- signal dbg_status_val : out std_logic_vector (7 downto 0);\r
+-- signal dbg_stat_we_n : out std_logic;\r
+ \r
+---monitor inside cpu\r
+-- signal dbg_d1, dbg_d2, dbg_d_out: out std_logic_vector (7 downto 0);\r
+-- signal dbg_ea_carry, dbg_carry_clr_n : out std_logic;\r
+-- signal dbg_gate_n : out std_logic;\r
+\r
+ signal dbg_pos_x : out std_logic_vector (8 downto 0);\r
+ signal dbg_pos_y : out std_logic_vector (8 downto 0);\r
+ signal dbg_nes_r : out std_logic_vector (3 downto 0);\r
+ signal dbg_nes_g : out std_logic_vector (3 downto 0);\r
+ signal dbg_nes_b : out std_logic_vector (3 downto 0);\r
+\r
+ signal dbg_wbs_adr_i : out std_logic_vector (21 downto 0); --Address (Bank, Row, Col)\r
+ signal dbg_wbs_dat_i : out std_logic_vector (15 downto 0); --Data In (16 bits)\r
+ signal dbg_wbs_we_i : out std_logic; --Write Enable\r
+ signal dbg_wbs_tga_i : out std_logic_vector (7 downto 0); --Address Tag : Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
+ signal dbg_wbs_cyc_i : out std_logic; --Cycle Command from interface\r
+ signal dbg_wbs_stb_i : out std_logic; --Strobe Command from interface\r
+\r
+ signal dbg_vga_x : out std_logic_vector (9 downto 0);\r
+ signal dbg_vga_y : out std_logic_vector (9 downto 0);\r
+ signal dbg_nes_x : out std_logic_vector(7 downto 0);\r
+ signal dbg_nes_x_old : out std_logic_vector(7 downto 0);\r
+ signal dbg_sw_state : out std_logic_vector(2 downto 0);\r
+\r
+ signal dbg_f_in : out std_logic_vector(11 downto 0);\r
+ signal dbg_f_out : out std_logic_vector(11 downto 0);\r
+ signal dbg_f_cnt : out std_logic_vector(7 downto 0);\r
+ signal dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful \r
+ : out std_logic;\r
+ signal dbg_bst_cnt : out std_logic_vector(7 downto 0);\r
+ \r
+ signal green_led : out std_logic; --Test passed\r
+ signal red_led : out std_logic; --Test fail\r
+\r
+ base_clk : in std_logic;\r
+ base_clk_27mhz : in std_logic;\r
+ rst_n : in std_logic;\r
+ h_sync_n : out std_logic;\r
+ v_sync_n : out std_logic;\r
+ r : out std_logic_vector(3 downto 0);\r
+ g : out std_logic_vector(3 downto 0);\r
+ b : out std_logic_vector(3 downto 0);\r
+\r
+ --SDRAM Signals\r
+ dram_addr : out std_logic_vector (11 downto 0); --Address (12 bit)\r
+ dram_bank : out std_logic_vector (1 downto 0); --Bank\r
+ dram_cas_n : out std_logic; --Column Address is being transmitted\r
+ dram_cke : out std_logic; --Clock Enable\r
+ dram_clk : out std_logic; --Clock\r
+ dram_cs_n : out std_logic; --Chip Select (Here - Mask commands)\r
+ dram_dq : inout std_logic_vector (15 downto 0); --Data in / Data out\r
+ dram_ldqm : out std_logic; --Byte masking\r
+ dram_udqm : out std_logic; --Byte masking\r
+ dram_ras_n : out std_logic; --Row Address is being transmitted\r
+ dram_we_n : out std_logic --Write Enable\r
+\r
+ );\r
+end qt_proj_test5_old;\r
+\r
+architecture rtl of qt_proj_test5_old is\r
+\r
component clock_divider\r
port ( base_clk : in std_logic;\r
reset_n : in std_logic;\r
(\r
inclk0 : IN STD_LOGIC := '0';\r
c0 : OUT STD_LOGIC ;\r
- c1 : OUT STD_LOGIC ;\r
locked : OUT STD_LOGIC \r
);\r
end component;\r
); \r
end component;\r
\r
+\r
+component sdram_rw\r
+ generic(\r
+ reset_polarity : std_logic := '0' --When rst = reset_polarity, system at RESET\r
+ );\r
+ port(\r
+ --Clock and Reset\r
+ clk_i : in std_logic; --WISHBONE Clock\r
+ rst : in std_logic; --RESET\r
+ \r
+ --Signals to SDRAM controller\r
+ wbm_adr_o : out std_logic_vector (21 downto 0); --Address to read from / write to\r
+ wbm_dat_i : in std_logic_vector (15 downto 0); --Data out (to SDRAM)\r
+ wbm_dat_o : out std_logic_vector (15 downto 0); --Data in (from SDRAM)\r
+ wbm_we_i : out std_logic; --'1' - Write, '0' - Read\r
+ wbm_tga_o : out std_logic_vector (7 downto 0); --Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
+ wbm_cyc_o : out std_logic; --Transmit command to SDRAM controller\r
+ wbm_stb_o : out std_logic; --Transmit command to SDRAM controller\r
+ wbm_stall_i : in std_logic; --When '1', write data to SDRAM\r
+ wbm_ack_i : in std_logic; --when '1', data is ready to be read from SDRAM\r
+ \r
+ --Debug and test signals\r
+ cmd_ack : in std_logic; --Command has been acknowledged by SDRAM controller\r
+ cmd_done : in std_logic; --Command has finished (read/write)\r
+ green_led : out std_logic; --Test passed\r
+ red_led : out std_logic; --Test fail\r
+ writing : out std_logic; --'1' when writing, '0' when reading\r
+ mem_val_o : out std_logic_vector (15 downto 0); --Memory value written / compared to SDRAM\r
+ sdram_val_o : out std_logic_vector (15 downto 0); --Read value from SDRAM\r
+ cur_st_o : out std_logic_vector (3 downto 0) --Current state\r
+ );\r
+end component;\r
+\r
constant data_size : integer := 8;\r
constant addr_size : integer := 16;\r
constant size14 : integer := 14;\r
signal init_st_o : std_logic_vector (3 downto 0); --Current init state\r
signal main_st_o : std_logic_vector (3 downto 0); --Current main state\r
\r
+ signal writing : std_logic; --'1' when writing, '0' when reading\r
+ signal mem_val_o : std_logic_vector (15 downto 0); --Memory value written / compared to SDRAM\r
+ signal sdram_val_o : std_logic_vector (15 downto 0); --Read value from SDRAM\r
+ signal cur_st_o : std_logic_vector (3 downto 0); --Current state\r
+ \r
begin\r
\r
\r
-- end process;\r
\r
\r
- vga_ctl_inst : vga_ctl\r
+-- vga_ctl_inst : vga_ctl\r
+-- port map ( \r
+-- dbg_vga_x ,\r
+-- dbg_vga_y ,\r
+-- dbg_nes_x ,\r
+-- dbg_nes_x_old ,\r
+-- dbg_sw_state ,\r
+-- \r
+-- dbg_f_in ,\r
+-- dbg_f_out ,\r
+-- dbg_f_cnt ,\r
+-- dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful ,\r
+-- dbg_bst_cnt ,\r
+--\r
+-- ppu_clk ,\r
+-- --vga_clk_pll, \r
+-- --ppu_clk ,\r
+-- vga_clk ,\r
+-- mem_clk ,\r
+-- rst_n ,\r
+-- pos_x ,\r
+-- pos_y ,\r
+-- nes_r ,\r
+-- nes_g ,\r
+-- nes_b ,\r
+-- h_sync_n ,\r
+-- v_sync_n ,\r
+-- r ,\r
+-- g ,\r
+-- b ,\r
+-- \r
+-- --SDRAM Signals\r
+-- wbs_adr_i ,\r
+-- wbs_dat_i ,\r
+-- wbs_we_i ,\r
+-- wbs_tga_i ,\r
+-- wbs_cyc_i ,\r
+-- wbs_stb_i ,\r
+-- wbs_dat_o ,\r
+-- wbs_stall_o ,\r
+-- wbs_err_o ,\r
+-- wbs_ack_o \r
+-- );\r
+\r
+ test_sdram_inst : sdram_rw\r
port map ( \r
- dbg_vga_x ,\r
- dbg_vga_y ,\r
- dbg_nes_x ,\r
- dbg_nes_x_old ,\r
- dbg_sw_state ,\r
- \r
- dbg_f_in ,\r
- dbg_f_out ,\r
- dbg_f_cnt ,\r
- dbg_f_rd, dbg_f_wr, dbg_f_emp, dbg_f_ful ,\r
- dbg_bst_cnt ,\r
-\r
- ppu_clk ,\r
- --vga_clk_pll, \r
- --ppu_clk ,\r
- vga_clk ,\r
- mem_clk ,\r
- rst_n ,\r
- pos_x ,\r
- pos_y ,\r
- nes_r ,\r
- nes_g ,\r
- nes_b ,\r
- h_sync_n ,\r
- v_sync_n ,\r
- r ,\r
- g ,\r
- b ,\r
- \r
- --SDRAM Signals\r
- wbs_adr_i ,\r
- wbs_dat_i ,\r
- wbs_we_i ,\r
- wbs_tga_i ,\r
- wbs_cyc_i ,\r
- wbs_stb_i ,\r
- wbs_dat_o ,\r
- wbs_stall_o ,\r
- wbs_err_o ,\r
- wbs_ack_o \r
- );\r
+ mem_clk,\r
+ rst_n,\r
+ \r
+ --Signals to SDRAM controller\r
+ wbs_adr_i,\r
+ wbs_dat_o,\r
+ wbs_dat_i,\r
+ wbs_we_i,\r
+ wbs_tga_i,\r
+ wbs_cyc_i,\r
+ wbs_stb_i,\r
+ wbs_stall_o,\r
+ wbs_ack_o,\r
+ \r
+ --Debug and test signals\r
+ cmd_ack ,\r
+ cmd_done ,\r
+ green_led ,\r
+ red_led ,\r
+ writing ,\r
+ mem_val_o ,\r
+ sdram_val_o ,\r
+ cur_st_o \r
+ );\r
\r
dram_clk <= not mem_clk;\r
sdram_clk <= not mem_clk;\r
--- /dev/null
+<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C(15|20) (0x020B30DD)" sof_file="">\r
+ <display_tree gui_logging_enabled="0">\r
+ <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>\r
+ </display_tree>\r
+ <global_info>\r
+ <single attribute="active instance" value="0"/>\r
+ <multi attribute="frame size" size="2" value="1471,883"/>\r
+ <single attribute="jtag widget visible" value="1"/>\r
+ <multi attribute="jtag widget size" size="2" value="334,270"/>\r
+ <single attribute="instance widget visible" value="1"/>\r
+ <single attribute="config widget visible" value="1"/>\r
+ <single attribute="hierarchy widget visible" value="1"/>\r
+ <single attribute="data log widget visible" value="1"/>\r
+ <single attribute="hierarchy widget height" value="1"/>\r
+ </global_info>\r
+ <instance entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">\r
+ <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>\r
+ <position_info>\r
+ <single attribute="active tab" value="0"/>\r
+ <single attribute="data vertical scroll position" value="0"/>\r
+ <single attribute="data horizontal scroll position" value="255"/>\r
+ <single attribute="zoom level numerator" value="128"/>\r
+ <single attribute="zoom level denominator" value="1"/>\r
+ <single attribute="zoom offset numerator" value="1008"/>\r
+ <single attribute="zoom offset denominator" value="1"/>\r
+ </position_info>\r
+ <signal_set global_temp="1" name="signal_set: 2014/02/14 13:01:49 #0">\r
+ <clock name="base_clk_24mhz" polarity="posedge" tap_mode="classic"/>\r
+ <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>\r
+ <top_entity/>\r
+ <signal_vec>\r
+ <trigger_input_vec>\r
+ <wire name="rst_n" tap_mode="classic"/>\r
+ </trigger_input_vec>\r
+ <data_input_vec>\r
+ <wire name="green_led" tap_mode="classic"/>\r
+ <wire name="red_led" tap_mode="classic"/>\r
+ <wire name="rst_n" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|clk_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_ack" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_done" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_ack_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[16]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[17]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[18]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[19]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[20]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[21]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_cyc_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stall_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stb_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_we_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|writing" tap_mode="classic"/>\r
+ </data_input_vec>\r
+ <storage_qualifier_input_vec>\r
+ <wire name="green_led" tap_mode="classic"/>\r
+ <wire name="red_led" tap_mode="classic"/>\r
+ <wire name="rst_n" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|clk_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_ack" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_done" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_ack_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[16]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[17]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[18]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[19]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[20]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[21]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_cyc_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stall_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stb_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_we_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|writing" tap_mode="classic"/>\r
+ </storage_qualifier_input_vec>\r
+ </signal_vec>\r
+ <presentation>\r
+ <unified_setup_data_view>\r
+ <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="green_led" storage_index="0" tap_mode="classic" type="output pin"/>\r
+ <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="red_led" storage_index="1" tap_mode="classic" type="output pin"/>\r
+ <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="rst_n" storage_index="2" tap_mode="classic" trigger_index="0" type="input pin"/>\r
+ <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|clk_i" storage_index="3" tap_mode="classic" type="combinatorial"/>\r
+ <node name="sdram_rw:sdr_rw|wbm_adr_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[21]" storage_index="56" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[20]" storage_index="55" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[19]" storage_index="53" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[18]" storage_index="52" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[17]" storage_index="51" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[16]" storage_index="50" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[15]" storage_index="49" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[14]" storage_index="48" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[13]" storage_index="47" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[12]" storage_index="46" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[11]" storage_index="45" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[10]" storage_index="44" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[9]" storage_index="64" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[8]" storage_index="63" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[7]" storage_index="62" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[6]" storage_index="61" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[5]" storage_index="60" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[4]" storage_index="59" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[3]" storage_index="58" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[2]" storage_index="57" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[1]" storage_index="54" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[0]" storage_index="43" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|wbm_dat_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[15]" storage_index="88" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[14]" storage_index="87" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[13]" storage_index="86" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[12]" storage_index="85" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[11]" storage_index="84" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[10]" storage_index="83" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[9]" storage_index="97" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[8]" storage_index="96" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[7]" storage_index="95" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[6]" storage_index="94" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[5]" storage_index="93" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[4]" storage_index="92" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[3]" storage_index="91" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[2]" storage_index="90" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[1]" storage_index="89" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[0]" storage_index="82" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|wbm_dat_i" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[15]" storage_index="72" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[14]" storage_index="71" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[13]" storage_index="70" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[12]" storage_index="69" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[11]" storage_index="68" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[10]" storage_index="67" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[9]" storage_index="81" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[8]" storage_index="80" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[7]" storage_index="79" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[6]" storage_index="78" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[5]" storage_index="77" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[4]" storage_index="76" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[3]" storage_index="75" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[2]" storage_index="74" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[1]" storage_index="73" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[0]" storage_index="66" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_we_i" storage_index="108" tap_mode="classic" type="combinatorial"/>\r
+ <node name="sdram_rw:sdr_rw|wbm_tga_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[7]" storage_index="107" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[6]" storage_index="106" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[5]" storage_index="105" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[4]" storage_index="104" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[3]" storage_index="103" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[2]" storage_index="102" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[1]" storage_index="101" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[0]" storage_index="100" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_cyc_o" storage_index="65" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stb_o" storage_index="99" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stall_i" storage_index="98" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_ack_i" storage_index="42" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_ack" storage_index="4" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_done" storage_index="5" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|writing" storage_index="109" tap_mode="classic" type="combinatorial"/>\r
+ <node name="sdram_rw:sdr_rw|mem_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[15]" storage_index="16" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[14]" storage_index="15" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[13]" storage_index="14" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[12]" storage_index="13" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[11]" storage_index="12" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[10]" storage_index="11" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[9]" storage_index="25" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[8]" storage_index="24" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[7]" storage_index="23" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[6]" storage_index="22" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[5]" storage_index="21" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[4]" storage_index="20" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[3]" storage_index="19" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[2]" storage_index="18" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[1]" storage_index="17" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[0]" storage_index="10" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|sdram_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[15]" storage_index="32" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[14]" storage_index="31" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[13]" storage_index="30" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[12]" storage_index="29" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[11]" storage_index="28" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[10]" storage_index="27" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[9]" storage_index="41" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[8]" storage_index="40" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[7]" storage_index="39" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[6]" storage_index="38" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[5]" storage_index="37" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[4]" storage_index="36" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[3]" storage_index="35" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[2]" storage_index="34" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[1]" storage_index="33" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[0]" storage_index="26" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|cur_st_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[3]" storage_index="9" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[2]" storage_index="8" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[1]" storage_index="7" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[0]" storage_index="6" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ </unified_setup_data_view>\r
+ <data_view>\r
+ <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="green_led" storage_index="0" tap_mode="classic" type="output pin"/>\r
+ <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="red_led" storage_index="1" tap_mode="classic" type="output pin"/>\r
+ <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="rst_n" storage_index="2" tap_mode="classic" trigger_index="0" type="input pin"/>\r
+ <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|clk_i" storage_index="3" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_adr_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[21]" storage_index="56" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[20]" storage_index="55" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[19]" storage_index="53" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[18]" storage_index="52" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[17]" storage_index="51" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[16]" storage_index="50" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[15]" storage_index="49" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[14]" storage_index="48" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[13]" storage_index="47" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[12]" storage_index="46" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[11]" storage_index="45" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[10]" storage_index="44" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[9]" storage_index="64" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[8]" storage_index="63" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[7]" storage_index="62" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[6]" storage_index="61" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[5]" storage_index="60" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[4]" storage_index="59" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[3]" storage_index="58" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[2]" storage_index="57" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[1]" storage_index="54" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[0]" storage_index="43" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[15]" storage_index="88" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[14]" storage_index="87" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[13]" storage_index="86" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[12]" storage_index="85" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[11]" storage_index="84" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[10]" storage_index="83" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[9]" storage_index="97" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[8]" storage_index="96" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[7]" storage_index="95" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[6]" storage_index="94" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[5]" storage_index="93" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[4]" storage_index="92" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[3]" storage_index="91" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[2]" storage_index="90" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[1]" storage_index="89" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[0]" storage_index="82" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_i" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[15]" storage_index="72" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[14]" storage_index="71" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[13]" storage_index="70" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[12]" storage_index="69" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[11]" storage_index="68" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[10]" storage_index="67" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[9]" storage_index="81" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[8]" storage_index="80" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[7]" storage_index="79" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[6]" storage_index="78" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[5]" storage_index="77" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[4]" storage_index="76" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[3]" storage_index="75" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[2]" storage_index="74" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[1]" storage_index="73" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[0]" storage_index="66" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_we_i" storage_index="108" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_tga_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[7]" storage_index="107" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[6]" storage_index="106" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[5]" storage_index="105" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[4]" storage_index="104" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[3]" storage_index="103" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[2]" storage_index="102" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[1]" storage_index="101" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[0]" storage_index="100" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_cyc_o" storage_index="65" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stb_o" storage_index="99" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stall_i" storage_index="98" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_ack_i" storage_index="42" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_ack" storage_index="4" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_done" storage_index="5" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|writing" storage_index="109" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|mem_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[15]" storage_index="16" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[14]" storage_index="15" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[13]" storage_index="14" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[12]" storage_index="13" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[11]" storage_index="12" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[10]" storage_index="11" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[9]" storage_index="25" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[8]" storage_index="24" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[7]" storage_index="23" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[6]" storage_index="22" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[5]" storage_index="21" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[4]" storage_index="20" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[3]" storage_index="19" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[2]" storage_index="18" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[1]" storage_index="17" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[0]" storage_index="10" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|sdram_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[15]" storage_index="32" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[14]" storage_index="31" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[13]" storage_index="30" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[12]" storage_index="29" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[11]" storage_index="28" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[10]" storage_index="27" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[9]" storage_index="41" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[8]" storage_index="40" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[7]" storage_index="39" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[6]" storage_index="38" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[5]" storage_index="37" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[4]" storage_index="36" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[3]" storage_index="35" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[2]" storage_index="34" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[1]" storage_index="33" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[0]" storage_index="26" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|cur_st_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[3]" storage_index="9" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[2]" storage_index="8" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[1]" storage_index="7" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[0]" storage_index="6" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ </data_view>\r
+ <setup_view>\r
+ <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="green_led" storage_index="0" tap_mode="classic" type="output pin"/>\r
+ <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="red_led" storage_index="1" tap_mode="classic" type="output pin"/>\r
+ <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="rst_n" storage_index="2" tap_mode="classic" trigger_index="0" type="input pin"/>\r
+ <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|clk_i" storage_index="3" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_adr_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[21]" storage_index="56" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[20]" storage_index="55" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[19]" storage_index="53" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[18]" storage_index="52" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[17]" storage_index="51" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[16]" storage_index="50" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[15]" storage_index="49" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[14]" storage_index="48" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[13]" storage_index="47" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[12]" storage_index="46" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[11]" storage_index="45" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[10]" storage_index="44" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[9]" storage_index="64" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[8]" storage_index="63" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[7]" storage_index="62" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[6]" storage_index="61" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[5]" storage_index="60" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[4]" storage_index="59" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[3]" storage_index="58" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[2]" storage_index="57" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[1]" storage_index="54" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[0]" storage_index="43" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[15]" storage_index="88" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[14]" storage_index="87" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[13]" storage_index="86" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[12]" storage_index="85" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[11]" storage_index="84" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[10]" storage_index="83" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[9]" storage_index="97" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[8]" storage_index="96" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[7]" storage_index="95" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[6]" storage_index="94" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[5]" storage_index="93" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[4]" storage_index="92" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[3]" storage_index="91" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[2]" storage_index="90" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[1]" storage_index="89" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[0]" storage_index="82" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_i" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[15]" storage_index="72" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[14]" storage_index="71" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[13]" storage_index="70" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[12]" storage_index="69" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[11]" storage_index="68" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[10]" storage_index="67" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[9]" storage_index="81" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[8]" storage_index="80" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[7]" storage_index="79" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[6]" storage_index="78" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[5]" storage_index="77" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[4]" storage_index="76" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[3]" storage_index="75" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[2]" storage_index="74" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[1]" storage_index="73" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[0]" storage_index="66" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_we_i" storage_index="108" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_tga_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[7]" storage_index="107" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[6]" storage_index="106" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[5]" storage_index="105" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[4]" storage_index="104" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[3]" storage_index="103" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[2]" storage_index="102" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[1]" storage_index="101" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[0]" storage_index="100" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_cyc_o" storage_index="65" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stb_o" storage_index="99" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stall_i" storage_index="98" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_ack_i" storage_index="42" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_ack" storage_index="4" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_done" storage_index="5" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|writing" storage_index="109" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|mem_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[15]" storage_index="16" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[14]" storage_index="15" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[13]" storage_index="14" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[12]" storage_index="13" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[11]" storage_index="12" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[10]" storage_index="11" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[9]" storage_index="25" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[8]" storage_index="24" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[7]" storage_index="23" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[6]" storage_index="22" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[5]" storage_index="21" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[4]" storage_index="20" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[3]" storage_index="19" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[2]" storage_index="18" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[1]" storage_index="17" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[0]" storage_index="10" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|sdram_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[15]" storage_index="32" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[14]" storage_index="31" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[13]" storage_index="30" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[12]" storage_index="29" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[11]" storage_index="28" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[10]" storage_index="27" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[9]" storage_index="41" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[8]" storage_index="40" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[7]" storage_index="39" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[6]" storage_index="38" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[5]" storage_index="37" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[4]" storage_index="36" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[3]" storage_index="35" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[2]" storage_index="34" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[1]" storage_index="33" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[0]" storage_index="26" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|cur_st_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[3]" storage_index="9" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[2]" storage_index="8" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[1]" storage_index="7" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[0]" storage_index="6" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ </setup_view>\r
+ <trigger_in_editor/>\r
+ <trigger_out_editor/>\r
+ </presentation>\r
+ <trigger CRC="2B003BEA" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2014/02/14 13:01:49 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">\r
+ <power_up_trigger position="pre" storage_qualifier_disabled="no"/>\r
+ <events use_custom_flow_control="no">\r
+ <level enabled="yes" name="condition1" type="basic">'rst_n' == rising edge\r
+ <power_up enabled="yes">\r
+ </power_up>\r
+ <op_node/>\r
+ </level>\r
+ </events>\r
+ <storage_qualifier_events>\r
+ <transitional>00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\r
+ <pwr_up_transitional>00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</pwr_up_transitional>\r
+ </transitional>\r
+ <storage_qualifier_level type="basic">\r
+ <power_up>\r
+ </power_up>\r
+ <op_node/>\r
+ </storage_qualifier_level>\r
+ <storage_qualifier_level type="basic">\r
+ <power_up>\r
+ </power_up>\r
+ <op_node/>\r
+ </storage_qualifier_level>\r
+ <storage_qualifier_level type="basic">\r
+ <power_up>\r
+ </power_up>\r
+ <op_node/>\r
+ </storage_qualifier_level>\r
+ </storage_qualifier_events>\r
+ <log>\r
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+ <extradata>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>\r
+ </log>\r
+ </trigger>\r
+ </signal_set>\r
+ </instance>\r
+ <mnemonics/>\r
+ <static_plugin_mnemonics/>\r
+</session>\r
--- /dev/null
+<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C(15|20) (0x020B30DD)" sof_file="">\r
+ <display_tree gui_logging_enabled="0">\r
+ <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>\r
+ </display_tree>\r
+ <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">\r
+ <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>\r
+ <signal_set global_temp="1" is_expanded="true" name="signal_set: 2014/02/14 13:01:49 #0">\r
+ <clock name="base_clk_24mhz" polarity="posedge" tap_mode="classic"/>\r
+ <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>\r
+ <top_entity/>\r
+ <signal_vec>\r
+ <trigger_input_vec>\r
+ <wire name="rst_n" tap_mode="classic"/>\r
+ </trigger_input_vec>\r
+ <data_input_vec>\r
+ <wire name="green_led" tap_mode="classic"/>\r
+ <wire name="red_led" tap_mode="classic"/>\r
+ <wire name="rst_n" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|clk_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_ack" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_done" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_ack_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[16]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[17]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[18]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[19]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[20]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[21]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_cyc_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stall_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stb_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_we_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|writing" tap_mode="classic"/>\r
+ </data_input_vec>\r
+ <storage_qualifier_input_vec>\r
+ <wire name="green_led" tap_mode="classic"/>\r
+ <wire name="red_led" tap_mode="classic"/>\r
+ <wire name="rst_n" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|clk_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_ack" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cmd_done" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|cur_st_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|mem_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|sdram_val_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_ack_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[16]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[17]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[18]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[19]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[20]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[21]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_adr_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_cyc_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_i[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[10]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[11]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[12]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[13]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[14]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[15]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[8]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_dat_o[9]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stall_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_stb_o" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[0]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[1]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[2]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[3]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[4]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[5]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[6]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_tga_o[7]" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|wbm_we_i" tap_mode="classic"/>\r
+ <wire name="sdram_rw:sdr_rw|writing" tap_mode="classic"/>\r
+ </storage_qualifier_input_vec>\r
+ </signal_vec>\r
+ <presentation>\r
+ <unified_setup_data_view>\r
+ <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="green_led" storage_index="0" tap_mode="classic" type="output pin"/>\r
+ <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="red_led" storage_index="1" tap_mode="classic" type="output pin"/>\r
+ <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="rst_n" storage_index="2" tap_mode="classic" trigger_index="0" type="input pin"/>\r
+ <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|clk_i" storage_index="3" tap_mode="classic" type="combinatorial"/>\r
+ <node name="sdram_rw:sdr_rw|wbm_adr_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[21]" storage_index="56" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[20]" storage_index="55" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[19]" storage_index="53" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[18]" storage_index="52" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[17]" storage_index="51" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[16]" storage_index="50" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[15]" storage_index="49" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[14]" storage_index="48" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[13]" storage_index="47" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[12]" storage_index="46" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[11]" storage_index="45" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[10]" storage_index="44" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[9]" storage_index="64" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[8]" storage_index="63" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[7]" storage_index="62" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[6]" storage_index="61" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[5]" storage_index="60" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[4]" storage_index="59" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[3]" storage_index="58" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[2]" storage_index="57" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[1]" storage_index="54" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[0]" storage_index="43" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|wbm_dat_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[15]" storage_index="88" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[14]" storage_index="87" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[13]" storage_index="86" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[12]" storage_index="85" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[11]" storage_index="84" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[10]" storage_index="83" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[9]" storage_index="97" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[8]" storage_index="96" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[7]" storage_index="95" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[6]" storage_index="94" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[5]" storage_index="93" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[4]" storage_index="92" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[3]" storage_index="91" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[2]" storage_index="90" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[1]" storage_index="89" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[0]" storage_index="82" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|wbm_dat_i" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[15]" storage_index="72" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[14]" storage_index="71" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[13]" storage_index="70" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[12]" storage_index="69" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[11]" storage_index="68" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[10]" storage_index="67" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[9]" storage_index="81" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[8]" storage_index="80" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[7]" storage_index="79" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[6]" storage_index="78" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[5]" storage_index="77" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[4]" storage_index="76" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[3]" storage_index="75" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[2]" storage_index="74" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[1]" storage_index="73" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[0]" storage_index="66" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_we_i" storage_index="108" tap_mode="classic" type="combinatorial"/>\r
+ <node name="sdram_rw:sdr_rw|wbm_tga_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[7]" storage_index="107" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[6]" storage_index="106" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[5]" storage_index="105" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[4]" storage_index="104" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[3]" storage_index="103" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[2]" storage_index="102" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[1]" storage_index="101" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[0]" storage_index="100" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_cyc_o" storage_index="65" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stb_o" storage_index="99" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stall_i" storage_index="98" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_ack_i" storage_index="42" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_ack" storage_index="4" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_done" storage_index="5" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|writing" storage_index="109" tap_mode="classic" type="combinatorial"/>\r
+ <node name="sdram_rw:sdr_rw|mem_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[15]" storage_index="16" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[14]" storage_index="15" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[13]" storage_index="14" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[12]" storage_index="13" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[11]" storage_index="12" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[10]" storage_index="11" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[9]" storage_index="25" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[8]" storage_index="24" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[7]" storage_index="23" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[6]" storage_index="22" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[5]" storage_index="21" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[4]" storage_index="20" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[3]" storage_index="19" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[2]" storage_index="18" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[1]" storage_index="17" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[0]" storage_index="10" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|sdram_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[15]" storage_index="32" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[14]" storage_index="31" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[13]" storage_index="30" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[12]" storage_index="29" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[11]" storage_index="28" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[10]" storage_index="27" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[9]" storage_index="41" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[8]" storage_index="40" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[7]" storage_index="39" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[6]" storage_index="38" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[5]" storage_index="37" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[4]" storage_index="36" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[3]" storage_index="35" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[2]" storage_index="34" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[1]" storage_index="33" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[0]" storage_index="26" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ <node name="sdram_rw:sdr_rw|cur_st_o" order="msb_to_lsb" type="combinatorial">\r
+ <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[3]" storage_index="9" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[2]" storage_index="8" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[1]" storage_index="7" tap_mode="classic" type="combinatorial"/>\r
+ <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[0]" storage_index="6" tap_mode="classic" type="combinatorial"/>\r
+ </node>\r
+ </unified_setup_data_view>\r
+ <data_view>\r
+ <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="green_led" storage_index="0" tap_mode="classic" type="output pin"/>\r
+ <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="red_led" storage_index="1" tap_mode="classic" type="output pin"/>\r
+ <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="rst_n" storage_index="2" tap_mode="classic" trigger_index="0" type="input pin"/>\r
+ <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|clk_i" storage_index="3" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_adr_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[21]" storage_index="56" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[20]" storage_index="55" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[19]" storage_index="53" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[18]" storage_index="52" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[17]" storage_index="51" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[16]" storage_index="50" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[15]" storage_index="49" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[14]" storage_index="48" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[13]" storage_index="47" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[12]" storage_index="46" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[11]" storage_index="45" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[10]" storage_index="44" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[9]" storage_index="64" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[8]" storage_index="63" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[7]" storage_index="62" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[6]" storage_index="61" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[5]" storage_index="60" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[4]" storage_index="59" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[3]" storage_index="58" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[2]" storage_index="57" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[1]" storage_index="54" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[0]" storage_index="43" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[15]" storage_index="88" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[14]" storage_index="87" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[13]" storage_index="86" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[12]" storage_index="85" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[11]" storage_index="84" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[10]" storage_index="83" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[9]" storage_index="97" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[8]" storage_index="96" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[7]" storage_index="95" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[6]" storage_index="94" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[5]" storage_index="93" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[4]" storage_index="92" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[3]" storage_index="91" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[2]" storage_index="90" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[1]" storage_index="89" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[0]" storage_index="82" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_i" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[15]" storage_index="72" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[14]" storage_index="71" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[13]" storage_index="70" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[12]" storage_index="69" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[11]" storage_index="68" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[10]" storage_index="67" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[9]" storage_index="81" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[8]" storage_index="80" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[7]" storage_index="79" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[6]" storage_index="78" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[5]" storage_index="77" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[4]" storage_index="76" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[3]" storage_index="75" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[2]" storage_index="74" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[1]" storage_index="73" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[0]" storage_index="66" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_we_i" storage_index="108" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_tga_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[7]" storage_index="107" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[6]" storage_index="106" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[5]" storage_index="105" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[4]" storage_index="104" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[3]" storage_index="103" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[2]" storage_index="102" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[1]" storage_index="101" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[0]" storage_index="100" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_cyc_o" storage_index="65" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stb_o" storage_index="99" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stall_i" storage_index="98" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_ack_i" storage_index="42" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_ack" storage_index="4" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_done" storage_index="5" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|writing" storage_index="109" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|mem_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[15]" storage_index="16" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[14]" storage_index="15" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[13]" storage_index="14" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[12]" storage_index="13" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[11]" storage_index="12" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[10]" storage_index="11" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[9]" storage_index="25" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[8]" storage_index="24" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[7]" storage_index="23" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[6]" storage_index="22" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[5]" storage_index="21" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[4]" storage_index="20" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[3]" storage_index="19" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[2]" storage_index="18" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[1]" storage_index="17" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[0]" storage_index="10" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|sdram_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[15]" storage_index="32" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[14]" storage_index="31" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[13]" storage_index="30" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[12]" storage_index="29" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[11]" storage_index="28" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[10]" storage_index="27" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[9]" storage_index="41" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[8]" storage_index="40" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[7]" storage_index="39" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[6]" storage_index="38" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[5]" storage_index="37" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[4]" storage_index="36" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[3]" storage_index="35" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[2]" storage_index="34" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[1]" storage_index="33" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[0]" storage_index="26" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|cur_st_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[3]" storage_index="9" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[2]" storage_index="8" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[1]" storage_index="7" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[0]" storage_index="6" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ </data_view>\r
+ <setup_view>\r
+ <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="green_led" storage_index="0" tap_mode="classic" type="output pin"/>\r
+ <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="red_led" storage_index="1" tap_mode="classic" type="output pin"/>\r
+ <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="rst_n" storage_index="2" tap_mode="classic" trigger_index="0" type="input pin"/>\r
+ <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|clk_i" storage_index="3" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_adr_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="56" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[21]" storage_index="56" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="55" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[20]" storage_index="55" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="53" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[19]" storage_index="53" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="52" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[18]" storage_index="52" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="51" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[17]" storage_index="51" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="50" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[16]" storage_index="50" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="49" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[15]" storage_index="49" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[14]" storage_index="48" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[13]" storage_index="47" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[12]" storage_index="46" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[11]" storage_index="45" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[10]" storage_index="44" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="64" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[9]" storage_index="64" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="63" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[8]" storage_index="63" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="62" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[7]" storage_index="62" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="61" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[6]" storage_index="61" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="60" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[5]" storage_index="60" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="59" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[4]" storage_index="59" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="58" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[3]" storage_index="58" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="57" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[2]" storage_index="57" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="54" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[1]" storage_index="54" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_adr_o[0]" storage_index="43" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="88" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[15]" storage_index="88" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="87" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[14]" storage_index="87" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="86" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[13]" storage_index="86" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="85" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[12]" storage_index="85" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="84" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[11]" storage_index="84" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="83" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[10]" storage_index="83" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="97" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[9]" storage_index="97" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="96" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[8]" storage_index="96" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="95" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[7]" storage_index="95" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="94" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[6]" storage_index="94" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="93" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[5]" storage_index="93" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="92" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[4]" storage_index="92" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="91" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[3]" storage_index="91" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="90" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[2]" storage_index="90" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="89" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[1]" storage_index="89" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="82" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_o[0]" storage_index="82" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|wbm_dat_i" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="72" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[15]" storage_index="72" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="71" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[14]" storage_index="71" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="70" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[13]" storage_index="70" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="69" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[12]" storage_index="69" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="68" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[11]" storage_index="68" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="67" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[10]" storage_index="67" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="81" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[9]" storage_index="81" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="80" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[8]" storage_index="80" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="79" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[7]" storage_index="79" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="78" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[6]" storage_index="78" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="77" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[5]" storage_index="77" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="76" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[4]" storage_index="76" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="75" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[3]" storage_index="75" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="74" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[2]" storage_index="74" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="73" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[1]" storage_index="73" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="66" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_dat_i[0]" storage_index="66" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="108" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_we_i" storage_index="108" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|wbm_tga_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="107" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[7]" storage_index="107" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="106" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[6]" storage_index="106" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="105" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[5]" storage_index="105" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="104" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[4]" storage_index="104" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="103" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[3]" storage_index="103" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="102" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[2]" storage_index="102" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="101" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[1]" storage_index="101" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="100" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_tga_o[0]" storage_index="100" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <net data_index="65" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_cyc_o" storage_index="65" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="99" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stb_o" storage_index="99" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="98" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_stall_i" storage_index="98" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|wbm_ack_i" storage_index="42" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_ack" storage_index="4" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cmd_done" storage_index="5" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="109" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|writing" storage_index="109" tap_mode="classic" type="combinatorial"/>\r
+ <bus name="sdram_rw:sdr_rw|mem_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[15]" storage_index="16" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[14]" storage_index="15" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[13]" storage_index="14" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[12]" storage_index="13" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[11]" storage_index="12" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[10]" storage_index="11" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[9]" storage_index="25" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[8]" storage_index="24" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[7]" storage_index="23" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[6]" storage_index="22" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[5]" storage_index="21" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[4]" storage_index="20" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[3]" storage_index="19" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[2]" storage_index="18" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[1]" storage_index="17" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|mem_val_o[0]" storage_index="10" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|sdram_val_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[15]" storage_index="32" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[14]" storage_index="31" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[13]" storage_index="30" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[12]" storage_index="29" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[11]" storage_index="28" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[10]" storage_index="27" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[9]" storage_index="41" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[8]" storage_index="40" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[7]" storage_index="39" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[6]" storage_index="38" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[5]" storage_index="37" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[4]" storage_index="36" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[3]" storage_index="35" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[2]" storage_index="34" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[1]" storage_index="33" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|sdram_val_o[0]" storage_index="26" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ <bus name="sdram_rw:sdr_rw|cur_st_o" order="msb_to_lsb" type="combinatorial">\r
+ <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[3]" storage_index="9" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[2]" storage_index="8" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[1]" storage_index="7" tap_mode="classic" type="combinatorial"/>\r
+ <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="false" name="sdram_rw:sdr_rw|cur_st_o[0]" storage_index="6" tap_mode="classic" type="combinatorial"/>\r
+ </bus>\r
+ </setup_view>\r
+ <trigger_in_editor/>\r
+ <trigger_out_editor/>\r
+ </presentation>\r
+ <trigger CRC="2B003BEA" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2014/02/14 13:01:49 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">\r
+ <power_up_trigger position="pre" storage_qualifier_disabled="no"/>\r
+ <events use_custom_flow_control="no">\r
+ <level enabled="yes" name="condition1" type="basic">'rst_n' == rising edge\r
+ <power_up enabled="yes">\r
+ </power_up><op_node/>\r
+ </level>\r
+ </events>\r
+ <storage_qualifier_events>\r
+ <transitional>00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\r
+ <pwr_up_transitional>00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</pwr_up_transitional>\r
+ </transitional>\r
+ <storage_qualifier_level type="basic">\r
+ <power_up>\r
+ </power_up>\r
+ <op_node/>\r
+ </storage_qualifier_level>\r
+ <storage_qualifier_level type="basic">\r
+ <power_up>\r
+ </power_up>\r
+ <op_node/>\r
+ </storage_qualifier_level>\r
+ <storage_qualifier_level type="basic">\r
+ <power_up>\r
+ </power_up>\r
+ <op_node/>\r
+ </storage_qualifier_level>\r
+ </storage_qualifier_events>\r
+ <log>\r
+ <data global_temp="1" name="log: 2014/02/14 13:03:10 #0" power_up_mode="false" sample_depth="2048" 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+ </log>\r
+ </trigger>\r
+ </signal_set>\r
+ <position_info>\r
+ <single attribute="active tab" value="0"/>\r
+ <single attribute="data horizontal scroll position" value="255"/>\r
+ <single attribute="data vertical scroll position" value="0"/>\r
+ <single attribute="zoom level denominator" value="1"/>\r
+ <single attribute="zoom level numerator" value="128"/>\r
+ <single attribute="zoom offset denominator" value="1"/>\r
+ <single attribute="zoom offset numerator" value="1008"/>\r
+ </position_info>\r
+ </instance>\r
+ <mnemonics/>\r
+ <static_plugin_mnemonics/>\r
+ <global_info>\r
+ <single attribute="active instance" value="0"/>\r
+ <single attribute="config widget visible" value="1"/>\r
+ <single attribute="data log widget visible" value="1"/>\r
+ <single attribute="hierarchy widget height" value="1"/>\r
+ <single attribute="hierarchy widget visible" value="1"/>\r
+ <single attribute="instance widget visible" value="1"/>\r
+ <single attribute="jtag widget visible" value="1"/>\r
+ <multi attribute="frame size" size="2" value="1471,883"/>\r
+ <multi attribute="jtag widget size" size="2" value="334,270"/>\r
+ </global_info>\r
+</session>\r
--- /dev/null
+------------------------------------------------------------------------------------------------\r
+-- Model Name : IS42S16400 SDRAM Read/Write test\r
+-- File Name : sdram_rw.vhd\r
+-- Generated : September 2010\r
+-- Author : Beeri Schreiber and Alon Yavich\r
+-- Project : RunLen Project\r
+------------------------------------------------------------------------------------------------\r
+-- Description: This model uses the IS42S16400 SDRAM Controller to perform test for the\r
+-- SDRAM:\r
+-- (1) Writing data to all of the addresses\r
+-- (2) Reading data from all the above addresses, and\r
+-- compare the expected value to the actual read value.\r
+--\r
+-- A green led will turn on if test had passed.\r
+-- A red led will turn on if the test had failed.\r
+--\r
+-- Clock: Use 133.333MHz clock for this model (7.5 ns period time) - Same as SDRAM Clock\r
+--\r
+-- Reset: Hold Reset for at least 1 clock\r
+------------------------------------------------------------------------------------------------\r
+-- Changes:\r
+-- Number Date Name Description\r
+-- (1) 09/2010 Beeri Schreiber Creation\r
+------------------------------------------------------------------------------------------------\r
+-- Todo:\r
+-- (1) Read burst addr incrementation\r
+------------------------------------------------------------------------------------------------\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+entity sdram_rw is\r
+ generic(\r
+ reset_polarity : std_logic := '0' --When rst = reset_polarity, system at RESET\r
+ );\r
+ port(\r
+ --Clock and Reset\r
+ clk_i : in std_logic; --WISHBONE Clock\r
+ rst : in std_logic; --RESET\r
+ \r
+ --Signals to SDRAM controller\r
+ wbm_adr_o : out std_logic_vector (21 downto 0); --Address to read from / write to\r
+ wbm_dat_i : in std_logic_vector (15 downto 0); --Data out (to SDRAM)\r
+ wbm_dat_o : out std_logic_vector (15 downto 0); --Data in (from SDRAM)\r
+ wbm_we_i : out std_logic; --'1' - Write, '0' - Read\r
+ wbm_tga_o : out std_logic_vector (7 downto 0); --Read/write burst length-1 (0 represents 1 word, FF represents 256 words)\r
+ wbm_cyc_o : out std_logic; --Transmit command to SDRAM controller\r
+ wbm_stb_o : out std_logic; --Transmit command to SDRAM controller\r
+ wbm_stall_i : in std_logic; --When '1', write data to SDRAM\r
+ wbm_ack_i : in std_logic; --when '1', data is ready to be read from SDRAM\r
+ \r
+ --Debug and test signals\r
+ cmd_ack : in std_logic; --Command has been acknowledged by SDRAM controller\r
+ cmd_done : in std_logic; --Command has finished (read/write)\r
+ green_led : out std_logic; --Test passed\r
+ red_led : out std_logic; --Test fail\r
+ writing : out std_logic; --'1' when writing, '0' when reading\r
+ mem_val_o : out std_logic_vector (15 downto 0); --Memory value written / compared to SDRAM\r
+ sdram_val_o : out std_logic_vector (15 downto 0); --Read value from SDRAM\r
+ cur_st_o : out std_logic_vector (3 downto 0) --Current state\r
+ );\r
+end entity sdram_rw;\r
+\r
+architecture arc_sdram_rw of sdram_rw is\r
+\r
+ -------------------------------- Types --------------------------------------\r
+ type states is ( START_WRITE_ST, -- Initilize Writing\r
+ WRITE_ST, -- Command SDRAM controller to write value (32bit)\r
+ WAIT_WRITE_ACK_ST, -- Wait for SDRAM controller to acknowledge\r
+ WRITE_BURST, -- Burst write\r
+ WRITE_WAIT_ST, -- Increment written data value, and repeat write process \r
+ START_READ_ST, -- Wait for Write to Read delay\r
+ READ_ST, -- Command SDRAM controller to read data\r
+ WAIT_READ_ACK_ST, -- Wait for SDRAM controller to acknowledge\r
+ READ_BURST, -- Burst Read, Compare between read and expected data\r
+ READ_WAIT_ST, -- End burst, Compare between read and expected data, repeat reading\r
+ DONE_ST -- Test done\r
+ );\r
+\r
+ -------------------------------- Constants -----------------------------------------\r
+ \r
+ constant MAX_ADDR : natural := 512; --2097150; -- 2,097,152 (-2 = 2,097,150, since we begin from 0) is the full 8 Mbytes of memory (2097152*32Bit*4Banks=67,108,864Bits)\r
+ constant W_TO_R_WAIT_TIME : natural := 10; --9999999; -- number of clock cycles between WRITE to READ\r
+ constant BURST_LENGTH : natural range 1 to 256 := 128; --Maximum is 256\r
+ constant ADDR_INC : natural := 128; --Increment address by this value in each burst\r
+ constant INITIAL_MEM_VALUE : std_logic_vector (15 downto 0) := conv_std_logic_vector(0, 16);--Initial memory value\r
+ -------------------------------- Signals -----------------------------------------\r
+\r
+ --Commands, Data and Address to SDRAM Controller\r
+ signal addr_r : std_logic_vector (21 downto 0) := (others => '0');\r
+ signal dat_o_r : std_logic_vector (15 downto 0);\r
+ signal we_i_r : std_logic := '0';\r
+ signal cmd_r : std_logic := '0';\r
+\r
+ --Test Signals\r
+ signal red_led_r : std_logic := '0'; --Test fail\r
+ signal green_led_r : std_logic := '0'; --Test passed\r
+ \r
+ --Internal Signals\r
+ signal cnt : integer := 0; --Counter for Write to Read delay\r
+ signal blen : natural range 0 to 256 := BURST_LENGTH; --Counter for burst length\r
+ signal mem_value : std_logic_vector (15 downto 0) := INITIAL_MEM_VALUE; --Written value / expected value\r
+ signal state : states := START_WRITE_ST;\r
+ \r
+ \r
+ \r
+ begin\r
+ --Connect internal signals to ports\r
+ wbm_dat_o <= dat_o_r;\r
+ wbm_adr_o <= addr_r;\r
+ wbm_we_i <= we_i_r;\r
+ wbm_cyc_o <= cmd_r;\r
+ wbm_stb_o <= cmd_r;\r
+ red_led <= red_led_r;\r
+ green_led <= green_led_r;\r
+ mem_val_o <= mem_value;\r
+ sdram_val_o <= dat_o_r;\r
+ \r
+ main_proc : process (clk_i, rst)\r
+ begin\r
+ if (rst = reset_polarity) then\r
+ state <= START_WRITE_ST;\r
+ red_led_r <= '1';\r
+ green_led_r <= '1';\r
+ elsif rising_edge(clk_i) then\r
+ case state is\r
+ when START_WRITE_ST => --Initilize writing\r
+ state <= WRITE_ST;\r
+ addr_r <= (others => '0');\r
+ mem_value <= INITIAL_MEM_VALUE;\r
+ writing <= '1';\r
+ dat_o_r <= mem_value;\r
+ red_led_r <= '0';\r
+ green_led_r <= '0';\r
+ \r
+ when WRITE_ST => --Write value (16 bits) to SDRAM controller\r
+ cmd_r <= '1';\r
+ --dat_o_r <= mem_value;\r
+ we_i_r <= '1';\r
+ state <= WAIT_WRITE_ACK_ST;\r
+ blen <= BURST_LENGTH; \r
+ wbm_tga_o <= conv_std_logic_vector(BURST_LENGTH-1, 8);\r
+\r
+ when WAIT_WRITE_ACK_ST => --Present first data\r
+ if (blen > 0) then --First data\r
+ dat_o_r <= mem_value;\r
+ mem_value <= mem_value + '1';\r
+ blen <= blen - 1;\r
+ end if;\r
+ state <= WRITE_BURST;\r
+ \r
+ when WRITE_BURST => --Burst write\r
+ if (wbm_stall_i = '1') then\r
+ dat_o_r <= dat_o_r;\r
+ elsif (blen > 0) then --Keep burst\r
+ dat_o_r <= mem_value;\r
+ mem_value <= mem_value + '1';\r
+ blen <= blen - 1;\r
+ else --End of write burst\r
+ state <= WRITE_WAIT_ST;\r
+ addr_r <= addr_r + conv_std_logic_vector(ADDR_INC, 22); --Add 256\r
+ end if;\r
+ \r
+ \r
+ when WRITE_WAIT_ST => --Increment DATA value. Repeat write\r
+ if (conv_integer(addr_r) < MAX_ADDR) then\r
+ state <= WRITE_ST;\r
+ else\r
+ state <= START_READ_ST;\r
+ writing <= '0';\r
+ cmd_r <= '0';\r
+ end if;\r
+\r
+ when START_READ_ST => --Wait Write to Read interval\r
+ if (cnt = 0) then -- wait for W_TO_R_WAIT_TIME\r
+ state <= READ_ST;\r
+ addr_r <= (others => '0');\r
+ mem_value <= INITIAL_MEM_VALUE;\r
+ else\r
+ state <= START_READ_ST;\r
+ end if;\r
+ \r
+ when READ_ST => --Transmit read command to controller\r
+ cmd_r <= '1';\r
+ we_i_r <= '0';\r
+ state <= READ_BURST;\r
+ blen <= BURST_LENGTH;\r
+ wbm_tga_o <= conv_std_logic_vector(BURST_LENGTH-1, 8);\r
+ \r
+ -- when WAIT_READ_ACK_ST => --Wait until controller has acknowledge - and read SDRAM value\r
+ -- if (cmd_ack = '1') then\r
+ -- state <= READ_BURST;\r
+ -- end if;\r
+\r
+ -- when READ_BURST => --Burst read\r
+ -- if (blen = 0) then\r
+ -- state <= READ_WAIT_ST;\r
+ -- addr_r <= addr_r + conv_std_logic_vector(ADDR_INC, 22); -- add 256\r
+ -- mem_value <= mem_value + '1'; --Increment expected value\r
+ -- blen <= 2; --CAS Delay is 3. Two more data are available\r
+ -- elsif (wbm_ack_i ='1') and (blen > 0) then --Keep burst read\r
+ -- if (wbm_dat_i /= mem_value) then --Compare between read value and expected value\r
+ -- red_led_r <= '1';\r
+ -- --state <= DONE_ST; --Test fail - abort Test\r
+ -- end if;\r
+ -- mem_value <= mem_value + '1'; --Increment expected value\r
+ -- blen <= blen - 1;\r
+ -- end if;\r
+ \r
+ when READ_BURST => --Wait until end of valid data after burst \r
+ if (wbm_stall_i = '1') then\r
+ null;\r
+ elsif (wbm_ack_i ='1') and (blen > 0) then --Data is being read from SDRAM\r
+ if (wbm_dat_i /= mem_value) then --Compare between read value and expected value\r
+ red_led_r <= '1';\r
+ --state <= DONE_ST; --Test fail - abort Test\r
+ end if;\r
+ mem_value <= mem_value + '1'; --Increment expected value\r
+ blen <= blen - 1;\r
+ elsif (conv_integer(addr_r) < MAX_ADDR) then\r
+ addr_r <= addr_r + conv_std_logic_vector(ADDR_INC, 22); -- add 256\r
+ state <= READ_ST;\r
+ else \r
+ state <= DONE_ST;\r
+ cmd_r <= '0';\r
+ end if;\r
+\r
+ when DONE_ST => --Test done\r
+ state <= DONE_ST;\r
+ if (red_led_r = '0') then\r
+ green_led_r <= '1';\r
+ end if;\r
+ \r
+ when others =>\r
+ \r
+ end case;\r
+ cur_st_o <= conv_std_logic_vector(states'pos(state), 4);\r
+ end if;\r
+ end process main_proc;\r
+\r
+\r
+ --Write to Read delay\r
+ cnt_proc : process (clk_i, rst) \r
+ begin\r
+ if rising_edge(clk_i) then\r
+ if (rst = reset_polarity) then\r
+ cnt <= 0;\r
+ elsif (state = WRITE_WAIT_ST) then\r
+ cnt <= W_TO_R_WAIT_TIME;\r
+ else\r
+ cnt <= cnt - 1;\r
+ end if;\r
+ end if;\r
+ end process cnt_proc;\r
+ \r
+end architecture arc_sdram_rw;\r
+\r
+++ /dev/null
-<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C(15|20) (0x020B30DD)" sof_file="output_files/qt_proj_test5.sof">\r
- <display_tree gui_logging_enabled="0">\r
- <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>\r
- </display_tree>\r
- <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">\r
- <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>\r
- <signal_set global_temp="1" is_expanded="true" name="signal_set: 2013/12/16 15:11:45 #0">\r
- <clock name="dram_clk" polarity="posedge" tap_mode="classic"/>\r
- <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>\r
- <top_entity/>\r
- <signal_vec>\r
- <trigger_input_vec>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_cyc_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_stb_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_we_i" tap_mode="classic"/>\r
- </trigger_input_vec>\r
- <data_input_vec>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_cyc_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_stb_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_we_i" tap_mode="classic"/>\r
- </data_input_vec>\r
- <storage_qualifier_input_vec>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_cyc_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_stb_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_we_i" tap_mode="classic"/>\r
- </storage_qualifier_input_vec>\r
- </signal_vec>\r
- <presentation>\r
- <unified_setup_data_view>\r
- <node name="vga_ctl:vga_ctl_inst|wbs_adr_i" order="msb_to_lsb" type="combinatorial">\r
- <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="combinatorial"/>\r
- <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="combinatorial"/>\r
- <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="combinatorial"/>\r
- <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="combinatorial"/>\r
- <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="combinatorial"/>\r
- <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="combinatorial"/>\r
- <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="combinatorial"/>\r
- <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="combinatorial"/>\r
- <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="combinatorial"/>\r
- <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="combinatorial"/>\r
- <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="combinatorial"/>\r
- <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="combinatorial"/>\r
- <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>\r
- <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>\r
- <node data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>\r
- <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="combinatorial"/>\r
- <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="combinatorial"/>\r
- <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="combinatorial"/>\r
- <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="combinatorial"/>\r
- <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="combinatorial"/>\r
- <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="combinatorial"/>\r
- <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="combinatorial"/>\r
- </node>\r
- <node name="vga_ctl:vga_ctl_inst|wbs_dat_i" order="msb_to_lsb" type="combinatorial">\r
- <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>\r
- <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>\r
- <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>\r
- <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>\r
- <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>\r
- <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>\r
- <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>\r
- <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>\r
- <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>\r
- <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>\r
- <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>\r
- <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>\r
- <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>\r
- <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>\r
- <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>\r
- <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>\r
- </node>\r
- <node name="vga_ctl:vga_ctl_inst|wbs_tga_i" order="msb_to_lsb" type="combinatorial">\r
- <node data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>\r
- <node data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>\r
- <node data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>\r
- <node data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>\r
- <node data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>\r
- <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>\r
- <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>\r
- <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>\r
- </node>\r
- <node data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_we_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>\r
- <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_stb_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>\r
- <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_cyc_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>\r
- </unified_setup_data_view>\r
- <data_view>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_adr_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="combinatorial"/>\r
- <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="combinatorial"/>\r
- <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="combinatorial"/>\r
- <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="combinatorial"/>\r
- <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="combinatorial"/>\r
- <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="combinatorial"/>\r
- <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="combinatorial"/>\r
- <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="combinatorial"/>\r
- <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="combinatorial"/>\r
- <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="combinatorial"/>\r
- <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="combinatorial"/>\r
- <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="combinatorial"/>\r
- <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>\r
- <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>\r
- <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>\r
- <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="combinatorial"/>\r
- <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="combinatorial"/>\r
- <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="combinatorial"/>\r
- <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="combinatorial"/>\r
- <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="combinatorial"/>\r
- <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="combinatorial"/>\r
- <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_dat_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>\r
- <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>\r
- <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>\r
- <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>\r
- <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>\r
- <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>\r
- <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>\r
- <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>\r
- <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>\r
- <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>\r
- <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>\r
- <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>\r
- <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>\r
- <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>\r
- <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>\r
- <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_tga_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>\r
- <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>\r
- <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>\r
- <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>\r
- <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>\r
- <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>\r
- <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>\r
- <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>\r
- </bus>\r
- <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_we_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>\r
- <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_stb_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>\r
- <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_cyc_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>\r
- </data_view>\r
- <setup_view>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_adr_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="combinatorial"/>\r
- <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="combinatorial"/>\r
- <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="combinatorial"/>\r
- <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="combinatorial"/>\r
- <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="combinatorial"/>\r
- <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="combinatorial"/>\r
- <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="combinatorial"/>\r
- <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="combinatorial"/>\r
- <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="combinatorial"/>\r
- <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="combinatorial"/>\r
- <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="combinatorial"/>\r
- <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="combinatorial"/>\r
- <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>\r
- <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>\r
- <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>\r
- <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="combinatorial"/>\r
- <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="combinatorial"/>\r
- <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="combinatorial"/>\r
- <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="combinatorial"/>\r
- <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="combinatorial"/>\r
- <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="combinatorial"/>\r
- <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_dat_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>\r
- <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>\r
- <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>\r
- <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>\r
- <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>\r
- <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>\r
- <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>\r
- <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>\r
- <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>\r
- <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>\r
- <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>\r
- <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>\r
- <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>\r
- <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>\r
- <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>\r
- <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_tga_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>\r
- <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>\r
- <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>\r
- <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>\r
- <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>\r
- <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>\r
- <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>\r
- <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>\r
- </bus>\r
- <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_we_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>\r
- <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_stb_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>\r
- <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_cyc_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>\r
- </setup_view>\r
- <trigger_in_editor/>\r
- <trigger_out_editor/>\r
- </presentation>\r
- <trigger CRC="4344D69C" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/12/16 15:11:45 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">\r
- <power_up_trigger position="pre" storage_qualifier_disabled="no"/>\r
- <events use_custom_flow_control="no">\r
- <level enabled="yes" name="condition1" type="basic">\r
- <power_up enabled="yes">\r
- </power_up><op_node/>\r
- </level>\r
- </events>\r
- <storage_qualifier_events>\r
- <transitional>1111111111111111111111111111111111111111111111111\r
- <pwr_up_transitional>1111111111111111111111111111111111111111111111111</pwr_up_transitional>\r
- </transitional>\r
- <storage_qualifier_level type="basic">\r
- <power_up>\r
- </power_up>\r
- <op_node/>\r
- </storage_qualifier_level>\r
- <storage_qualifier_level type="basic">\r
- <power_up>\r
- </power_up>\r
- <op_node/>\r
- </storage_qualifier_level>\r
- <storage_qualifier_level type="basic">\r
- <power_up>\r
- </power_up>\r
- <op_node/>\r
- </storage_qualifier_level>\r
- </storage_qualifier_events>\r
- <log>\r
- <data global_temp="1" name="log: 2013/12/16 15:17:36 #0" power_up_mode="false" sample_depth="127" trigger_position="16">0111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000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- <extradata>1111111111111111T11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>\r
- </log>\r
- </trigger>\r
- </signal_set>\r
- <position_info>\r
- <single attribute="active tab" value="0"/>\r
- <single attribute="data vertical scroll position" value="0"/>\r
- <single attribute="data horizontal scroll position" value="95"/>\r
- <single attribute="zoom level numerator" value="4"/>\r
- <single attribute="zoom level denominator" value="1"/>\r
- <single attribute="zoom offset numerator" value="130945"/>\r
- <single attribute="zoom offset denominator" value="4"/>\r
- <multi attribute="timebars" size="3" value="127,51,43"/>\r
- </position_info>\r
- </instance>\r
- <mnemonics/>\r
- <global_info>\r
- <single attribute="active instance" value="0"/>\r
- <single attribute="config widget visible" value="1"/>\r
- <single attribute="data log widget visible" value="1"/>\r
- <single attribute="hierarchy widget visible" value="1"/>\r
- <single attribute="instance widget visible" value="1"/>\r
- <single attribute="jtag widget visible" value="1"/>\r
- <multi attribute="column width" size="23" value="34,34,210,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>\r
- <multi attribute="frame size" size="2" value="1471,791"/>\r
- <multi attribute="jtag widget size" size="2" value="334,120"/>\r
- </global_info>\r
- <static_plugin_mnemonics/>\r
-</session>\r
+++ /dev/null
-<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C(15|20) (0x020B30DD)" sof_file="output_files/qt_proj_test5.sof">\r
- <display_tree gui_logging_enabled="0">\r
- <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>\r
- </display_tree>\r
- <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">\r
- <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>\r
- <signal_set global_temp="1" is_expanded="true" name="signal_set: 2013/12/16 15:11:45 #0">\r
- <clock name="dram_clk" polarity="posedge" tap_mode="classic"/>\r
- <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>\r
- <top_entity/>\r
- <signal_vec>\r
- <trigger_input_vec>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_cyc_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_stb_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_we_i" tap_mode="classic"/>\r
- </trigger_input_vec>\r
- <data_input_vec>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_cyc_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_stb_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_we_i" tap_mode="classic"/>\r
- </data_input_vec>\r
- <storage_qualifier_input_vec>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_cyc_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_stb_i" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" tap_mode="classic"/>\r
- <wire name="vga_ctl:vga_ctl_inst|wbs_we_i" tap_mode="classic"/>\r
- </storage_qualifier_input_vec>\r
- </signal_vec>\r
- <presentation>\r
- <unified_setup_data_view>\r
- <node name="vga_ctl:vga_ctl_inst|wbs_adr_i" order="msb_to_lsb" type="combinatorial">\r
- <node data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="combinatorial"/>\r
- <node data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="combinatorial"/>\r
- <node data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="combinatorial"/>\r
- <node data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="combinatorial"/>\r
- <node data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="combinatorial"/>\r
- <node data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="combinatorial"/>\r
- <node data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="combinatorial"/>\r
- <node data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="combinatorial"/>\r
- <node data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="combinatorial"/>\r
- <node data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="combinatorial"/>\r
- <node data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="combinatorial"/>\r
- <node data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="combinatorial"/>\r
- <node data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>\r
- <node data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>\r
- <node data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>\r
- <node data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="combinatorial"/>\r
- <node data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="combinatorial"/>\r
- <node data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="combinatorial"/>\r
- <node data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="combinatorial"/>\r
- <node data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="combinatorial"/>\r
- <node data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="combinatorial"/>\r
- <node data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="combinatorial"/>\r
- </node>\r
- <node name="vga_ctl:vga_ctl_inst|wbs_dat_i" order="msb_to_lsb" type="combinatorial">\r
- <node data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>\r
- <node data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>\r
- <node data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>\r
- <node data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>\r
- <node data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>\r
- <node data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>\r
- <node data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>\r
- <node data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>\r
- <node data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>\r
- <node data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>\r
- <node data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>\r
- <node data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>\r
- <node data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>\r
- <node data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>\r
- <node data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>\r
- <node data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>\r
- </node>\r
- <node name="vga_ctl:vga_ctl_inst|wbs_tga_i" order="msb_to_lsb" type="combinatorial">\r
- <node data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>\r
- <node data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>\r
- <node data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>\r
- <node data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>\r
- <node data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>\r
- <node data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>\r
- <node data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>\r
- <node data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>\r
- </node>\r
- <node data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_we_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>\r
- <node data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_stb_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>\r
- <node data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_cyc_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>\r
- </unified_setup_data_view>\r
- <data_view>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_adr_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="combinatorial"/>\r
- <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="combinatorial"/>\r
- <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="combinatorial"/>\r
- <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="combinatorial"/>\r
- <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="combinatorial"/>\r
- <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="combinatorial"/>\r
- <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="combinatorial"/>\r
- <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="combinatorial"/>\r
- <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="combinatorial"/>\r
- <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="combinatorial"/>\r
- <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="combinatorial"/>\r
- <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="combinatorial"/>\r
- <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>\r
- <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>\r
- <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>\r
- <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="combinatorial"/>\r
- <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="combinatorial"/>\r
- <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="combinatorial"/>\r
- <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="combinatorial"/>\r
- <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="combinatorial"/>\r
- <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="combinatorial"/>\r
- <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_dat_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>\r
- <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>\r
- <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>\r
- <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>\r
- <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>\r
- <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>\r
- <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>\r
- <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>\r
- <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>\r
- <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>\r
- <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>\r
- <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>\r
- <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>\r
- <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>\r
- <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>\r
- <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_tga_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>\r
- <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>\r
- <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>\r
- <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>\r
- <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>\r
- <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>\r
- <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>\r
- <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>\r
- </bus>\r
- <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_we_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>\r
- <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_stb_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>\r
- <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_cyc_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>\r
- </data_view>\r
- <setup_view>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_adr_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="13" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="combinatorial"/>\r
- <net data_index="12" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="combinatorial"/>\r
- <net data_index="10" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" trigger_index="10" type="combinatorial"/>\r
- <net data_index="9" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="combinatorial"/>\r
- <net data_index="8" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="combinatorial"/>\r
- <net data_index="7" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="combinatorial"/>\r
- <net data_index="6" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="combinatorial"/>\r
- <net data_index="5" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="combinatorial"/>\r
- <net data_index="4" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="combinatorial"/>\r
- <net data_index="3" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="combinatorial"/>\r
- <net data_index="2" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="combinatorial"/>\r
- <net data_index="1" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="combinatorial"/>\r
- <net data_index="21" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="combinatorial"/>\r
- <net data_index="20" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="combinatorial"/>\r
- <net data_index="19" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="combinatorial"/>\r
- <net data_index="18" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="combinatorial"/>\r
- <net data_index="17" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="combinatorial"/>\r
- <net data_index="16" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="combinatorial"/>\r
- <net data_index="15" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="combinatorial"/>\r
- <net data_index="14" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="combinatorial"/>\r
- <net data_index="11" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="combinatorial"/>\r
- <net data_index="0" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_adr_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_dat_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="29" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="29" type="combinatorial"/>\r
- <net data_index="28" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="28" type="combinatorial"/>\r
- <net data_index="27" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="combinatorial"/>\r
- <net data_index="26" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="combinatorial"/>\r
- <net data_index="25" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="combinatorial"/>\r
- <net data_index="24" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="combinatorial"/>\r
- <net data_index="38" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="38" type="combinatorial"/>\r
- <net data_index="37" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="37" type="combinatorial"/>\r
- <net data_index="36" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="36" type="combinatorial"/>\r
- <net data_index="35" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="35" type="combinatorial"/>\r
- <net data_index="34" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="34" type="combinatorial"/>\r
- <net data_index="33" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="33" type="combinatorial"/>\r
- <net data_index="32" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="32" type="combinatorial"/>\r
- <net data_index="31" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="31" type="combinatorial"/>\r
- <net data_index="30" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="30" type="combinatorial"/>\r
- <net data_index="23" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_dat_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="combinatorial"/>\r
- </bus>\r
- <bus name="vga_ctl:vga_ctl_inst|wbs_tga_i" order="msb_to_lsb" type="combinatorial">\r
- <net data_index="47" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="classic" trigger_index="47" type="combinatorial"/>\r
- <net data_index="46" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="classic" trigger_index="46" type="combinatorial"/>\r
- <net data_index="45" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" trigger_index="45" type="combinatorial"/>\r
- <net data_index="44" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="44" type="combinatorial"/>\r
- <net data_index="43" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="43" type="combinatorial"/>\r
- <net data_index="42" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="42" type="combinatorial"/>\r
- <net data_index="41" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="41" type="combinatorial"/>\r
- <net data_index="40" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_tga_i[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="40" type="combinatorial"/>\r
- </bus>\r
- <net data_index="48" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_we_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="classic" trigger_index="48" type="combinatorial"/>\r
- <net data_index="39" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_stb_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="39" type="combinatorial"/>\r
- <net data_index="22" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="vga_ctl:vga_ctl_inst|wbs_cyc_i" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="combinatorial"/>\r
- </setup_view>\r
- <trigger_in_editor/>\r
- <trigger_out_editor/>\r
- </presentation>\r
- <trigger CRC="4344D69C" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/12/16 15:11:45 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">\r
- <power_up_trigger position="pre" storage_qualifier_disabled="no"/>\r
- <events use_custom_flow_control="no">\r
- <level enabled="yes" name="condition1" type="basic">\r
- <power_up enabled="yes">\r
- </power_up><op_node/>\r
- </level>\r
- </events>\r
- <storage_qualifier_events>\r
- <transitional>1111111111111111111111111111111111111111111111111\r
- <pwr_up_transitional>1111111111111111111111111111111111111111111111111</pwr_up_transitional>\r
- </transitional>\r
- <storage_qualifier_level type="basic">\r
- <power_up>\r
- </power_up>\r
- <op_node/>\r
- </storage_qualifier_level>\r
- <storage_qualifier_level type="basic">\r
- <power_up>\r
- </power_up>\r
- <op_node/>\r
- </storage_qualifier_level>\r
- <storage_qualifier_level type="basic">\r
- <power_up>\r
- </power_up>\r
- <op_node/>\r
- </storage_qualifier_level>\r
- </storage_qualifier_events>\r
- <log>\r
- <data global_temp="1" name="log: 2013/12/16 15:17:36 #0" power_up_mode="false" sample_depth="127" trigger_position="16">0111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001011100100000001110010010010000101010101100000000101110010000000111001001001000010101010110000000010111001000000011100100100100001010101011000000001</data>\r
- <extradata>1111111111111111T11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>\r
- </log>\r
- </trigger>\r
- </signal_set>\r
- <position_info>\r
- <single attribute="active tab" value="0"/>\r
- <single attribute="data horizontal scroll position" value="95"/>\r
- <single attribute="data vertical scroll position" value="0"/>\r
- <single attribute="zoom level denominator" value="1"/>\r
- <single attribute="zoom level numerator" value="4"/>\r
- <single attribute="zoom offset denominator" value="4"/>\r
- <single attribute="zoom offset numerator" value="130945"/>\r
- <multi attribute="timebars" size="3" value="127,51,43"/>\r
- </position_info>\r
- </instance>\r
- <mnemonics/>\r
- <static_plugin_mnemonics/>\r
- <global_info>\r
- <single attribute="active instance" value="0"/>\r
- <single attribute="config widget visible" value="1"/>\r
- <single attribute="data log widget visible" value="1"/>\r
- <single attribute="hierarchy widget visible" value="1"/>\r
- <single attribute="instance widget visible" value="1"/>\r
- <single attribute="jtag widget visible" value="1"/>\r
- <multi attribute="column width" size="23" value="34,34,210,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>\r
- <multi attribute="frame size" size="2" value="1471,791"/>\r
- <multi attribute="jtag widget size" size="2" value="334,120"/>\r
- </global_info>\r
-</session>\r
(\r
inclk0 : IN STD_LOGIC := '0';\r
c0 : OUT STD_LOGIC ;\r
- c1 : OUT STD_LOGIC ;\r
locked : OUT STD_LOGIC \r
);\r
end component;\r
<global>\r
<pin name="inclk0" direction="input" scope="external" source="clock" />\r
<pin name="c0" direction="output" scope="external" source="clock" />\r
-<pin name="c1" direction="output" scope="external" source="clock" />\r
<pin name="locked" direction="output" scope="external" />\r
\r
</global>\r
(\r
inclk0 : IN STD_LOGIC := '0';\r
c0 : OUT STD_LOGIC ;\r
- c1 : OUT STD_LOGIC ;\r
locked : OUT STD_LOGIC \r
);\r
END vga_clk_gen;\r
SIGNAL sub_wire1 : STD_LOGIC ;\r
SIGNAL sub_wire2 : STD_LOGIC ;\r
SIGNAL sub_wire3 : STD_LOGIC ;\r
- SIGNAL sub_wire4 : STD_LOGIC ;\r
- SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);\r
- SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);\r
- SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+ SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);\r
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
\r
\r
\r
clk0_duty_cycle : NATURAL;\r
clk0_multiply_by : NATURAL;\r
clk0_phase_shift : STRING;\r
- clk1_divide_by : NATURAL;\r
- clk1_duty_cycle : NATURAL;\r
- clk1_multiply_by : NATURAL;\r
- clk1_phase_shift : STRING;\r
compensate_clock : STRING;\r
gate_lock_signal : STRING;\r
inclk0_input_frequency : NATURAL;\r
END COMPONENT;\r
\r
BEGIN\r
- sub_wire6_bv(0 DOWNTO 0) <= "0";\r
- sub_wire6 <= To_stdlogicvector(sub_wire6_bv);\r
- sub_wire3 <= sub_wire0(0);\r
- sub_wire1 <= sub_wire0(1);\r
- c1 <= sub_wire1;\r
+ sub_wire5_bv(0 DOWNTO 0) <= "0";\r
+ sub_wire5 <= To_stdlogicvector(sub_wire5_bv);\r
+ sub_wire1 <= sub_wire0(0);\r
+ c0 <= sub_wire1;\r
locked <= sub_wire2;\r
- c0 <= sub_wire3;\r
- sub_wire4 <= inclk0;\r
- sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;\r
+ sub_wire3 <= inclk0;\r
+ sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;\r
\r
altpll_component : altpll\r
GENERIC MAP (\r
- clk0_divide_by => 2,\r
+ clk0_divide_by => 50000,\r
clk0_duty_cycle => 50,\r
- clk0_multiply_by => 1,\r
+ clk0_multiply_by => 133333,\r
clk0_phase_shift => "0",\r
- clk1_divide_by => 2,\r
- clk1_duty_cycle => 50,\r
- clk1_multiply_by => 3,\r
- clk1_phase_shift => "0",\r
compensate_clock => "CLK0",\r
gate_lock_signal => "NO",\r
inclk0_input_frequency => 20000,\r
port_scanread => "PORT_UNUSED",\r
port_scanwrite => "PORT_UNUSED",\r
port_clk0 => "PORT_USED",\r
- port_clk1 => "PORT_USED",\r
+ port_clk1 => "PORT_UNUSED",\r
port_clk2 => "PORT_UNUSED",\r
port_clk3 => "PORT_UNUSED",\r
port_clk4 => "PORT_UNUSED",\r
valid_lock_multiplier => 1\r
)\r
PORT MAP (\r
- inclk => sub_wire5,\r
+ inclk => sub_wire4,\r
clk => sub_wire0,\r
locked => sub_wire2\r
);\r
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"\r
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"\r
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"\r
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"\r
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"\r
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "75.000000"\r
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "133.332993"\r
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"\r
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"\r
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"\r
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"\r
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"\r
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"\r
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "75.00000000"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33300000"\r
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"\r
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"\r
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"\r
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"\r
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"\r
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"\r
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"\r
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"\r
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"\r
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"\r
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"\r
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"\r
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"\r
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"\r
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"\r
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"\r
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000"\r
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"\r
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "133333"\r
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"\r
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"\r
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"\r
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"\r
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"\r
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"\r
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"\r
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"\r
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"\r
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"\r
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"\r
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"\r
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"\r
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"\r
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"\r
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"\r
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"\r
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"\r
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"\r
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"\r
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1\r
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\r
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.vhd TRUE\r
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.ppf TRUE\r
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