"false",
"Disable IR Structurizer">;
+def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
+ "EnablePromoteAlloca",
+ "true",
+ "Enable promote alloca pass">;
+
// Target features
def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
#include "R600InstrInfo.h"
#include "SIInstrInfo.h"
+#include "llvm/ADT/SmallString.h"
+
using namespace llvm;
#define DEBUG_TYPE "amdgpu-subtarget"
FP64(false),
CaymanISA(false),
EnableIRStructurizer(true),
+ EnablePromoteAlloca(false),
EnableIfCvt(true),
WavefrontSize(0),
CFALUBug(false),
LocalMemorySize(0),
InstrItins(getInstrItineraryForCPU(GPU)) {
- ParseSubtargetFeatures(GPU, FS);
+
+ SmallString<256> FullFS("+promote-alloca,");
+ FullFS += FS;
+
+ ParseSubtargetFeatures(GPU, FullFS);
if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
InstrInfo.reset(new R600InstrInfo(*this));
bool FP64;
bool CaymanISA;
bool EnableIRStructurizer;
+ bool EnablePromoteAlloca;
bool EnableIfCvt;
unsigned WavefrontSize;
bool CFALUBug;
}
short getTexVTXClauseSize() const {
- return TexVTXClauseSize;
+ return TexVTXClauseSize;
}
Generation getGeneration() const {
return EnableIRStructurizer;
}
+ bool isPromoteAllocaEnabled() const {
+ return EnablePromoteAlloca;
+ }
+
bool isIfCvtEnabled() const {
return EnableIfCvt;
}
#include "llvm/Transforms/Scalar.h"
#include <llvm/CodeGen/Passes.h>
-
using namespace llvm;
extern "C" void LLVMInitializeR600Target() {
void AMDGPUPassConfig::addCodeGenPrepare() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
- addPass(createAMDGPUPromoteAlloca(ST));
- addPass(createSROAPass());
+ if (ST.isPromoteAllocaEnabled()) {
+ addPass(createAMDGPUPromoteAlloca(ST));
+ addPass(createSROAPass());
+ }
+
TargetPassConfig::addCodeGenPrepare();
}