}
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
+ RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
if (riscv_cpu_mxl(env) == MXL_RV64) {
}
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
- uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+ RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+ uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+ (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+ (cfg->ext_svadu ? MENVCFG_HADE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
}
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
- uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
+ uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
+ HENVCFG_HADE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;