--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module FIFO ( p_reset , m_clock );\r
+ input p_reset, m_clock;\r
+\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:46 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack );\r
+ input p_reset, m_clock;\r
+ input [7:0] i_Wdata;\r
+ input [13:0] i_Wadrs;\r
+ input [13:0] i_Radrs;\r
+ output [7:0] o_Rdata;\r
+ input fi_Wr_req;\r
+ input fi_Rd_req;\r
+ output fo_Rd_ack;\r
+ reg [13:0] r_Radrs_hld;\r
+ wire _u_VRAM_clk;\r
+ wire [7:0] _u_VRAM_d;\r
+ wire [13:0] _u_VRAM_ra;\r
+ wire [13:0] _u_VRAM_wa;\r
+ wire _u_VRAM_we;\r
+ wire [7:0] _u_VRAM_q;\r
+ wire _u_VRAM_p_reset;\r
+ wire _u_VRAM_m_clock;\r
+ wire _net_0;\r
+ reg _reg_1;\r
+ reg _reg_2;\r
+ wire _net_3;\r
+ wire _net_4;\r
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk));\r
+\r
+ assign _u_VRAM_d = i_Wdata;\r
+ assign _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)|\r
+ ((_reg_1)?r_Radrs_hld:14'b0);\r
+ assign _u_VRAM_wa = i_Wadrs;\r
+ assign _u_VRAM_we = fi_Wr_req|\r
+ ((_net_0)?1'b0:1'b0);\r
+ assign _net_0 = ~fi_Wr_req;\r
+ assign _net_3 = fi_Rd_req|_reg_2;\r
+ assign _net_4 = fi_Rd_req|_reg_1|_reg_2;\r
+ assign o_Rdata = _u_VRAM_q;\r
+ assign fo_Rd_ack = _reg_1;\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_Radrs_hld <= 14'b00000000000000;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_1 <= 1'b0;\r
+else if ((_net_4)) \r
+ _reg_1 <= _reg_2|fi_Rd_req;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_2 <= 1'b0;\r
+else if ((_reg_2)) \r
+ _reg_2 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:48 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
+\r
+module exp_ctrl ( p_reset , m_clock , i_Radrs , o_Rdata , fi_Rd_req , fo_Rd_ack , i_Wdata , i_Wadrs , fi_Wr_req );\r
+ input p_reset, m_clock;\r
+ input [13:0] i_Radrs;\r
+ output [15:0] o_Rdata;\r
+ input fi_Rd_req;\r
+ output fo_Rd_ack;\r
+ input [7:0] i_Wdata;\r
+ input [13:0] i_Wadrs;\r
+ input fi_Wr_req;\r
+ wire [15:0] w_exp_q;\r
+ wire [7:0] _u_VRAMC_i_Wdata;\r
+ wire [13:0] _u_VRAMC_i_Wadrs;\r
+ wire [13:0] _u_VRAMC_i_Radrs;\r
+ wire [7:0] _u_VRAMC_o_Rdata;\r
+ wire _u_VRAMC_fi_Wr_req;\r
+ wire _u_VRAMC_fi_Rd_req;\r
+ wire _u_VRAMC_fo_Rd_ack;\r
+ wire _u_VRAMC_p_reset;\r
+ wire _u_VRAMC_m_clock;\r
+ reg _reg_5;\r
+ wire _net_6;\r
+ wire _net_7;\r
+vram_ctrl u_VRAMC (.p_reset(p_reset), .m_clock(m_clock), .fo_Rd_ack(_u_VRAMC_fo_Rd_ack), .fi_Rd_req(_u_VRAMC_fi_Rd_req), .fi_Wr_req(_u_VRAMC_fi_Wr_req), .o_Rdata(_u_VRAMC_o_Rdata), .i_Radrs(_u_VRAMC_i_Radrs), .i_Wadrs(_u_VRAMC_i_Wadrs), .i_Wdata(_u_VRAMC_i_Wdata));\r
+\r
+ assign w_exp_q = {_u_VRAMC_o_Rdata[7],_u_VRAMC_o_Rdata[7],_u_VRAMC_o_Rdata[6],_u_VRAMC_o_Rdata[6],_u_VRAMC_o_Rdata[5],_u_VRAMC_o_Rdata[5],_u_VRAMC_o_Rdata[4],_u_VRAMC_o_Rdata[4],_u_VRAMC_o_Rdata[3],_u_VRAMC_o_Rdata[3],_u_VRAMC_o_Rdata[2],_u_VRAMC_o_Rdata[2],_u_VRAMC_o_Rdata[1],_u_VRAMC_o_Rdata[1],_u_VRAMC_o_Rdata[0],_u_VRAMC_o_Rdata[0]};\r
+ assign _u_VRAMC_i_Wdata = i_Wdata;\r
+ assign _u_VRAMC_i_Wadrs = i_Wadrs;\r
+ assign _u_VRAMC_i_Radrs = i_Radrs;\r
+ assign _u_VRAMC_fi_Wr_req = fi_Wr_req;\r
+ assign _u_VRAMC_fi_Rd_req = _net_6;\r
+ assign _net_6 = fi_Rd_req|_reg_5;\r
+ assign _net_7 = fi_Rd_req|_reg_5;\r
+ assign o_Rdata = w_exp_q;\r
+ assign fo_Rd_ack = _u_VRAMC_fo_Rd_ack;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_5 <= 1'b0;\r
+else if ((_reg_5)) \r
+ _reg_5 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:48 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:37 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module from_ctrl ( p_reset , m_clock );\r
+ input p_reset, m_clock;\r
+\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:37 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+module vram ( q, wa, ra, d, we, clk );\r
+ output [7:0] q ;\r
+ input [7:0] d ;\r
+ input [13:0] wa ;\r
+ input [13:0] ra ;\r
+ input we, clk ;\r
+ reg [13:0] read_add ;\r
+ (* remstyle = "no_rw_check" *) reg [7:0] mem[16383:0];\r
+ always @ (posedge clk) begin\r
+ if(we)\r
+ mem[wa] <= d ;\r
+ read_add <= ra ;\r
+ end\r
+ \r
+ assign q = mem[read_add];\r
+endmodule\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:33 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module vga_generate ( p_reset , m_clock , pix32_data_i , v_sync_o , h_sync_o , vga_red_o , vga_green_o , vga_blue_o , h_cnt_o , ack_req_32dot , req_32dot );\r
+ input p_reset;\r
+ input m_clock;\r
+ input [31:0] pix32_data_i;\r
+ output v_sync_o;\r
+ output h_sync_o;\r
+ output [3:0] vga_red_o;\r
+ output [3:0] vga_green_o;\r
+ output [3:0] vga_blue_o;\r
+ output [9:0] h_cnt_o;\r
+ input ack_req_32dot;\r
+ output req_32dot;\r
+ wire disp_data;\r
+ reg v_sync;\r
+ reg h_sync;\r
+ reg h_flg;\r
+ reg vdata_flg;\r
+ reg hdata_flg;\r
+ reg [9:0] h_cnt;\r
+ reg [18:0] v_cnt;\r
+ reg [4:0] bit32_cnt;\r
+ reg reg_flg;\r
+ reg reg_cnt;\r
+ reg [31:0] r1;\r
+ reg [31:0] r2;\r
+ reg data_select_flag;\r
+ wire [3:0] red;\r
+ wire [3:0] green;\r
+ wire [3:0] blue;\r
+ wire sel_disp_data;\r
+ wire _net_0;\r
+ wire _net_1;\r
+ wire _net_2;\r
+ wire _net_3;\r
+ wire _net_4;\r
+ wire _net_5;\r
+ wire _net_6;\r
+ wire _net_7;\r
+ wire _net_8;\r
+ wire _net_9;\r
+ wire _net_10;\r
+ wire _net_11;\r
+ wire _net_12;\r
+ wire _net_13;\r
+ wire _net_14;\r
+ wire _net_15;\r
+ wire _net_16;\r
+ wire _net_17;\r
+ wire _net_18;\r
+ wire _net_19;\r
+ wire _net_20;\r
+ wire _net_21;\r
+ wire _net_22;\r
+ wire _net_23;\r
+ wire _net_24;\r
+ wire _net_25;\r
+ wire _net_26;\r
+ wire _net_27;\r
+ wire _net_28;\r
+ wire _net_29;\r
+ wire _net_30;\r
+ wire _net_31;\r
+ wire _net_32;\r
+ wire _net_33;\r
+ wire _net_34;\r
+ wire _net_35;\r
+ wire _net_36;\r
+ wire _net_37;\r
+ wire _net_38;\r
+ wire _net_39;\r
+ wire _net_40;\r
+ wire _net_41;\r
+ wire _net_42;\r
+ wire _net_43;\r
+ wire _net_44;\r
+ wire _net_45;\r
+ wire _net_46;\r
+ wire _net_47;\r
+ wire _net_48;\r
+ wire _net_49;\r
+ wire _net_50;\r
+ wire _net_51;\r
+ wire _net_52;\r
+ wire _net_53;\r
+ wire _net_54;\r
+ wire _net_55;\r
+ wire _net_56;\r
+ wire _net_57;\r
+ wire _net_58;\r
+ wire _net_59;\r
+ wire _net_60;\r
+ wire _net_61;\r
+ wire _net_62;\r
+ wire _net_63;\r
+ wire _net_64;\r
+ wire _net_65;\r
+ wire _net_66;\r
+ wire _net_67;\r
+ wire _net_68;\r
+ wire _net_69;\r
+ wire _net_70;\r
+ wire _net_71;\r
+ wire _net_72;\r
+ wire _net_73;\r
+ wire _net_74;\r
+ wire _net_75;\r
+ wire _net_76;\r
+ wire _net_77;\r
+ wire _net_78;\r
+ wire _net_79;\r
+ wire _net_80;\r
+ wire _net_81;\r
+ wire _net_82;\r
+ wire _net_83;\r
+ wire _net_84;\r
+ wire _net_85;\r
+ wire _net_86;\r
+ wire _net_87;\r
+ wire _net_88;\r
+ wire _net_89;\r
+ wire _net_90;\r
+ wire _net_91;\r
+ wire _net_92;\r
+ wire _net_93;\r
+ wire _net_94;\r
+ wire _net_95;\r
+ wire _net_96;\r
+ wire _net_97;\r
+ wire _net_98;\r
+ wire _net_99;\r
+ wire _net_100;\r
+ wire _net_101;\r
+ wire _net_102;\r
+ wire _net_103;\r
+ wire _net_104;\r
+ wire _net_105;\r
+ wire _net_106;\r
+ wire _net_107;\r
+ wire _net_108;\r
+ wire _net_109;\r
+ wire _net_110;\r
+ wire _net_111;\r
+ wire _net_112;\r
+ wire _net_113;\r
+ wire _net_114;\r
+ wire _net_115;\r
+ wire _net_116;\r
+ wire _net_117;\r
+ wire _net_118;\r
+ wire _net_119;\r
+ wire _net_120;\r
+ wire _net_121;\r
+ wire _net_122;\r
+ wire _net_123;\r
+ wire _net_124;\r
+ wire _net_125;\r
+ wire _net_126;\r
+ wire _net_127;\r
+ wire _net_128;\r
+ wire _net_129;\r
+ wire _net_130;\r
+ wire _net_131;\r
+ wire _net_132;\r
+ wire _net_133;\r
+ wire _net_134;\r
+ wire _net_135;\r
+ wire _net_136;\r
+ wire _net_137;\r
+ wire _net_138;\r
+ wire _net_139;\r
+ wire _net_140;\r
+ wire _net_141;\r
+ wire _net_142;\r
+ wire _net_143;\r
+ wire _net_144;\r
+ wire _net_145;\r
+ wire _net_146;\r
+ wire _net_147;\r
+ wire _net_148;\r
+ wire _net_149;\r
+ wire _net_150;\r
+ wire _net_151;\r
+ wire _net_152;\r
+ wire _net_153;\r
+ wire _net_154;\r
+ wire _net_155;\r
+ wire _net_156;\r
+ wire _net_157;\r
+ wire _net_158;\r
+ wire _net_159;\r
+ wire _net_160;\r
+ wire _net_161;\r
+ wire _net_162;\r
+ wire _net_163;\r
+ wire _net_164;\r
+ wire _net_165;\r
+ wire _net_166;\r
+ wire _net_167;\r
+ wire _net_168;\r
+ wire _net_169;\r
+ wire _net_170;\r
+ wire _net_171;\r
+ wire _net_172;\r
+ wire _net_173;\r
+ wire _net_174;\r
+ wire _net_175;\r
+ wire _net_176;\r
+ wire _net_177;\r
+ wire _net_178;\r
+ wire _net_179;\r
+ wire _net_180;\r
+ wire _net_181;\r
+ wire _net_182;\r
+ wire _net_183;\r
+ wire _net_184;\r
+ wire _net_185;\r
+ wire _net_186;\r
+ wire _net_187;\r
+ wire _net_188;\r
+ wire _net_189;\r
+ wire _net_190;\r
+ wire _net_191;\r
+ wire _net_192;\r
+ wire _net_193;\r
+ wire _net_194;\r
+ wire _net_195;\r
+ wire _net_196;\r
+ wire _net_197;\r
+ wire _net_198;\r
+ wire _net_199;\r
+ wire _net_200;\r
+ wire _net_201;\r
+ wire _net_202;\r
+ wire _net_203;\r
+ wire _net_204;\r
+ wire _net_205;\r
+ wire _net_206;\r
+ wire _net_207;\r
+ wire _net_208;\r
+ wire _net_209;\r
+ wire _net_210;\r
+ wire _net_211;\r
+ wire _net_212;\r
+ wire _net_213;\r
+ wire _net_214;\r
+ wire _net_215;\r
+ wire _net_216;\r
+ wire _net_217;\r
+ wire _net_218;\r
+\r
+ assign disp_data = _net_10;\r
+ assign red = 4'b0000;\r
+ assign green = 4'b0000;\r
+ assign blue = ((_net_20)?4'b0000:4'b0)|\r
+ ((_net_18)?4'b1111:4'b0);\r
+ assign sel_disp_data = ((_net_218)?r2[31]:1'b0)|\r
+ ((_net_215)?r2[30]:1'b0)|\r
+ ((_net_212)?r2[29]:1'b0)|\r
+ ((_net_209)?r2[28]:1'b0)|\r
+ ((_net_206)?r2[27]:1'b0)|\r
+ ((_net_203)?r2[26]:1'b0)|\r
+ ((_net_200)?r2[25]:1'b0)|\r
+ ((_net_197)?r2[24]:1'b0)|\r
+ ((_net_194)?r2[23]:1'b0)|\r
+ ((_net_191)?r2[22]:1'b0)|\r
+ ((_net_188)?r2[21]:1'b0)|\r
+ ((_net_185)?r2[20]:1'b0)|\r
+ ((_net_182)?r2[19]:1'b0)|\r
+ ((_net_179)?r2[18]:1'b0)|\r
+ ((_net_176)?r2[17]:1'b0)|\r
+ ((_net_173)?r2[16]:1'b0)|\r
+ ((_net_170)?r2[15]:1'b0)|\r
+ ((_net_167)?r2[14]:1'b0)|\r
+ ((_net_164)?r2[13]:1'b0)|\r
+ ((_net_161)?r2[12]:1'b0)|\r
+ ((_net_158)?r2[11]:1'b0)|\r
+ ((_net_155)?r2[10]:1'b0)|\r
+ ((_net_152)?r2[9]:1'b0)|\r
+ ((_net_149)?r2[8]:1'b0)|\r
+ ((_net_146)?r2[7]:1'b0)|\r
+ ((_net_143)?r2[6]:1'b0)|\r
+ ((_net_140)?r2[5]:1'b0)|\r
+ ((_net_137)?r2[4]:1'b0)|\r
+ ((_net_134)?r2[3]:1'b0)|\r
+ ((_net_131)?r2[2]:1'b0)|\r
+ ((_net_128)?r2[1]:1'b0)|\r
+ ((_net_124)?r2[0]:1'b0)|\r
+ ((_net_121)?r1[31]:1'b0)|\r
+ ((_net_118)?r1[30]:1'b0)|\r
+ ((_net_115)?r1[29]:1'b0)|\r
+ ((_net_112)?r1[28]:1'b0)|\r
+ ((_net_109)?r1[27]:1'b0)|\r
+ ((_net_106)?r1[26]:1'b0)|\r
+ ((_net_103)?r1[25]:1'b0)|\r
+ ((_net_100)?r1[24]:1'b0)|\r
+ ((_net_97)?r1[23]:1'b0)|\r
+ ((_net_94)?r1[22]:1'b0)|\r
+ ((_net_91)?r1[21]:1'b0)|\r
+ ((_net_88)?r1[20]:1'b0)|\r
+ ((_net_85)?r1[19]:1'b0)|\r
+ ((_net_82)?r1[18]:1'b0)|\r
+ ((_net_79)?r1[17]:1'b0)|\r
+ ((_net_76)?r1[16]:1'b0)|\r
+ ((_net_73)?r1[15]:1'b0)|\r
+ ((_net_70)?r1[14]:1'b0)|\r
+ ((_net_67)?r1[13]:1'b0)|\r
+ ((_net_64)?r1[12]:1'b0)|\r
+ ((_net_61)?r1[11]:1'b0)|\r
+ ((_net_58)?r1[10]:1'b0)|\r
+ ((_net_55)?r1[9]:1'b0)|\r
+ ((_net_52)?r1[8]:1'b0)|\r
+ ((_net_49)?r1[7]:1'b0)|\r
+ ((_net_46)?r1[6]:1'b0)|\r
+ ((_net_43)?r1[5]:1'b0)|\r
+ ((_net_40)?r1[4]:1'b0)|\r
+ ((_net_37)?r1[3]:1'b0)|\r
+ ((_net_34)?r1[2]:1'b0)|\r
+ ((_net_31)?r1[1]:1'b0)|\r
+ ((_net_27)?r1[0]:1'b0);\r
+ assign _net_0 = (h_cnt)==(10'b1100100000);\r
+ assign _net_1 = (h_cnt)==(10'b1100001110);\r
+ assign _net_2 = (h_cnt)==(10'b0010001110);\r
+ assign _net_3 = (h_cnt)==(10'b0001100000);\r
+ assign _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3);\r
+ assign _net_5 = (v_cnt)==(19'b1100101110000011111);\r
+ assign _net_6 = (v_cnt)==(19'b1100011110011011111);\r
+ assign _net_7 = (v_cnt)==(19'b0000110000011011111);\r
+ assign _net_8 = (v_cnt)==(19'b0000000011000111111);\r
+ assign _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8);\r
+ assign _net_10 = hdata_flg&vdata_flg;\r
+ assign _net_11 = (((h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111)));\r
+ assign _net_12 = (bit32_cnt)==(5'b00000);\r
+ assign _net_13 = _net_11&_net_12;\r
+ assign _net_14 = (bit32_cnt)==(5'b11111);\r
+ assign _net_15 = _net_11&_net_14;\r
+ assign _net_16 = _net_11&(~_net_14);\r
+ assign _net_17 = ~_net_11;\r
+ assign _net_18 = hdata_flg&vdata_flg;\r
+ assign _net_19 = ~_net_18;\r
+ assign _net_20 = ~_net_18;\r
+ assign _net_21 = ~_net_18;\r
+ assign _net_22 = ack_req_32dot&data_select_flag;\r
+ assign _net_23 = ack_req_32dot&(~data_select_flag);\r
+ assign _net_24 = ~reg_flg;\r
+ assign _net_25 = (bit32_cnt)==(5'b11111);\r
+ assign _net_26 = disp_data&_net_24;\r
+ assign _net_27 = (disp_data&_net_24)&_net_25;\r
+ assign _net_28 = (disp_data&_net_24)&_net_25;\r
+ assign _net_29 = (bit32_cnt)==(5'b11110);\r
+ assign _net_30 = disp_data&_net_24;\r
+ assign _net_31 = (disp_data&_net_24)&_net_29;\r
+ assign _net_32 = (bit32_cnt)==(5'b11101);\r
+ assign _net_33 = disp_data&_net_24;\r
+ assign _net_34 = (disp_data&_net_24)&_net_32;\r
+ assign _net_35 = (bit32_cnt)==(5'b11100);\r
+ assign _net_36 = disp_data&_net_24;\r
+ assign _net_37 = (disp_data&_net_24)&_net_35;\r
+ assign _net_38 = (bit32_cnt)==(5'b11011);\r
+ assign _net_39 = disp_data&_net_24;\r
+ assign _net_40 = (disp_data&_net_24)&_net_38;\r
+ assign _net_41 = (bit32_cnt)==(5'b11010);\r
+ assign _net_42 = disp_data&_net_24;\r
+ assign _net_43 = (disp_data&_net_24)&_net_41;\r
+ assign _net_44 = (bit32_cnt)==(5'b11001);\r
+ assign _net_45 = disp_data&_net_24;\r
+ assign _net_46 = (disp_data&_net_24)&_net_44;\r
+ assign _net_47 = (bit32_cnt)==(5'b11000);\r
+ assign _net_48 = disp_data&_net_24;\r
+ assign _net_49 = (disp_data&_net_24)&_net_47;\r
+ assign _net_50 = (bit32_cnt)==(5'b10111);\r
+ assign _net_51 = disp_data&_net_24;\r
+ assign _net_52 = (disp_data&_net_24)&_net_50;\r
+ assign _net_53 = (bit32_cnt)==(5'b10110);\r
+ assign _net_54 = disp_data&_net_24;\r
+ assign _net_55 = (disp_data&_net_24)&_net_53;\r
+ assign _net_56 = (bit32_cnt)==(5'b10101);\r
+ assign _net_57 = disp_data&_net_24;\r
+ assign _net_58 = (disp_data&_net_24)&_net_56;\r
+ assign _net_59 = (bit32_cnt)==(5'b10100);\r
+ assign _net_60 = disp_data&_net_24;\r
+ assign _net_61 = (disp_data&_net_24)&_net_59;\r
+ assign _net_62 = (bit32_cnt)==(5'b10011);\r
+ assign _net_63 = disp_data&_net_24;\r
+ assign _net_64 = (disp_data&_net_24)&_net_62;\r
+ assign _net_65 = (bit32_cnt)==(5'b10010);\r
+ assign _net_66 = disp_data&_net_24;\r
+ assign _net_67 = (disp_data&_net_24)&_net_65;\r
+ assign _net_68 = (bit32_cnt)==(5'b10001);\r
+ assign _net_69 = disp_data&_net_24;\r
+ assign _net_70 = (disp_data&_net_24)&_net_68;\r
+ assign _net_71 = (bit32_cnt)==(5'b10000);\r
+ assign _net_72 = disp_data&_net_24;\r
+ assign _net_73 = (disp_data&_net_24)&_net_71;\r
+ assign _net_74 = (bit32_cnt)==(5'b01111);\r
+ assign _net_75 = disp_data&_net_24;\r
+ assign _net_76 = (disp_data&_net_24)&_net_74;\r
+ assign _net_77 = (bit32_cnt)==(5'b01110);\r
+ assign _net_78 = disp_data&_net_24;\r
+ assign _net_79 = (disp_data&_net_24)&_net_77;\r
+ assign _net_80 = (bit32_cnt)==(5'b01101);\r
+ assign _net_81 = disp_data&_net_24;\r
+ assign _net_82 = (disp_data&_net_24)&_net_80;\r
+ assign _net_83 = (bit32_cnt)==(5'b01100);\r
+ assign _net_84 = disp_data&_net_24;\r
+ assign _net_85 = (disp_data&_net_24)&_net_83;\r
+ assign _net_86 = (bit32_cnt)==(5'b01011);\r
+ assign _net_87 = disp_data&_net_24;\r
+ assign _net_88 = (disp_data&_net_24)&_net_86;\r
+ assign _net_89 = (bit32_cnt)==(5'b01010);\r
+ assign _net_90 = disp_data&_net_24;\r
+ assign _net_91 = (disp_data&_net_24)&_net_89;\r
+ assign _net_92 = (bit32_cnt)==(5'b01001);\r
+ assign _net_93 = disp_data&_net_24;\r
+ assign _net_94 = (disp_data&_net_24)&_net_92;\r
+ assign _net_95 = (bit32_cnt)==(5'b01000);\r
+ assign _net_96 = disp_data&_net_24;\r
+ assign _net_97 = (disp_data&_net_24)&_net_95;\r
+ assign _net_98 = (bit32_cnt)==(5'b00111);\r
+ assign _net_99 = disp_data&_net_24;\r
+ assign _net_100 = (disp_data&_net_24)&_net_98;\r
+ assign _net_101 = (bit32_cnt)==(5'b00110);\r
+ assign _net_102 = disp_data&_net_24;\r
+ assign _net_103 = (disp_data&_net_24)&_net_101;\r
+ assign _net_104 = (bit32_cnt)==(5'b00101);\r
+ assign _net_105 = disp_data&_net_24;\r
+ assign _net_106 = (disp_data&_net_24)&_net_104;\r
+ assign _net_107 = (bit32_cnt)==(5'b00100);\r
+ assign _net_108 = disp_data&_net_24;\r
+ assign _net_109 = (disp_data&_net_24)&_net_107;\r
+ assign _net_110 = (bit32_cnt)==(5'b00011);\r
+ assign _net_111 = disp_data&_net_24;\r
+ assign _net_112 = (disp_data&_net_24)&_net_110;\r
+ assign _net_113 = (bit32_cnt)==(5'b00010);\r
+ assign _net_114 = disp_data&_net_24;\r
+ assign _net_115 = (disp_data&_net_24)&_net_113;\r
+ assign _net_116 = (bit32_cnt)==(5'b00001);\r
+ assign _net_117 = disp_data&_net_24;\r
+ assign _net_118 = (disp_data&_net_24)&_net_116;\r
+ assign _net_119 = (bit32_cnt)==(5'b00000);\r
+ assign _net_120 = disp_data&_net_24;\r
+ assign _net_121 = (disp_data&_net_24)&_net_119;\r
+ assign _net_122 = (bit32_cnt)==(5'b11111);\r
+ assign _net_123 = disp_data&(~_net_24);\r
+ assign _net_124 = (disp_data&(~_net_24))&_net_122;\r
+ assign _net_125 = (disp_data&(~_net_24))&_net_122;\r
+ assign _net_126 = (bit32_cnt)==(5'b11110);\r
+ assign _net_127 = disp_data&(~_net_24);\r
+ assign _net_128 = (disp_data&(~_net_24))&_net_126;\r
+ assign _net_129 = (bit32_cnt)==(5'b11101);\r
+ assign _net_130 = disp_data&(~_net_24);\r
+ assign _net_131 = (disp_data&(~_net_24))&_net_129;\r
+ assign _net_132 = (bit32_cnt)==(5'b11100);\r
+ assign _net_133 = disp_data&(~_net_24);\r
+ assign _net_134 = (disp_data&(~_net_24))&_net_132;\r
+ assign _net_135 = (bit32_cnt)==(5'b11011);\r
+ assign _net_136 = disp_data&(~_net_24);\r
+ assign _net_137 = (disp_data&(~_net_24))&_net_135;\r
+ assign _net_138 = (bit32_cnt)==(5'b11010);\r
+ assign _net_139 = disp_data&(~_net_24);\r
+ assign _net_140 = (disp_data&(~_net_24))&_net_138;\r
+ assign _net_141 = (bit32_cnt)==(5'b11001);\r
+ assign _net_142 = disp_data&(~_net_24);\r
+ assign _net_143 = (disp_data&(~_net_24))&_net_141;\r
+ assign _net_144 = (bit32_cnt)==(5'b11000);\r
+ assign _net_145 = disp_data&(~_net_24);\r
+ assign _net_146 = (disp_data&(~_net_24))&_net_144;\r
+ assign _net_147 = (bit32_cnt)==(5'b10111);\r
+ assign _net_148 = disp_data&(~_net_24);\r
+ assign _net_149 = (disp_data&(~_net_24))&_net_147;\r
+ assign _net_150 = (bit32_cnt)==(5'b10110);\r
+ assign _net_151 = disp_data&(~_net_24);\r
+ assign _net_152 = (disp_data&(~_net_24))&_net_150;\r
+ assign _net_153 = (bit32_cnt)==(5'b10101);\r
+ assign _net_154 = disp_data&(~_net_24);\r
+ assign _net_155 = (disp_data&(~_net_24))&_net_153;\r
+ assign _net_156 = (bit32_cnt)==(5'b10100);\r
+ assign _net_157 = disp_data&(~_net_24);\r
+ assign _net_158 = (disp_data&(~_net_24))&_net_156;\r
+ assign _net_159 = (bit32_cnt)==(5'b10011);\r
+ assign _net_160 = disp_data&(~_net_24);\r
+ assign _net_161 = (disp_data&(~_net_24))&_net_159;\r
+ assign _net_162 = (bit32_cnt)==(5'b10010);\r
+ assign _net_163 = disp_data&(~_net_24);\r
+ assign _net_164 = (disp_data&(~_net_24))&_net_162;\r
+ assign _net_165 = (bit32_cnt)==(5'b10001);\r
+ assign _net_166 = disp_data&(~_net_24);\r
+ assign _net_167 = (disp_data&(~_net_24))&_net_165;\r
+ assign _net_168 = (bit32_cnt)==(5'b10000);\r
+ assign _net_169 = disp_data&(~_net_24);\r
+ assign _net_170 = (disp_data&(~_net_24))&_net_168;\r
+ assign _net_171 = (bit32_cnt)==(5'b01111);\r
+ assign _net_172 = disp_data&(~_net_24);\r
+ assign _net_173 = (disp_data&(~_net_24))&_net_171;\r
+ assign _net_174 = (bit32_cnt)==(5'b01110);\r
+ assign _net_175 = disp_data&(~_net_24);\r
+ assign _net_176 = (disp_data&(~_net_24))&_net_174;\r
+ assign _net_177 = (bit32_cnt)==(5'b01101);\r
+ assign _net_178 = disp_data&(~_net_24);\r
+ assign _net_179 = (disp_data&(~_net_24))&_net_177;\r
+ assign _net_180 = (bit32_cnt)==(5'b01100);\r
+ assign _net_181 = disp_data&(~_net_24);\r
+ assign _net_182 = (disp_data&(~_net_24))&_net_180;\r
+ assign _net_183 = (bit32_cnt)==(5'b01011);\r
+ assign _net_184 = disp_data&(~_net_24);\r
+ assign _net_185 = (disp_data&(~_net_24))&_net_183;\r
+ assign _net_186 = (bit32_cnt)==(5'b01010);\r
+ assign _net_187 = disp_data&(~_net_24);\r
+ assign _net_188 = (disp_data&(~_net_24))&_net_186;\r
+ assign _net_189 = (bit32_cnt)==(5'b01001);\r
+ assign _net_190 = disp_data&(~_net_24);\r
+ assign _net_191 = (disp_data&(~_net_24))&_net_189;\r
+ assign _net_192 = (bit32_cnt)==(5'b01000);\r
+ assign _net_193 = disp_data&(~_net_24);\r
+ assign _net_194 = (disp_data&(~_net_24))&_net_192;\r
+ assign _net_195 = (bit32_cnt)==(5'b00111);\r
+ assign _net_196 = disp_data&(~_net_24);\r
+ assign _net_197 = (disp_data&(~_net_24))&_net_195;\r
+ assign _net_198 = (bit32_cnt)==(5'b00110);\r
+ assign _net_199 = disp_data&(~_net_24);\r
+ assign _net_200 = (disp_data&(~_net_24))&_net_198;\r
+ assign _net_201 = (bit32_cnt)==(5'b00101);\r
+ assign _net_202 = disp_data&(~_net_24);\r
+ assign _net_203 = (disp_data&(~_net_24))&_net_201;\r
+ assign _net_204 = (bit32_cnt)==(5'b00100);\r
+ assign _net_205 = disp_data&(~_net_24);\r
+ assign _net_206 = (disp_data&(~_net_24))&_net_204;\r
+ assign _net_207 = (bit32_cnt)==(5'b00011);\r
+ assign _net_208 = disp_data&(~_net_24);\r
+ assign _net_209 = (disp_data&(~_net_24))&_net_207;\r
+ assign _net_210 = (bit32_cnt)==(5'b00010);\r
+ assign _net_211 = disp_data&(~_net_24);\r
+ assign _net_212 = (disp_data&(~_net_24))&_net_210;\r
+ assign _net_213 = (bit32_cnt)==(5'b00001);\r
+ assign _net_214 = disp_data&(~_net_24);\r
+ assign _net_215 = (disp_data&(~_net_24))&_net_213;\r
+ assign _net_216 = (bit32_cnt)==(5'b00000);\r
+ assign _net_217 = disp_data&(~_net_24);\r
+ assign _net_218 = (disp_data&(~_net_24))&_net_216;\r
+ assign v_sync_o = v_sync;\r
+ assign h_sync_o = h_sync;\r
+ assign vga_red_o = red;\r
+ assign vga_green_o = green;\r
+ assign vga_blue_o = blue;\r
+ assign h_cnt_o = h_cnt;\r
+ assign req_32dot = _net_13;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ v_sync <= 1'b0;\r
+else if ((_net_8|_net_5)) \r
+ v_sync <= ~v_sync;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ h_sync <= 1'b0;\r
+else if ((_net_3|_net_0)) \r
+ h_sync <= ~h_sync;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ h_flg <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ vdata_flg <= 1'b0;\r
+else if ((_net_7)|(_net_6)) \r
+ vdata_flg <= ((_net_7) ?1'b1:1'b0)|\r
+ ((_net_6) ?1'b0:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ hdata_flg <= 1'b0;\r
+else if ((_net_2)|(_net_1)) \r
+ hdata_flg <= ((_net_2) ?1'b1:1'b0)|\r
+ ((_net_1) ?1'b0:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ h_cnt <= 10'b0000000000;\r
+else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) \r
+ h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(h_cnt)+(10'b0000000001):10'b0)|\r
+ ((_net_0) ?10'b0000000000:10'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ v_cnt <= 19'b0000000000000000000;\r
+else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) \r
+ v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(v_cnt)+(19'b0000000000000000001):19'b0)|\r
+ ((_net_5) ?19'b0000000000000000000:19'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ bit32_cnt <= 5'b00000;\r
+else if ((disp_data)|(_net_16)|(_net_17|_net_15)) \r
+ bit32_cnt <= ((disp_data) ?(bit32_cnt)+(5'b00001):5'b0)|\r
+ ((_net_16) ?(bit32_cnt)+(5'b00001):5'b0)|\r
+ ((_net_17|_net_15) ?5'b00000:5'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ reg_flg <= 1'b0;\r
+else if ((_net_125|_net_28)) \r
+ reg_flg <= ~reg_flg;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ reg_cnt <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r1 <= 32'b00000000000000000000000000000000;\r
+else if ((_net_22)) \r
+ r1 <= pix32_data_i;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r2 <= 32'b00000000000000000000000000000000;\r
+else if ((_net_23)) \r
+ r2 <= pix32_data_i;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ data_select_flag <= 1'b0;\r
+else if ((ack_req_32dot)) \r
+ data_select_flag <= ~data_select_flag;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:36 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:31 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module vga_generate ( p_reset , m_clock , pix32_data_i , v_sync_o , h_sync_o , vga_red_o , vga_green_o , vga_blue_o , h_cnt_o , ack_req_32dot , req_32dot );\r
+ input p_reset;\r
+ input m_clock;\r
+ input [31:0] pix32_data_i;\r
+ output v_sync_o;\r
+ output h_sync_o;\r
+ output [3:0] vga_red_o;\r
+ output [3:0] vga_green_o;\r
+ output [3:0] vga_blue_o;\r
+ output [9:0] h_cnt_o;\r
+ input ack_req_32dot;\r
+ output req_32dot;\r
+ wire disp_data;\r
+ reg v_sync;\r
+ reg h_sync;\r
+ reg h_flg;\r
+ reg vdata_flg;\r
+ reg hdata_flg;\r
+ reg [9:0] h_cnt;\r
+ reg [18:0] v_cnt;\r
+ reg [4:0] bit32_cnt;\r
+ reg reg_flg;\r
+ reg reg_cnt;\r
+ reg [31:0] r1;\r
+ reg [31:0] r2;\r
+ reg data_select_flag;\r
+ wire [3:0] red;\r
+ wire [3:0] green;\r
+ wire [3:0] blue;\r
+ wire sel_disp_data;\r
+ wire _net_0;\r
+ wire _net_1;\r
+ wire _net_2;\r
+ wire _net_3;\r
+ wire _net_4;\r
+ wire _net_5;\r
+ wire _net_6;\r
+ wire _net_7;\r
+ wire _net_8;\r
+ wire _net_9;\r
+ wire _net_10;\r
+ wire _net_11;\r
+ wire _net_12;\r
+ wire _net_13;\r
+ wire _net_14;\r
+ wire _net_15;\r
+ wire _net_16;\r
+ wire _net_17;\r
+ wire _net_18;\r
+ wire _net_19;\r
+ wire _net_20;\r
+ wire _net_21;\r
+ wire _net_22;\r
+ wire _net_23;\r
+ wire _net_24;\r
+ wire _net_25;\r
+ wire _net_26;\r
+ wire _net_27;\r
+ wire _net_28;\r
+ wire _net_29;\r
+ wire _net_30;\r
+ wire _net_31;\r
+ wire _net_32;\r
+ wire _net_33;\r
+ wire _net_34;\r
+ wire _net_35;\r
+ wire _net_36;\r
+ wire _net_37;\r
+ wire _net_38;\r
+ wire _net_39;\r
+ wire _net_40;\r
+ wire _net_41;\r
+ wire _net_42;\r
+ wire _net_43;\r
+ wire _net_44;\r
+ wire _net_45;\r
+ wire _net_46;\r
+ wire _net_47;\r
+ wire _net_48;\r
+ wire _net_49;\r
+ wire _net_50;\r
+ wire _net_51;\r
+ wire _net_52;\r
+ wire _net_53;\r
+ wire _net_54;\r
+ wire _net_55;\r
+ wire _net_56;\r
+ wire _net_57;\r
+ wire _net_58;\r
+ wire _net_59;\r
+ wire _net_60;\r
+ wire _net_61;\r
+ wire _net_62;\r
+ wire _net_63;\r
+ wire _net_64;\r
+ wire _net_65;\r
+ wire _net_66;\r
+ wire _net_67;\r
+ wire _net_68;\r
+ wire _net_69;\r
+ wire _net_70;\r
+ wire _net_71;\r
+ wire _net_72;\r
+ wire _net_73;\r
+ wire _net_74;\r
+ wire _net_75;\r
+ wire _net_76;\r
+ wire _net_77;\r
+ wire _net_78;\r
+ wire _net_79;\r
+ wire _net_80;\r
+ wire _net_81;\r
+ wire _net_82;\r
+ wire _net_83;\r
+ wire _net_84;\r
+ wire _net_85;\r
+ wire _net_86;\r
+ wire _net_87;\r
+ wire _net_88;\r
+ wire _net_89;\r
+ wire _net_90;\r
+ wire _net_91;\r
+ wire _net_92;\r
+ wire _net_93;\r
+ wire _net_94;\r
+ wire _net_95;\r
+ wire _net_96;\r
+ wire _net_97;\r
+ wire _net_98;\r
+ wire _net_99;\r
+ wire _net_100;\r
+ wire _net_101;\r
+ wire _net_102;\r
+ wire _net_103;\r
+ wire _net_104;\r
+ wire _net_105;\r
+ wire _net_106;\r
+ wire _net_107;\r
+ wire _net_108;\r
+ wire _net_109;\r
+ wire _net_110;\r
+ wire _net_111;\r
+ wire _net_112;\r
+ wire _net_113;\r
+ wire _net_114;\r
+ wire _net_115;\r
+ wire _net_116;\r
+ wire _net_117;\r
+ wire _net_118;\r
+ wire _net_119;\r
+ wire _net_120;\r
+ wire _net_121;\r
+ wire _net_122;\r
+ wire _net_123;\r
+ wire _net_124;\r
+ wire _net_125;\r
+ wire _net_126;\r
+ wire _net_127;\r
+ wire _net_128;\r
+ wire _net_129;\r
+ wire _net_130;\r
+ wire _net_131;\r
+ wire _net_132;\r
+ wire _net_133;\r
+ wire _net_134;\r
+ wire _net_135;\r
+ wire _net_136;\r
+ wire _net_137;\r
+ wire _net_138;\r
+ wire _net_139;\r
+ wire _net_140;\r
+ wire _net_141;\r
+ wire _net_142;\r
+ wire _net_143;\r
+ wire _net_144;\r
+ wire _net_145;\r
+ wire _net_146;\r
+ wire _net_147;\r
+ wire _net_148;\r
+ wire _net_149;\r
+ wire _net_150;\r
+ wire _net_151;\r
+ wire _net_152;\r
+ wire _net_153;\r
+ wire _net_154;\r
+ wire _net_155;\r
+ wire _net_156;\r
+ wire _net_157;\r
+ wire _net_158;\r
+ wire _net_159;\r
+ wire _net_160;\r
+ wire _net_161;\r
+ wire _net_162;\r
+ wire _net_163;\r
+ wire _net_164;\r
+ wire _net_165;\r
+ wire _net_166;\r
+ wire _net_167;\r
+ wire _net_168;\r
+ wire _net_169;\r
+ wire _net_170;\r
+ wire _net_171;\r
+ wire _net_172;\r
+ wire _net_173;\r
+ wire _net_174;\r
+ wire _net_175;\r
+ wire _net_176;\r
+ wire _net_177;\r
+ wire _net_178;\r
+ wire _net_179;\r
+ wire _net_180;\r
+ wire _net_181;\r
+ wire _net_182;\r
+ wire _net_183;\r
+ wire _net_184;\r
+ wire _net_185;\r
+ wire _net_186;\r
+ wire _net_187;\r
+ wire _net_188;\r
+ wire _net_189;\r
+ wire _net_190;\r
+ wire _net_191;\r
+ wire _net_192;\r
+ wire _net_193;\r
+ wire _net_194;\r
+ wire _net_195;\r
+ wire _net_196;\r
+ wire _net_197;\r
+ wire _net_198;\r
+ wire _net_199;\r
+ wire _net_200;\r
+ wire _net_201;\r
+ wire _net_202;\r
+ wire _net_203;\r
+ wire _net_204;\r
+ wire _net_205;\r
+ wire _net_206;\r
+ wire _net_207;\r
+ wire _net_208;\r
+ wire _net_209;\r
+ wire _net_210;\r
+ wire _net_211;\r
+ wire _net_212;\r
+ wire _net_213;\r
+ wire _net_214;\r
+ wire _net_215;\r
+ wire _net_216;\r
+ wire _net_217;\r
+ wire _net_218;\r
+\r
+ assign disp_data = _net_10;\r
+ assign red = 4'b0000;\r
+ assign green = 4'b0000;\r
+ assign blue = ((_net_20)?4'b0000:4'b0)|\r
+ ((_net_18)?4'b1111:4'b0);\r
+ assign sel_disp_data = ((_net_218)?r2[31]:1'b0)|\r
+ ((_net_215)?r2[30]:1'b0)|\r
+ ((_net_212)?r2[29]:1'b0)|\r
+ ((_net_209)?r2[28]:1'b0)|\r
+ ((_net_206)?r2[27]:1'b0)|\r
+ ((_net_203)?r2[26]:1'b0)|\r
+ ((_net_200)?r2[25]:1'b0)|\r
+ ((_net_197)?r2[24]:1'b0)|\r
+ ((_net_194)?r2[23]:1'b0)|\r
+ ((_net_191)?r2[22]:1'b0)|\r
+ ((_net_188)?r2[21]:1'b0)|\r
+ ((_net_185)?r2[20]:1'b0)|\r
+ ((_net_182)?r2[19]:1'b0)|\r
+ ((_net_179)?r2[18]:1'b0)|\r
+ ((_net_176)?r2[17]:1'b0)|\r
+ ((_net_173)?r2[16]:1'b0)|\r
+ ((_net_170)?r2[15]:1'b0)|\r
+ ((_net_167)?r2[14]:1'b0)|\r
+ ((_net_164)?r2[13]:1'b0)|\r
+ ((_net_161)?r2[12]:1'b0)|\r
+ ((_net_158)?r2[11]:1'b0)|\r
+ ((_net_155)?r2[10]:1'b0)|\r
+ ((_net_152)?r2[9]:1'b0)|\r
+ ((_net_149)?r2[8]:1'b0)|\r
+ ((_net_146)?r2[7]:1'b0)|\r
+ ((_net_143)?r2[6]:1'b0)|\r
+ ((_net_140)?r2[5]:1'b0)|\r
+ ((_net_137)?r2[4]:1'b0)|\r
+ ((_net_134)?r2[3]:1'b0)|\r
+ ((_net_131)?r2[2]:1'b0)|\r
+ ((_net_128)?r2[1]:1'b0)|\r
+ ((_net_124)?r2[0]:1'b0)|\r
+ ((_net_121)?r1[31]:1'b0)|\r
+ ((_net_118)?r1[30]:1'b0)|\r
+ ((_net_115)?r1[29]:1'b0)|\r
+ ((_net_112)?r1[28]:1'b0)|\r
+ ((_net_109)?r1[27]:1'b0)|\r
+ ((_net_106)?r1[26]:1'b0)|\r
+ ((_net_103)?r1[25]:1'b0)|\r
+ ((_net_100)?r1[24]:1'b0)|\r
+ ((_net_97)?r1[23]:1'b0)|\r
+ ((_net_94)?r1[22]:1'b0)|\r
+ ((_net_91)?r1[21]:1'b0)|\r
+ ((_net_88)?r1[20]:1'b0)|\r
+ ((_net_85)?r1[19]:1'b0)|\r
+ ((_net_82)?r1[18]:1'b0)|\r
+ ((_net_79)?r1[17]:1'b0)|\r
+ ((_net_76)?r1[16]:1'b0)|\r
+ ((_net_73)?r1[15]:1'b0)|\r
+ ((_net_70)?r1[14]:1'b0)|\r
+ ((_net_67)?r1[13]:1'b0)|\r
+ ((_net_64)?r1[12]:1'b0)|\r
+ ((_net_61)?r1[11]:1'b0)|\r
+ ((_net_58)?r1[10]:1'b0)|\r
+ ((_net_55)?r1[9]:1'b0)|\r
+ ((_net_52)?r1[8]:1'b0)|\r
+ ((_net_49)?r1[7]:1'b0)|\r
+ ((_net_46)?r1[6]:1'b0)|\r
+ ((_net_43)?r1[5]:1'b0)|\r
+ ((_net_40)?r1[4]:1'b0)|\r
+ ((_net_37)?r1[3]:1'b0)|\r
+ ((_net_34)?r1[2]:1'b0)|\r
+ ((_net_31)?r1[1]:1'b0)|\r
+ ((_net_27)?r1[0]:1'b0);\r
+ assign _net_0 = (h_cnt)==(10'b1100100000);\r
+ assign _net_1 = (h_cnt)==(10'b1100001110);\r
+ assign _net_2 = (h_cnt)==(10'b0010001110);\r
+ assign _net_3 = (h_cnt)==(10'b0001100000);\r
+ assign _net_4 = (((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3);\r
+ assign _net_5 = (v_cnt)==(19'b1100101110000011111);\r
+ assign _net_6 = (v_cnt)==(19'b1100011110011011111);\r
+ assign _net_7 = (v_cnt)==(19'b0000110000011011111);\r
+ assign _net_8 = (v_cnt)==(19'b0000000011000111111);\r
+ assign _net_9 = (((~_net_5)&(~_net_6))&(~_net_7))&(~_net_8);\r
+ assign _net_10 = hdata_flg&vdata_flg;\r
+ assign _net_11 = (((h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111)));\r
+ assign _net_12 = (bit32_cnt)==(5'b00000);\r
+ assign _net_13 = _net_11&_net_12;\r
+ assign _net_14 = (bit32_cnt)==(5'b11111);\r
+ assign _net_15 = _net_11&_net_14;\r
+ assign _net_16 = _net_11&(~_net_14);\r
+ assign _net_17 = ~_net_11;\r
+ assign _net_18 = hdata_flg&vdata_flg;\r
+ assign _net_19 = ~_net_18;\r
+ assign _net_20 = ~_net_18;\r
+ assign _net_21 = ~_net_18;\r
+ assign _net_22 = ack_req_32dot&data_select_flag;\r
+ assign _net_23 = ack_req_32dot&(~data_select_flag);\r
+ assign _net_24 = ~reg_flg;\r
+ assign _net_25 = (bit32_cnt)==(5'b11111);\r
+ assign _net_26 = disp_data&_net_24;\r
+ assign _net_27 = (disp_data&_net_24)&_net_25;\r
+ assign _net_28 = (disp_data&_net_24)&_net_25;\r
+ assign _net_29 = (bit32_cnt)==(5'b11110);\r
+ assign _net_30 = disp_data&_net_24;\r
+ assign _net_31 = (disp_data&_net_24)&_net_29;\r
+ assign _net_32 = (bit32_cnt)==(5'b11101);\r
+ assign _net_33 = disp_data&_net_24;\r
+ assign _net_34 = (disp_data&_net_24)&_net_32;\r
+ assign _net_35 = (bit32_cnt)==(5'b11100);\r
+ assign _net_36 = disp_data&_net_24;\r
+ assign _net_37 = (disp_data&_net_24)&_net_35;\r
+ assign _net_38 = (bit32_cnt)==(5'b11011);\r
+ assign _net_39 = disp_data&_net_24;\r
+ assign _net_40 = (disp_data&_net_24)&_net_38;\r
+ assign _net_41 = (bit32_cnt)==(5'b11010);\r
+ assign _net_42 = disp_data&_net_24;\r
+ assign _net_43 = (disp_data&_net_24)&_net_41;\r
+ assign _net_44 = (bit32_cnt)==(5'b11001);\r
+ assign _net_45 = disp_data&_net_24;\r
+ assign _net_46 = (disp_data&_net_24)&_net_44;\r
+ assign _net_47 = (bit32_cnt)==(5'b11000);\r
+ assign _net_48 = disp_data&_net_24;\r
+ assign _net_49 = (disp_data&_net_24)&_net_47;\r
+ assign _net_50 = (bit32_cnt)==(5'b10111);\r
+ assign _net_51 = disp_data&_net_24;\r
+ assign _net_52 = (disp_data&_net_24)&_net_50;\r
+ assign _net_53 = (bit32_cnt)==(5'b10110);\r
+ assign _net_54 = disp_data&_net_24;\r
+ assign _net_55 = (disp_data&_net_24)&_net_53;\r
+ assign _net_56 = (bit32_cnt)==(5'b10101);\r
+ assign _net_57 = disp_data&_net_24;\r
+ assign _net_58 = (disp_data&_net_24)&_net_56;\r
+ assign _net_59 = (bit32_cnt)==(5'b10100);\r
+ assign _net_60 = disp_data&_net_24;\r
+ assign _net_61 = (disp_data&_net_24)&_net_59;\r
+ assign _net_62 = (bit32_cnt)==(5'b10011);\r
+ assign _net_63 = disp_data&_net_24;\r
+ assign _net_64 = (disp_data&_net_24)&_net_62;\r
+ assign _net_65 = (bit32_cnt)==(5'b10010);\r
+ assign _net_66 = disp_data&_net_24;\r
+ assign _net_67 = (disp_data&_net_24)&_net_65;\r
+ assign _net_68 = (bit32_cnt)==(5'b10001);\r
+ assign _net_69 = disp_data&_net_24;\r
+ assign _net_70 = (disp_data&_net_24)&_net_68;\r
+ assign _net_71 = (bit32_cnt)==(5'b10000);\r
+ assign _net_72 = disp_data&_net_24;\r
+ assign _net_73 = (disp_data&_net_24)&_net_71;\r
+ assign _net_74 = (bit32_cnt)==(5'b01111);\r
+ assign _net_75 = disp_data&_net_24;\r
+ assign _net_76 = (disp_data&_net_24)&_net_74;\r
+ assign _net_77 = (bit32_cnt)==(5'b01110);\r
+ assign _net_78 = disp_data&_net_24;\r
+ assign _net_79 = (disp_data&_net_24)&_net_77;\r
+ assign _net_80 = (bit32_cnt)==(5'b01101);\r
+ assign _net_81 = disp_data&_net_24;\r
+ assign _net_82 = (disp_data&_net_24)&_net_80;\r
+ assign _net_83 = (bit32_cnt)==(5'b01100);\r
+ assign _net_84 = disp_data&_net_24;\r
+ assign _net_85 = (disp_data&_net_24)&_net_83;\r
+ assign _net_86 = (bit32_cnt)==(5'b01011);\r
+ assign _net_87 = disp_data&_net_24;\r
+ assign _net_88 = (disp_data&_net_24)&_net_86;\r
+ assign _net_89 = (bit32_cnt)==(5'b01010);\r
+ assign _net_90 = disp_data&_net_24;\r
+ assign _net_91 = (disp_data&_net_24)&_net_89;\r
+ assign _net_92 = (bit32_cnt)==(5'b01001);\r
+ assign _net_93 = disp_data&_net_24;\r
+ assign _net_94 = (disp_data&_net_24)&_net_92;\r
+ assign _net_95 = (bit32_cnt)==(5'b01000);\r
+ assign _net_96 = disp_data&_net_24;\r
+ assign _net_97 = (disp_data&_net_24)&_net_95;\r
+ assign _net_98 = (bit32_cnt)==(5'b00111);\r
+ assign _net_99 = disp_data&_net_24;\r
+ assign _net_100 = (disp_data&_net_24)&_net_98;\r
+ assign _net_101 = (bit32_cnt)==(5'b00110);\r
+ assign _net_102 = disp_data&_net_24;\r
+ assign _net_103 = (disp_data&_net_24)&_net_101;\r
+ assign _net_104 = (bit32_cnt)==(5'b00101);\r
+ assign _net_105 = disp_data&_net_24;\r
+ assign _net_106 = (disp_data&_net_24)&_net_104;\r
+ assign _net_107 = (bit32_cnt)==(5'b00100);\r
+ assign _net_108 = disp_data&_net_24;\r
+ assign _net_109 = (disp_data&_net_24)&_net_107;\r
+ assign _net_110 = (bit32_cnt)==(5'b00011);\r
+ assign _net_111 = disp_data&_net_24;\r
+ assign _net_112 = (disp_data&_net_24)&_net_110;\r
+ assign _net_113 = (bit32_cnt)==(5'b00010);\r
+ assign _net_114 = disp_data&_net_24;\r
+ assign _net_115 = (disp_data&_net_24)&_net_113;\r
+ assign _net_116 = (bit32_cnt)==(5'b00001);\r
+ assign _net_117 = disp_data&_net_24;\r
+ assign _net_118 = (disp_data&_net_24)&_net_116;\r
+ assign _net_119 = (bit32_cnt)==(5'b00000);\r
+ assign _net_120 = disp_data&_net_24;\r
+ assign _net_121 = (disp_data&_net_24)&_net_119;\r
+ assign _net_122 = (bit32_cnt)==(5'b11111);\r
+ assign _net_123 = disp_data&(~_net_24);\r
+ assign _net_124 = (disp_data&(~_net_24))&_net_122;\r
+ assign _net_125 = (disp_data&(~_net_24))&_net_122;\r
+ assign _net_126 = (bit32_cnt)==(5'b11110);\r
+ assign _net_127 = disp_data&(~_net_24);\r
+ assign _net_128 = (disp_data&(~_net_24))&_net_126;\r
+ assign _net_129 = (bit32_cnt)==(5'b11101);\r
+ assign _net_130 = disp_data&(~_net_24);\r
+ assign _net_131 = (disp_data&(~_net_24))&_net_129;\r
+ assign _net_132 = (bit32_cnt)==(5'b11100);\r
+ assign _net_133 = disp_data&(~_net_24);\r
+ assign _net_134 = (disp_data&(~_net_24))&_net_132;\r
+ assign _net_135 = (bit32_cnt)==(5'b11011);\r
+ assign _net_136 = disp_data&(~_net_24);\r
+ assign _net_137 = (disp_data&(~_net_24))&_net_135;\r
+ assign _net_138 = (bit32_cnt)==(5'b11010);\r
+ assign _net_139 = disp_data&(~_net_24);\r
+ assign _net_140 = (disp_data&(~_net_24))&_net_138;\r
+ assign _net_141 = (bit32_cnt)==(5'b11001);\r
+ assign _net_142 = disp_data&(~_net_24);\r
+ assign _net_143 = (disp_data&(~_net_24))&_net_141;\r
+ assign _net_144 = (bit32_cnt)==(5'b11000);\r
+ assign _net_145 = disp_data&(~_net_24);\r
+ assign _net_146 = (disp_data&(~_net_24))&_net_144;\r
+ assign _net_147 = (bit32_cnt)==(5'b10111);\r
+ assign _net_148 = disp_data&(~_net_24);\r
+ assign _net_149 = (disp_data&(~_net_24))&_net_147;\r
+ assign _net_150 = (bit32_cnt)==(5'b10110);\r
+ assign _net_151 = disp_data&(~_net_24);\r
+ assign _net_152 = (disp_data&(~_net_24))&_net_150;\r
+ assign _net_153 = (bit32_cnt)==(5'b10101);\r
+ assign _net_154 = disp_data&(~_net_24);\r
+ assign _net_155 = (disp_data&(~_net_24))&_net_153;\r
+ assign _net_156 = (bit32_cnt)==(5'b10100);\r
+ assign _net_157 = disp_data&(~_net_24);\r
+ assign _net_158 = (disp_data&(~_net_24))&_net_156;\r
+ assign _net_159 = (bit32_cnt)==(5'b10011);\r
+ assign _net_160 = disp_data&(~_net_24);\r
+ assign _net_161 = (disp_data&(~_net_24))&_net_159;\r
+ assign _net_162 = (bit32_cnt)==(5'b10010);\r
+ assign _net_163 = disp_data&(~_net_24);\r
+ assign _net_164 = (disp_data&(~_net_24))&_net_162;\r
+ assign _net_165 = (bit32_cnt)==(5'b10001);\r
+ assign _net_166 = disp_data&(~_net_24);\r
+ assign _net_167 = (disp_data&(~_net_24))&_net_165;\r
+ assign _net_168 = (bit32_cnt)==(5'b10000);\r
+ assign _net_169 = disp_data&(~_net_24);\r
+ assign _net_170 = (disp_data&(~_net_24))&_net_168;\r
+ assign _net_171 = (bit32_cnt)==(5'b01111);\r
+ assign _net_172 = disp_data&(~_net_24);\r
+ assign _net_173 = (disp_data&(~_net_24))&_net_171;\r
+ assign _net_174 = (bit32_cnt)==(5'b01110);\r
+ assign _net_175 = disp_data&(~_net_24);\r
+ assign _net_176 = (disp_data&(~_net_24))&_net_174;\r
+ assign _net_177 = (bit32_cnt)==(5'b01101);\r
+ assign _net_178 = disp_data&(~_net_24);\r
+ assign _net_179 = (disp_data&(~_net_24))&_net_177;\r
+ assign _net_180 = (bit32_cnt)==(5'b01100);\r
+ assign _net_181 = disp_data&(~_net_24);\r
+ assign _net_182 = (disp_data&(~_net_24))&_net_180;\r
+ assign _net_183 = (bit32_cnt)==(5'b01011);\r
+ assign _net_184 = disp_data&(~_net_24);\r
+ assign _net_185 = (disp_data&(~_net_24))&_net_183;\r
+ assign _net_186 = (bit32_cnt)==(5'b01010);\r
+ assign _net_187 = disp_data&(~_net_24);\r
+ assign _net_188 = (disp_data&(~_net_24))&_net_186;\r
+ assign _net_189 = (bit32_cnt)==(5'b01001);\r
+ assign _net_190 = disp_data&(~_net_24);\r
+ assign _net_191 = (disp_data&(~_net_24))&_net_189;\r
+ assign _net_192 = (bit32_cnt)==(5'b01000);\r
+ assign _net_193 = disp_data&(~_net_24);\r
+ assign _net_194 = (disp_data&(~_net_24))&_net_192;\r
+ assign _net_195 = (bit32_cnt)==(5'b00111);\r
+ assign _net_196 = disp_data&(~_net_24);\r
+ assign _net_197 = (disp_data&(~_net_24))&_net_195;\r
+ assign _net_198 = (bit32_cnt)==(5'b00110);\r
+ assign _net_199 = disp_data&(~_net_24);\r
+ assign _net_200 = (disp_data&(~_net_24))&_net_198;\r
+ assign _net_201 = (bit32_cnt)==(5'b00101);\r
+ assign _net_202 = disp_data&(~_net_24);\r
+ assign _net_203 = (disp_data&(~_net_24))&_net_201;\r
+ assign _net_204 = (bit32_cnt)==(5'b00100);\r
+ assign _net_205 = disp_data&(~_net_24);\r
+ assign _net_206 = (disp_data&(~_net_24))&_net_204;\r
+ assign _net_207 = (bit32_cnt)==(5'b00011);\r
+ assign _net_208 = disp_data&(~_net_24);\r
+ assign _net_209 = (disp_data&(~_net_24))&_net_207;\r
+ assign _net_210 = (bit32_cnt)==(5'b00010);\r
+ assign _net_211 = disp_data&(~_net_24);\r
+ assign _net_212 = (disp_data&(~_net_24))&_net_210;\r
+ assign _net_213 = (bit32_cnt)==(5'b00001);\r
+ assign _net_214 = disp_data&(~_net_24);\r
+ assign _net_215 = (disp_data&(~_net_24))&_net_213;\r
+ assign _net_216 = (bit32_cnt)==(5'b00000);\r
+ assign _net_217 = disp_data&(~_net_24);\r
+ assign _net_218 = (disp_data&(~_net_24))&_net_216;\r
+ assign v_sync_o = v_sync;\r
+ assign h_sync_o = h_sync;\r
+ assign vga_red_o = red;\r
+ assign vga_green_o = green;\r
+ assign vga_blue_o = blue;\r
+ assign h_cnt_o = h_cnt;\r
+ assign req_32dot = _net_13;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ v_sync <= 1'b0;\r
+else if ((_net_8|_net_5)) \r
+ v_sync <= ~v_sync;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ h_sync <= 1'b0;\r
+else if ((_net_3|_net_0)) \r
+ h_sync <= ~h_sync;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ h_flg <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ vdata_flg <= 1'b0;\r
+else if ((_net_7)|(_net_6)) \r
+ vdata_flg <= ((_net_7) ?1'b1:1'b0)|\r
+ ((_net_6) ?1'b0:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ hdata_flg <= 1'b0;\r
+else if ((_net_2)|(_net_1)) \r
+ hdata_flg <= ((_net_2) ?1'b1:1'b0)|\r
+ ((_net_1) ?1'b0:1'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ h_cnt <= 10'b0000000000;\r
+else if ((_net_4|_net_3|_net_2|_net_1)|(_net_0)) \r
+ h_cnt <= ((_net_4|_net_3|_net_2|_net_1) ?(h_cnt)+(10'b0000000001):10'b0)|\r
+ ((_net_0) ?10'b0000000000:10'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ v_cnt <= 19'b0000000000000000000;\r
+else if ((_net_9|_net_8|_net_7|_net_6)|(_net_5)) \r
+ v_cnt <= ((_net_9|_net_8|_net_7|_net_6) ?(v_cnt)+(19'b0000000000000000001):19'b0)|\r
+ ((_net_5) ?19'b0000000000000000000:19'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ bit32_cnt <= 5'b00000;\r
+else if ((disp_data)|(_net_16)|(_net_17|_net_15)) \r
+ bit32_cnt <= ((disp_data) ?(bit32_cnt)+(5'b00001):5'b0)|\r
+ ((_net_16) ?(bit32_cnt)+(5'b00001):5'b0)|\r
+ ((_net_17|_net_15) ?5'b00000:5'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ reg_flg <= 1'b0;\r
+else if ((_net_125|_net_28)) \r
+ reg_flg <= ~reg_flg;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ reg_cnt <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r1 <= 32'b00000000000000000000000000000000;\r
+else if ((_net_22)) \r
+ r1 <= pix32_data_i;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r2 <= 32'b00000000000000000000000000000000;\r
+else if ((_net_23)) \r
+ r2 <= pix32_data_i;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ data_select_flag <= 1'b0;\r
+else if ((ack_req_32dot)) \r
+ data_select_flag <= ~data_select_flag;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:36 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
+\r
+module vga_top ( p_reset , m_clock , o_v_sync , o_h_sync , o_red , o_green , o_blue , o_LED );\r
+ input p_reset, m_clock;\r
+ output o_v_sync;\r
+ output o_h_sync;\r
+ output [3:0] o_red;\r
+ output [3:0] o_green;\r
+ output [3:0] o_blue;\r
+ output [7:0] o_LED;\r
+ reg r_cnt;\r
+ reg [2:0] r_reset;\r
+ reg [14:0] r_line_cnt;\r
+ reg [13:0] r_line_cnt2;\r
+ reg [13:0] r_vram_adrs_cnt;\r
+ reg [24:0] r_Sec_cnt;\r
+ reg r_Init_flag;\r
+ reg [7:0] r_LED;\r
+ reg r_test_LED;\r
+ reg [7:0] line_buff1 [0:79];\r
+ reg [7:0] line_buff2 [0:79];\r
+ wire fs_vga_sys_init;\r
+ wire [14:0] _net_221;\r
+ wire _u_VGA_p_reset;\r
+ wire _u_VGA_m_clock;\r
+ wire [31:0] _u_VGA_pix32_data_i;\r
+ wire _u_VGA_v_sync_o;\r
+ wire _u_VGA_h_sync_o;\r
+ wire [3:0] _u_VGA_vga_red_o;\r
+ wire [3:0] _u_VGA_vga_green_o;\r
+ wire [3:0] _u_VGA_vga_blue_o;\r
+ wire [9:0] _u_VGA_h_cnt_o;\r
+ wire _u_VGA_ack_req_32dot;\r
+ wire _u_VGA_req_32dot;\r
+ wire [13:0] _U_EXP_iRadrs;\r
+ wire [15:0] _U_EXP_oRdata;\r
+ wire _U_EXP_fiRd_req;\r
+ wire _U_EXP_foRd_ack;\r
+ wire [7:0] _U_EXP_iWdata;\r
+ wire [13:0] _U_EXP_iWadrs;\r
+ wire _U_EXP_fiWr_req;\r
+ wire _U_EXP_p_reset;\r
+ wire _U_EXP_m_clock;\r
+ wire _net_222;\r
+ wire _net_223;\r
+ wire _net_224;\r
+ wire _net_225;\r
+ wire _net_226;\r
+ wire _net_227;\r
+ wire _net_228;\r
+ wire _net_229;\r
+ wire _net_230;\r
+ wire _net_231;\r
+ wire _net_232;\r
+ wire _net_233;\r
+ reg _reg_234;\r
+ reg _reg_235;\r
+ reg _reg_236;\r
+ reg _reg_237;\r
+ wire _net_238;\r
+ wire _reg_235_goto;\r
+ wire _net_239;\r
+ wire _reg_236_goin;\r
+ wire _net_240;\r
+ wire _net_241;\r
+ wire _reg_236_goto;\r
+ wire _net_242;\r
+ wire _reg_234_goin;\r
+ wire _net_243;\r
+ wire _net_244;\r
+ wire _net_245;\r
+ wire _net_246;\r
+ wire _net_247;\r
+ wire _net_248;\r
+ wire _net_249;\r
+ wire _net_250;\r
+exp_ctrl U_EXP (.p_reset(p_reset), .m_clock(m_clock), .fiWr_req(_U_EXP_fiWr_req), .iWadrs(_U_EXP_iWadrs), .iWdata(_U_EXP_iWdata), .foRd_ack(_U_EXP_foRd_ack), .fiRd_req(_U_EXP_fiRd_req), .oRdata(_U_EXP_oRdata), .iRadrs(_U_EXP_iRadrs));\r
+vga_generate u_VGA (.req_32dot(_u_VGA_req_32dot), .ack_req_32dot(_u_VGA_ack_req_32dot), .h_cnt_o(_u_VGA_h_cnt_o), .vga_blue_o(_u_VGA_vga_blue_o), .vga_green_o(_u_VGA_vga_green_o), .vga_red_o(_u_VGA_vga_red_o), .h_sync_o(_u_VGA_h_sync_o), .v_sync_o(_u_VGA_v_sync_o), .pix32_data_i(_u_VGA_pix32_data_i), .m_clock(_u_VGA_m_clock), .p_reset(_u_VGA_p_reset));\r
+\r
+ assign fs_vga_sys_init = _net_222;\r
+ assign _net_221 = (r_line_cnt)+(15'b000000000000001);\r
+ assign _u_VGA_p_reset = r_reset[2];\r
+ assign _u_VGA_m_clock = r_cnt;\r
+ assign _u_VGA_pix32_data_i = 32'b11111111111111111111111111111111;\r
+ assign _u_VGA_ack_req_32dot = _u_VGA_req_32dot;\r
+ assign _U_EXP_iRadrs = r_line_cnt2;\r
+ assign _U_EXP_fiRd_req = _net_224;\r
+ assign _U_EXP_iWdata = 8'b11110000;\r
+ assign _U_EXP_iWadrs = r_line_cnt[13:0];\r
+ assign _U_EXP_fiWr_req = _net_244;\r
+ assign _net_222 = (r_reset)==(3'b100);\r
+ assign _net_223 = (r_Sec_cnt)==(25'b0111110101111000010000000);\r
+ assign _net_224 = r_Init_flag&_net_223;\r
+ assign _net_225 = r_Init_flag&_net_223;\r
+ assign _net_226 = r_Init_flag&_net_223;\r
+ assign _net_227 = r_Init_flag&_net_223;\r
+ assign _net_228 = (r_line_cnt2)==(14'b00001111101000);\r
+ assign _net_229 = r_Init_flag&_net_223;\r
+ assign _net_230 = (r_Init_flag&_net_223)&_net_228;\r
+ assign _net_231 = (r_Init_flag&_net_223)&(~_net_228);\r
+ assign _net_232 = r_Init_flag&(~_net_223);\r
+ assign _net_233 = ~r_Init_flag;\r
+ assign _net_238 = (_net_221) < (15'b100000000000000);\r
+ assign _reg_235_goto = _net_239;\r
+ assign _net_239 = _reg_235&_net_238;\r
+ assign _reg_236_goin = _net_240;\r
+ assign _net_240 = _reg_235&_net_238;\r
+ assign _net_241 = ~((r_line_cnt) < (15'b100000000000000));\r
+ assign _reg_236_goto = _net_242;\r
+ assign _net_242 = _reg_236&_net_241;\r
+ assign _reg_234_goin = _net_243;\r
+ assign _net_243 = _reg_236&_net_241;\r
+ assign _net_244 = _reg_236&(~_net_241);\r
+ assign _net_245 = _reg_236&(~_net_241);\r
+ assign _net_246 = _reg_236&(~_net_241);\r
+ assign _net_247 = fs_vga_sys_init|_reg_237;\r
+ assign _net_248 = (_reg_236_goin|fs_vga_sys_init)|_reg_236|_reg_237;\r
+ assign _net_249 = (_reg_236_goin|fs_vga_sys_init)|_reg_235|_reg_236;\r
+ assign _net_250 = _reg_234_goin|_reg_234|_reg_235;\r
+ assign o_v_sync = _u_VGA_v_sync_o;\r
+ assign o_h_sync = _u_VGA_h_sync_o;\r
+ assign o_red = _u_VGA_vga_red_o;\r
+ assign o_green = _u_VGA_vga_green_o;\r
+ assign o_blue = _u_VGA_vga_blue_o;\r
+ assign o_LED = r_LED;\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt <= 1'b0;\r
+else r_cnt <= ~r_cnt;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_reset <= 3'b111;\r
+else r_reset <= {r_reset[1:0],1'b0};\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_line_cnt <= 15'b000000000000000;\r
+else if ((_net_247)|(_reg_235)) \r
+ r_line_cnt <= ((_net_247) ?15'b000000000000000:15'b0)|\r
+ ((_reg_235) ?_net_221:15'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_line_cnt2 <= 14'b00000000000000;\r
+else if ((_net_231)|(_net_230)) \r
+ r_line_cnt2 <= ((_net_231) ?(r_line_cnt2)+(14'b00000000000001):14'b0)|\r
+ ((_net_230) ?14'b00000000000000:14'b0);\r
+\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_vram_adrs_cnt <= 14'b00000000000000;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_Sec_cnt <= 25'b0000000000000000000000000;\r
+else if ((_net_232)|(_net_233|_net_226)) \r
+ r_Sec_cnt <= ((_net_232) ?(r_Sec_cnt)+(25'b0000000000000000000000001):25'b0)|\r
+ ((_net_233|_net_226) ?25'b0000000000000000000000000:25'b0);\r
+\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_Init_flag <= 1'b0;\r
+else if ((_reg_234)) \r
+ r_Init_flag <= 1'b1;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_LED <= 8'b00000000;\r
+else if ((_U_EXP_foRd_ack)) \r
+ r_LED <= {_U_EXP_oRdata[10],_U_EXP_oRdata[8],_U_EXP_oRdata[6],_U_EXP_oRdata[4],_U_EXP_oRdata[2],_U_EXP_oRdata[0],r_test_LED,r_Init_flag};\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_test_LED <= 1'b0;\r
+else if ((_net_227)) \r
+ r_test_LED <= ~r_test_LED;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_234 <= 1'b0;\r
+else if ((_net_250)) \r
+ _reg_234 <= _reg_234_goin|(_reg_235&(~_reg_235_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_235 <= 1'b0;\r
+else if ((_net_249)) \r
+ _reg_235 <= _reg_236&(~_reg_236_goto);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_236 <= 1'b0;\r
+else if ((_net_248)) \r
+ _reg_236 <= (_reg_236_goin|_reg_237)|fs_vga_sys_init;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_237 <= 1'b0;\r
+else if ((_reg_237)) \r
+ _reg_237 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:06:37 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:26 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module vram ( clock , data , rdaddress , wraddress , wren , q );\r
+ input clock;\r
+ input [7:0] data;\r
+ input [13:0] rdaddress;\r
+ input [13:0] wraddress;\r
+ input wren;\r
+ input rden;\r
+ output [7:0] q;\r
+ reg [7:0] m_vram [0:16383];\r
+ reg [7:0] r_ram_data;\r
+\r
+ assign q = r_ram_data;\r
+always @(posedge m_clock)\r
+ begin\r
+ if (wren)\r
+ m_vram[wraddress] <= data;\r
+end\r
+\r
+always @(posedge m_clock)\r
+begin\r
+ if (rden)\r
+ r_ram_data <= m_vram[rdaddress];\r
+end\r
+\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:26 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:20 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+*/\r
+\r
+module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack );\r
+ input p_reset, m_clock;\r
+ input [7:0] i_Wdata;\r
+ input [13:0] i_Wadrs;\r
+ input [13:0] i_Radrs;\r
+ output [7:0] o_Rdata;\r
+ input fi_Wr_req;\r
+ input fi_Rd_req;\r
+ output fo_Rd_ack;\r
+ reg [13:0] r_Radrs_hld;\r
+ wire _u_VRAM_clk;\r
+ wire [7:0] _u_VRAM_d;\r
+ wire [13:0] _u_VRAM_ra;\r
+ wire [13:0] _u_VRAM_wa;\r
+ wire _u_VRAM_we;\r
+ wire [7:0] _u_VRAM_q;\r
+ wire _u_VRAM_p_reset;\r
+ wire _u_VRAM_m_clock;\r
+ wire _net_0;\r
+ reg _reg_1;\r
+ reg _reg_2;\r
+ wire _net_3;\r
+ wire _net_4;\r
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk));\r
+\r
+ assign _u_VRAM_d = i_Wdata;\r
+ assign _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)|\r
+ ((_reg_1)?r_Radrs_hld:14'b0);\r
+ assign _u_VRAM_wa = i_Wadrs;\r
+ assign _u_VRAM_we = fi_Wr_req|\r
+ ((_net_0)?1'b0:1'b0);\r
+ assign _net_0 = ~fi_Wr_req;\r
+ assign _net_3 = fi_Rd_req|_reg_2;\r
+ assign _net_4 = fi_Rd_req|_reg_1|_reg_2;\r
+ assign o_Rdata = _u_VRAM_q;\r
+ assign fo_Rd_ack = _reg_1;\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_Radrs_hld <= 14'b00000000000000;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_1 <= 1'b0;\r
+else if ((_net_4)) \r
+ _reg_1 <= _reg_2|fi_Rd_req;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_2 <= 1'b0;\r
+else if ((_reg_2)) \r
+ _reg_2 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jul 07 21:02:22 2011\r
+ Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+*/\r
--- /dev/null
+declare exp_ctrl {
+ input iRadrs[14] ;
+ output oRdata[16] ;
+ func_in fiRd_req( iRadrs ) ;
+ func_out foRd_ack( oRdata ) ;
+
+ input iWdata[8] ;
+ input iWadrs[14] ;
+ func_in fiWr_req( iWadrs, iWdata ) ;
+}
#include "vram_ctrl.nsl"
declare exp_ctrl {
- input iRadrs[14] ;
- output oRdata[16] ;
- func_in fiRd_req( iRadrs ) ;
- func_out foRd_ack( oRdata ) ;
+ input i_Radrs[14] ;
+ output o_Rdata[16] ;
+ func_in fi_Rd_req( i_Radrs ) ;
+ func_out fo_Rd_ack( o_Rdata ) ;
- input iWdata[8] ;
- input iWadrs[14] ;
- func_in fiWr_req( iWadrs, iWdata ) ;
+ input i_Wdata[8] ;
+ input i_Wadrs[14] ;
+ func_in fi_Wr_req( i_Wadrs, i_Wdata ) ;
}
module exp_ctrl {
- wire exp_q[16] ;
- vram_ctrl U_VRAMC ;
-
- U_VRAMC.p_reset = 0b0 ;
-
- exp_q = {
- U_VRAMC.oRdata[7], U_VRAMC.oRdata[7],
- U_VRAMC.oRdata[6], U_VRAMC.oRdata[6],
- U_VRAMC.oRdata[5], U_VRAMC.oRdata[5],
- U_VRAMC.oRdata[4], U_VRAMC.oRdata[4],
- U_VRAMC.oRdata[3], U_VRAMC.oRdata[3],
- U_VRAMC.oRdata[2], U_VRAMC.oRdata[2],
- U_VRAMC.oRdata[1], U_VRAMC.oRdata[1],
- U_VRAMC.oRdata[0], U_VRAMC.oRdata[0]
+ wire w_exp_q[16] ;
+ vram_ctrl u_VRAMC ;
+
+ w_exp_q = {
+ u_VRAMC.o_Rdata[7], u_VRAMC.o_Rdata[7],
+ u_VRAMC.o_Rdata[6], u_VRAMC.o_Rdata[6],
+ u_VRAMC.o_Rdata[5], u_VRAMC.o_Rdata[5],
+ u_VRAMC.o_Rdata[4], u_VRAMC.o_Rdata[4],
+ u_VRAMC.o_Rdata[3], u_VRAMC.o_Rdata[3],
+ u_VRAMC.o_Rdata[2], u_VRAMC.o_Rdata[2],
+ u_VRAMC.o_Rdata[1], u_VRAMC.o_Rdata[1],
+ u_VRAMC.o_Rdata[0], u_VRAMC.o_Rdata[0]
} ;
- if( U_VRAMC.foRd_ack ) foRd_ack( exp_q ) ;
+ if( u_VRAMC.fo_Rd_ack ) fo_Rd_ack( w_exp_q ) ;
- func fiRd_req seq {
- U_VRAMC.fiRd_req( iRadrs ) ;
+ func fi_Rd_req seq {
+ u_VRAMC.fi_Rd_req( i_Radrs ) ;
}
- func fiWr_req {
- U_VRAMC.fiWr_req( iWadrs, iWdata ) ;
+ func fi_Wr_req {
+ u_VRAMC.fi_Wr_req( i_Wadrs, i_Wdata ) ;
}
}
\ No newline at end of file
+/**\r
+* VGA top module\r
+* module name is "vga_top"\r
+* @author zyanham\r
+* @version 1.0\r
+* comment : \r
+*/\r
+\r
#define SIM\r
\r
#include "vga_generate.nsl"\r
\r
\r
declare vga_top {\r
- output v_sync_o ;\r
- output h_sync_o ;\r
- output vga_red_o[4] ;\r
- output vga_green_o[4] ;\r
- output vga_blue_o[4] ;\r
+ output o_v_sync ;\r
+ output o_h_sync ;\r
+ output o_red[4] ;\r
+ output o_green[4] ;\r
+ output o_blue[4] ;\r
\r
- output oLED[8] ;\r
+ output o_LED[8] ;\r
}\r
module vga_top {\r
integer i ;\r
\r
- reg cnt = 0 ;\r
- reg reset[3] = 0b111 ;\r
- reg line_cnt[15] = 0 ;\r
- reg line_cnt2[14] = 0 ;\r
+ reg r_cnt = 0 ;\r
+ reg r_reset[3] = 0b111 ;\r
+ reg r_line_cnt[15] = 0 ;\r
+ reg r_line_cnt2[14] = 0 ;\r
\r
- reg vram_adrs_cnt[14] = 0 ;\r
- reg rSec_cnt[25] = 0 ;\r
- reg rInit_flag = 0 ;\r
- reg rLED[8] = 0 ;\r
- reg test_LED = 0 ;\r
+ reg r_vram_adrs_cnt[14] = 0 ;\r
+ reg r_Sec_cnt[25] = 0 ;\r
+ reg r_Init_flag = 0 ;\r
+ reg r_LED[8] = 0 ;\r
+ reg r_test_LED = 0 ;\r
\r
mem line_buff1[80][8] ;\r
mem line_buff2[80][8] ;\r
\r
- func_self vga_sys_init ;\r
+ func_self fs_vga_sys_init ;\r
\r
- vga_generate U_VGA ;\r
- exp_ctrl U_EXP ;\r
+ vga_generate u_VGA ;\r
+ exp_ctrl U_EXP ;\r
\r
- v_sync_o = U_VGA.v_sync_o ;\r
- h_sync_o = U_VGA.h_sync_o ;\r
- vga_red_o = U_VGA.vga_red_o ;\r
- vga_green_o = U_VGA.vga_green_o ;\r
- vga_blue_o = U_VGA.vga_blue_o ;\r
+ o_v_sync = u_VGA.v_sync_o ;\r
+ o_h_sync = u_VGA.h_sync_o ;\r
+ o_red = u_VGA.vga_red_o ;\r
+ o_green = u_VGA.vga_green_o ;\r
+ o_blue = u_VGA.vga_blue_o ;\r
\r
- if( U_VGA.req_32dot ) {\r
- U_VGA.ack_req_32dot( 32'hFFFFFFFF ) ;\r
+ if( u_VGA.req_32dot ) {\r
+ u_VGA.ack_req_32dot( 32'hFFFFFFFF ) ;\r
}\r
\r
{\r
- cnt := ~cnt ;\r
- oLED = rLED ;\r
+ r_cnt := ~r_cnt ;\r
+ o_LED = r_LED ;\r
\r
- reset := { reset[1:0], 0b0 } ;\r
- if( reset == 0b100 ) vga_sys_init() ;\r
+ r_reset := { r_reset[1:0], 0b0 } ;\r
+ if( r_reset == 0b100 ) fs_vga_sys_init() ;\r
\r
- U_VGA.p_reset = reset[2] ;\r
- U_VGA.m_clock = cnt ;\r
+ u_VGA.p_reset = r_reset[2] ;\r
+ u_VGA.m_clock = r_cnt ;\r
\r
if( U_EXP.foRd_ack ) {\r
- rLED := {\r
+ r_LED := {\r
// U_EXP.oRdata[14],\r
// U_EXP.oRdata[12],\r
U_EXP.oRdata[10],\r
U_EXP.oRdata[4],\r
U_EXP.oRdata[2],\r
U_EXP.oRdata[0],\r
- test_LED,\r
- \r
- rInit_flag\r
+ r_test_LED,\r
+ r_Init_flag\r
} ;\r
}\r
\r
- if( rInit_flag ) {\r
+ if( r_Init_flag ) {\r
any {\r
- rSec_cnt == ONE_SEC : {\r
- U_EXP.fiRd_req( line_cnt2 ) ;\r
- rSec_cnt := 0 ;\r
- test_LED := ~test_LED ;\r
+ r_Sec_cnt == ONE_SEC : {\r
+ U_EXP.fiRd_req( r_line_cnt2 ) ;\r
+ r_Sec_cnt := 0 ;\r
+ r_test_LED := ~r_test_LED ;\r
any {\r
- line_cnt2 == 14'd1000 : line_cnt2 := 0 ;\r
- else : line_cnt2++ ;\r
+ r_line_cnt2 == 14'd1000 : r_line_cnt2 := 0 ;\r
+ else : r_line_cnt2++ ;\r
}\r
}\r
else : {\r
- rSec_cnt++ ;\r
+ r_Sec_cnt++ ;\r
}\r
}\r
} else {\r
- rSec_cnt := 0 ;\r
+ r_Sec_cnt := 0 ;\r
}\r
}\r
\r
- func vga_sys_init seq {\r
-// for(line_cnt=0;line_cnt<80;line_cnt++) {\r
-// line_buff1[line_cnt] := \r
-// }\r
-\r
- for( line_cnt:=0; line_cnt<16384; line_cnt++ ) {\r
- U_EXP.fiWr_req( line_cnt[13:0], line_cnt[7:0] ) ;\r
+ func fs_vga_sys_init seq {\r
+ for( r_line_cnt:=0; r_line_cnt<16384; r_line_cnt++ ) {\r
+ U_EXP.fiWr_req( r_line_cnt[13:0], 8'b11110000 ) ;\r
;\r
}\r
\r
- rInit_flag := 1 ;\r
+ r_Init_flag := 1 ;\r
}\r
}
\ No newline at end of file
-/* VRAM Header File For Altera Config */
-
+/**
+* VRAM Header File For Altera Config
+* Module name is "vram"
+* @author zyanham
+* @version 1.0
+* comment : Hokuto Ujou Danjin Ken!
+*/
declare vram {
- input clock ;
- input data[8] ;
- input rdaddress[14] ;
- input wraddress[14] ;
- input rden ;
- input wren ;
+ input clk ;
+ input d[8] ;
+ input ra[14] ;
+ input wa[14] ;
+ input we ;
output q[8] ;
-}
+}
\ No newline at end of file
--- /dev/null
+/* VRAM\81@Module For Simulation */
+
+declare vram {
+ input clock ;
+ input data[8] ;
+ input rdaddress[14] ;
+ input wraddress[14] ;
+ input wren ;
+ output q[8] ;
+}
+
+module vram {
+ mem m_vram[16384][8] ;
+ reg r_ram_data[8] = 0 ;
+
+ {
+ /* Write part */
+ if(wren) {
+ m_vram[wraddress] := data ;
+ }
+
+ /* Read part */
+ q = r_ram_data ;
+ r_ram_data := m_vram[rdaddress] ;
+ }
+}
\ No newline at end of file
-/* VRAM Control Module */
+/**
+* VRAM Control Module
+* Module name is "vram_ctrl"
+* @author zyanham
+* @version 1.0
+* Comment : Reading Steiner
+*/
#include "vram.nsh"
declare vram_ctrl {
- input iWdata[8] ; // in Write Data
- input iWadrs[14] ; // in Write Address
- input iRadrs[14] ; // in Read Address
- output oRdata[8] ; // out Read Data
+ input i_Wdata[8] ; // in Write Data
+ input i_Wadrs[14] ; // in Write Address
+ input i_Radrs[14] ; // in Read Address
+ output o_Rdata[8] ; // out Read Data
- func_in fiWr_req( iWadrs, iWdata ) ;
- func_in fiRd_req( iRadrs ) ;
- func_out foRd_ack( oRdata ) ;
+ func_in fi_Wr_req( i_Wadrs, i_Wdata ) ;
+ func_in fi_Rd_req( i_Radrs ) ;
+ func_out fo_Rd_ack( o_Rdata ) ;
}
module vram_ctrl{
- vram U_VRAM ;
+ vram u_VRAM ;
- reg rRadrs_hld[14] = 0 ;
+ reg r_Radrs_hld[14] = 0 ;
{
/* Memory Terminal Assign */
- if(~fiWr_req) {
- U_VRAM.wren = 0 ;
+ if(~fi_Wr_req) {
+ u_VRAM.we = 0 ;
}
}
- func fiWr_req {
- U_VRAM.wren = 1 ;
- U_VRAM.data = iWdata ;
- U_VRAM.wraddress = iWadrs ;
+ func fi_Wr_req {
+ u_VRAM.we = 1 ;
+ u_VRAM.d = i_Wdata ;
+ u_VRAM.wa = i_Wadrs ;
}
- func fiRd_req seq {
+ func fi_Rd_req seq {
+ u_VRAM.ra = i_Radrs ;
{
- U_VRAM.rdaddress = iRadrs ;
-
- }
- {
- U_VRAM.rdaddress = rRadrs_hld ;
- foRd_ack( U_VRAM.q ) ;
+ u_VRAM.ra = r_Radrs_hld ;
+ fo_Rd_ack( u_VRAM.q ) ;
}
}
}
\ No newline at end of file
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