return;
for (const auto &SrcOp : Def->explicit_operands())
- if (SrcOp.isUse() && (!SrcOp.isReg() ||
- TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
+ if (SrcOp.isReg() && SrcOp.isUse() &&
+ (TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
SrcOp.getReg() == AMDGPU::EXEC))
Src.push_back(SrcOp);
}
--- /dev/null
+# RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgizcl -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
+
+# Check that assert is not triggered
+# GCN-LABEL: name: si-lower-control-flow{{$}}
+# GCN-CHECK: S_LOAD_DWORD_IMM
+
+--- |
+
+ define amdgpu_kernel void @si-lower-control-flow() {
+ ret void
+ }
+
+...
+---
+name: si-lower-control-flow
+body: |
+ bb.0:
+ %0:sgpr_64 = COPY $sgpr4_sgpr5
+ %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
+ %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
+ %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
+ S_ENDPGM
+...