[ARM] 't' asm constraint should accept i32

't' constraint normally only accepts f32 operands, but for VCVT the
operands can be i32. LLVM is overly restrictive and rejects asm like:

  float foo() {
    float result;
    __asm__ __volatile__(
      "vcvt.f32.s32 %[result], %[arg1]\n"
      : [result]"=t"(result)
      : [arg1]"t"(0x01020304) );
    return result;
  }

Relax the value type for 't' constraint to either f32 or i32.

Differential Revision: https://reviews.llvm.org/D40137

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318472 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 617675c..4f200ec 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -13024,7 +13024,7 @@ RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
         return RCPair(0U, &ARM::QPR_8RegClass);
       break;
     case 't':
-      if (VT == MVT::f32)
+      if (VT == MVT::f32 || VT == MVT::i32)
         return RCPair(0U, &ARM::SPRRegClass);
       break;
     }

diff --git a/test/CodeGen/ARM/inlineasm.ll b/test/CodeGen/ARM/inlineasm.ll
index 39962e0..fdb8938 100644 (file)
--- a/test/CodeGen/ARM/inlineasm.ll
+++ b/test/CodeGen/ARM/inlineasm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
+; RUN: llc -mtriple=armv8-eabi -mattr=+neon %s -o - | FileCheck %s
 
 define i32 @test1(i32 %tmp54) {
        %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )         ; <i32> [#uses=1]
@@ -9,3 +9,10 @@ define void @test2() {
        tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
        ret void
 }
+
+define float @t-constraint-int(i32 %i) {
+       ; CHECK-LABEL: t-constraint-int
+       ; CHECK: vcvt.f32.s32 {{s[0-9]+}}, {{s[0-9]+}}
+       %ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i)
+       ret float %ret
+}