drm/amd/display: Remove dsc disable_ich flag programming.

Current default is sufficient for a flag that does not change.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index ffd0014..e870caa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -436,7 +436,7 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
        reg_vals->ich_reset_at_eol            = 0;
        reg_vals->alternate_ich_encoding_en   = 0;
        reg_vals->rc_buffer_model_size        = 0;
-       reg_vals->disable_ich                 = 0;
+       /*reg_vals->disable_ich                 = 0;*/
        reg_vals->dsc_dbg_en                  = 0;
 
        for (i = 0; i < 4; i++)
@@ -518,9 +518,11 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
                ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
                NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
 
-       REG_SET_2(DSCC_CONFIG1, 0,
+       REG_SET(DSCC_CONFIG1, 0,
+                       DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
+       /*REG_SET_2(DSCC_CONFIG1, 0,
                DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
-               DSCC_DISABLE_ICH, reg_vals->disable_ich);
+               DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
 
        REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
                DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
index 168865a..4e2fb38 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
@@ -103,7 +103,7 @@
        DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
        DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
        DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
-       DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh), \
+       /*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
        DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
        DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
        DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
@@ -278,7 +278,7 @@
        type ALTERNATE_ICH_ENCODING_EN; \
        type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
        type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
-       type DSCC_DISABLE_ICH; \
+       /*type DSCC_DISABLE_ICH;*/ \
        type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
        type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
        type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \