drm/amdgpu: init aperture definitions (v2)

v2: agd: move apertures to mc structure

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 946ef0c..d5eed6b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -570,6 +570,11 @@ struct amdgpu_mc {
        uint32_t                srbm_soft_reset;
        struct amdgpu_mode_mc_save save;
        bool                    prt_warning;
+       /* apertures */
+       u64                                     shared_aperture_start;
+       u64                                     shared_aperture_end;
+       u64                                     private_aperture_start;
+       u64                                     private_aperture_end;
 };
 
 /*

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e471c08..1b8b494 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1889,7 +1889,8 @@ static void gfx_v7_0_config_init(struct amdgpu_device *adev)
  */
 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
 {
-       u32 tmp, sh_mem_cfg;
+       u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
+       u32 tmp;
        int i;
 
        WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
@@ -1920,15 +1921,32 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
        /* where to put LDS, scratch, GPUVM in FSA64 space */
        sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+       sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
+                                  MTYPE_NC);
+       sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
+                                  MTYPE_UC);
+       sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
+
+       sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
+                                  SWIZZLE_ENABLE, 1);
+       sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+                                  ELEMENT_SIZE, 1);
+       sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+                                  INDEX_STRIDE, 3);
 
        mutex_lock(&adev->srbm_mutex);
-       for (i = 0; i < 16; i++) {
+       for (i = 0; i < adev->vm_manager.num_ids; i++) {
+               if (i == 0)
+                       sh_mem_base = 0;
+               else
+                       sh_mem_base = adev->mc.shared_aperture_start >> 48;
                cik_srbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
                WREG32(mmSH_MEM_APE1_BASE, 1);
                WREG32(mmSH_MEM_APE1_LIMIT, 0);
-               WREG32(mmSH_MEM_BASES, 0);
+               WREG32(mmSH_MEM_BASES, sh_mem_base);
+               WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
        }
        cik_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5dcf8db..fefec6e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3859,7 +3859,7 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
 
 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 {
-       u32 tmp;
+       u32 tmp, sh_static_mem_cfg;
        int i;
 
        WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
@@ -3874,8 +3874,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
+       sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
+                                  SWIZZLE_ENABLE, 1);
+       sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+                                  ELEMENT_SIZE, 1);
+       sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+                                  INDEX_STRIDE, 3);
        mutex_lock(&adev->srbm_mutex);
-       for (i = 0; i < 16; i++) {
+       for (i = 0; i < adev->vm_manager.num_ids; i++) {
                vi_srbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                if (i == 0) {
@@ -3884,17 +3890,20 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
                        tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                            SH_MEM_ALIGNMENT_MODE_UNALIGNED);
                        WREG32(mmSH_MEM_CONFIG, tmp);
+                       WREG32(mmSH_MEM_BASES, 0);
                } else {
                        tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
-                       tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
+                       tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
                        tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                            SH_MEM_ALIGNMENT_MODE_UNALIGNED);
                        WREG32(mmSH_MEM_CONFIG, tmp);
+                       tmp = adev->mc.shared_aperture_start >> 48;
+                       WREG32(mmSH_MEM_BASES, tmp);
                }
 
                WREG32(mmSH_MEM_APE1_BASE, 1);
                WREG32(mmSH_MEM_APE1_LIMIT, 0);
-               WREG32(mmSH_MEM_BASES, 0);
+               WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
        }
        vi_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 552bf6b..13efb67 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -934,6 +934,14 @@ static int gmc_v7_0_early_init(void *handle)
        gmc_v7_0_set_gart_funcs(adev);
        gmc_v7_0_set_irq_funcs(adev);
 
+       adev->mc.shared_aperture_start = 0x2000000000000000ULL;
+       adev->mc.shared_aperture_end =
+               adev->mc.shared_aperture_start + (4ULL << 30) - 1;
+       adev->mc.private_aperture_start =
+               adev->mc.shared_aperture_end + 1;
+       adev->mc.private_aperture_end =
+               adev->mc.private_aperture_start + (4ULL << 30) - 1;
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f2bd016..952ba1e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -939,6 +939,14 @@ static int gmc_v8_0_early_init(void *handle)
        gmc_v8_0_set_gart_funcs(adev);
        gmc_v8_0_set_irq_funcs(adev);
 
+       adev->mc.shared_aperture_start = 0x2000000000000000ULL;
+       adev->mc.shared_aperture_end =
+               adev->mc.shared_aperture_start + (4ULL << 30) - 1;
+       adev->mc.private_aperture_start =
+               adev->mc.shared_aperture_end + 1;
+       adev->mc.private_aperture_end =
+               adev->mc.private_aperture_start + (4ULL << 30) - 1;
+
        return 0;
 }