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drm/msm/dsi: Add phy configuration for MSM8953
authorVladimir Lypak <vladimir.lypak@gmail.com>
Tue, 28 Sep 2021 13:19:28 +0000 (18:49 +0530)
committerRob Clark <robdclark@chromium.org>
Fri, 15 Oct 2021 20:26:34 +0000 (13:26 -0700)
Add phy configuration for 14nm dsi phy found on MSM8953 SoC. Only
difference from existing configurations are io_start addresses.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sireesh Kodali <sireeshkodali1@gmail.com>
Link: https://lore.kernel.org/r/20210928131929.18567-3-sireeshkodali1@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

index 8c65ef6..9842e04 100644 (file)
@@ -627,6 +627,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
          .data = &dsi_phy_14nm_cfgs },
        { .compatible = "qcom,dsi-phy-14nm-660",
          .data = &dsi_phy_14nm_660_cfgs },
+       { .compatible = "qcom,dsi-phy-14nm-8953",
+         .data = &dsi_phy_14nm_8953_cfgs },
 #endif
 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
        { .compatible = "qcom,dsi-phy-10nm",
index b91303a..4c82575 100644 (file)
@@ -48,6 +48,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
index c62d903..7414966 100644 (file)
@@ -1063,3 +1063,24 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
        .io_start = { 0xc994400, 0xc996000 },
        .num_dsi_phy = 2,
 };
+
+const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
+       .has_phy_lane = true,
+       .reg_cfg = {
+               .num = 1,
+               .regs = {
+                       {"vcca", 17000, 32},
+               },
+       },
+       .ops = {
+               .enable = dsi_14nm_phy_enable,
+               .disable = dsi_14nm_phy_disable,
+               .pll_init = dsi_pll_14nm_init,
+               .save_pll_state = dsi_14nm_pll_save_state,
+               .restore_pll_state = dsi_14nm_pll_restore_state,
+       },
+       .min_pll_rate = VCO_MIN_RATE,
+       .max_pll_rate = VCO_MAX_RATE,
+       .io_start = { 0x1a94400, 0x1a96400 },
+       .num_dsi_phy = 2,
+};