// R600 Passes
FunctionPass* createR600KernelParametersPass(const TargetData* TD);
-FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
// SI Passes
#define GET_INSTRINFO_ENUM
#include "AMDGPUGenInstrInfo.inc"
-#define MO_FLAG_CLAMP (1 << 0)
-#define MO_FLAG_NEG (1 << 1)
-#define MO_FLAG_ABS (1 << 2)
-#define MO_FLAG_MASK (1 << 3)
-#define MO_FLAG_PUSH (1 << 4)
-#define MO_FLAG_LAST (1 << 5)
-#define NUM_MO_FLAGS 6
-
#define OPCODE_IS_ZERO_INT 0x00000045
#define OPCODE_IS_NOT_ZERO_INT 0x00000042
#define OPCODE_IS_ZERO 0x00000020
#include "AMDGPUMCInstLower.h"
#include "AMDGPUAsmPrinter.h"
+#include "R600InstrInfo.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Constants.h"
#include "llvm/MC/MCInst.h"
void AMDGPUMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
switch (MO.getType()) {
default:
- MI->dump();
llvm_unreachable("unknown operand type");
case MachineOperand::MO_FPImmediate: {
const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
AMDGPUMCInstLower MCInstLowering;
- MCInst TmpInst;
- MCInstLowering.Lower(MI, TmpInst);
- OutStreamer.EmitInstruction(TmpInst);
+
+ // Ignore placeholder instructions:
+ if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
+ return;
+ }
+
+ if (MI->isBundle()) {
+ const MachineBasicBlock *MBB = MI->getParent();
+ MachineBasicBlock::const_instr_iterator I = MI;
+ ++I;
+ while (I != MBB->end() && I->isInsideBundle()) {
+ MCInst MCBundleInst;
+ const MachineInstr *BundledInst = I;
+ MCInstLowering.Lower(BundledInst, MCBundleInst);
+ OutStreamer.EmitInstruction(MCBundleInst);
+ ++I;
+ }
+ } else {
+ MCInst TmpInst;
+ MCInstLowering.Lower(MI, TmpInst);
+ OutStreamer.EmitInstruction(TmpInst);
+ }
}
{
}
-bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
- formatted_raw_ostream &Out,
- CodeGenFileType FileType,
- bool DisableVerify) {
-
- const AMDGPUSubtarget &STM = getSubtarget<AMDGPUSubtarget>();
- std::string gpu = STM.getDeviceName();
- if (gpu == "SI") {
- return LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
- DisableVerify);
- } else if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
- // XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
- // only using it to access addPassesToGenerateCode()
- bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
- DisableVerify);
- assert(fail);
- PM.add(createR600CodeEmitterPass(Out));
- } else {
- abort();
- return true;
- }
- PM.add(createGCInfoDeleter());
-
- return false;
-}
-
namespace {
class AMDGPUPassConfig : public TargetPassConfig {
public:
}
virtual const TargetData* getTargetData() const { return &DataLayout; }
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
- virtual bool addPassesToEmitFile(PassManagerBase &PM,
- formatted_raw_ostream &Out,
- CodeGenFileType FileType,
- bool DisableVerify);
};
} // End namespace llvm
return new AMDGPUInstPrinter(MAI, MII, MRI);
}
+static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
+ if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
+ return createSIMCCodeEmitter(MCII, STI, Ctx);
+ } else {
+ return createR600MCCodeEmitter(MCII, STI, Ctx);
+ }
+}
+
static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
MCContext &Ctx, MCAsmBackend &MAB,
raw_ostream &_OS,
extern Target TheAMDGPUTarget;
-MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx);
+MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx);
+
+MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT);
} // End llvm namespace
--- /dev/null
+//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This code emitters outputs bytecode that is understood by the r600g driver
+// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
+// except that the size of the instruction fields are rounded up to the
+// nearest byte.
+//
+// [1] http://www.mesa3d.org/
+//
+//===----------------------------------------------------------------------===//
+
+#include "R600Defines.h"
+#include "MCTargetDesc/AMDILMCTargetDesc.h"
+#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/raw_ostream.h"
+
+#include <stdio.h>
+
+#define SRC_BYTE_COUNT 11
+#define DST_BYTE_COUNT 5
+
+using namespace llvm;
+
+namespace {
+
+class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
+ R600MCCodeEmitter(const R600MCCodeEmitter &); // DO NOT IMPLEMENT
+ void operator=(const R600MCCodeEmitter &); // DO NOT IMPLEMENT
+ const MCInstrInfo &MCII;
+ const MCSubtargetInfo &STI;
+ MCContext &Ctx;
+
+public:
+
+ R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
+ MCContext &ctx)
+ : MCII(mcii), STI(sti), Ctx(ctx) { }
+
+ /// EncodeInstruction - Encode the instruction and write it to the OS.
+ virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+
+ /// getMachineOpValue - Reutrn the encoding for an MCOperand.
+ virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+private:
+
+ void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
+ raw_ostream &OS) const;
+ void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
+ void EmitDst(const MCInst &MI, raw_ostream &OS) const;
+ void EmitALU(const MCInst &MI, unsigned numSrc,
+ SmallVectorImpl<MCFixup> &Fixups,
+ raw_ostream &OS) const;
+ void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
+ raw_ostream &OS) const;
+ void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
+
+ void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
+
+ void EmitByte(unsigned int byte, raw_ostream &OS) const;
+
+ void EmitTwoBytes(uint32_t bytes, raw_ostream &OS) const;
+
+ void Emit(uint32_t value, raw_ostream &OS) const;
+ void Emit(uint64_t value, raw_ostream &OS) const;
+
+ unsigned getHWRegIndex(unsigned reg) const;
+ unsigned getHWRegChan(unsigned reg) const;
+ unsigned getHWReg(unsigned regNo) const;
+
+ bool isFCOp(unsigned opcode) const;
+ bool isTexOp(unsigned opcode) const;
+ bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
+
+ /// getHWRegIndexGen - Get the register's hardware index. Implemented in
+ /// R600HwRegInfo.include.
+ unsigned getHWRegIndexGen(unsigned int Reg) const;
+
+ /// getHWRegChanGen - Get the register's channel. Implemented in
+ /// R600HwRegInfo.include.
+ unsigned getHWRegChanGen(unsigned int Reg) const;
+};
+
+} // End anonymous namespace
+
+enum RegElement {
+ ELEMENT_X = 0,
+ ELEMENT_Y,
+ ELEMENT_Z,
+ ELEMENT_W
+};
+
+enum InstrTypes {
+ INSTR_ALU = 0,
+ INSTR_TEX,
+ INSTR_FC,
+ INSTR_NATIVE,
+ INSTR_VTX
+};
+
+enum FCInstr {
+ FC_IF = 0,
+ FC_IF_INT,
+ FC_ELSE,
+ FC_ENDIF,
+ FC_BGNLOOP,
+ FC_ENDLOOP,
+ FC_BREAK,
+ FC_BREAK_NZ_INT,
+ FC_CONTINUE,
+ FC_BREAK_Z_INT,
+ FC_BREAK_NZ
+};
+
+enum TextureTypes {
+ TEXTURE_1D = 1,
+ TEXTURE_2D,
+ TEXTURE_3D,
+ TEXTURE_CUBE,
+ TEXTURE_RECT,
+ TEXTURE_SHADOW1D,
+ TEXTURE_SHADOW2D,
+ TEXTURE_SHADOWRECT,
+ TEXTURE_1D_ARRAY,
+ TEXTURE_2D_ARRAY,
+ TEXTURE_SHADOW1D_ARRAY,
+ TEXTURE_SHADOW2D_ARRAY
+};
+
+MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
+ return new R600MCCodeEmitter(MCII, STI, Ctx);
+}
+
+void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+ SmallVectorImpl<MCFixup> &Fixups) const {
+/*
+ if (MI.getNumOperands() > 1 && MI.getOperand(0).isReg() &&
+ MI.getOperand(0).isDead()) {
+ return;
+ }
+*/
+ if (isTexOp(MI.getOpcode())) {
+ EmitTexInstr(MI, Fixups, OS);
+ } else if (isFCOp(MI.getOpcode())){
+ EmitFCInstr(MI, OS);
+ } else if (MI.getOpcode() == AMDGPU::RETURN ||
+ MI.getOpcode() == AMDGPU::BUNDLE ||
+ MI.getOpcode() == AMDGPU::KILL) {
+ return;
+ } else {
+ switch(MI.getOpcode()) {
+ case AMDGPU::RAT_WRITE_CACHELESS_eg:
+ {
+ uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
+ // XXX: Set End Of Program bit when necessary
+ // inst |= (((uint64_t)1) << 53);
+ EmitByte(INSTR_NATIVE, OS);
+ Emit(inst, OS);
+ break;
+ }
+ case AMDGPU::VTX_READ_PARAM_i32_eg:
+ case AMDGPU::VTX_READ_PARAM_f32_eg:
+ case AMDGPU::VTX_READ_GLOBAL_i32_eg:
+ case AMDGPU::VTX_READ_GLOBAL_f32_eg:
+ case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
+ case AMDGPU::VTX_READ_GLOBAL_v4f32_eg:
+ {
+ uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
+ uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
+
+ EmitByte(INSTR_VTX, OS);
+ Emit(InstWord01, OS);
+ Emit(InstWord2, OS);
+ break;
+ }
+
+ default:
+ EmitALUInstr(MI, Fixups, OS);
+ break;
+ }
+ }
+}
+
+void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
+ SmallVectorImpl<MCFixup> &Fixups,
+ raw_ostream &OS) const {
+ const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
+ unsigned NumOperands = MI.getNumOperands();
+
+ if(MCDesc.findFirstPredOperandIdx() > -1)
+ NumOperands--;
+
+ if (GET_FLAG_OPERAND_IDX(MCDesc.TSFlags) != 0)
+ NumOperands--;
+
+ // Some instructions are just place holder instructions that represent
+ // operations that the GPU does automatically. They should be ignored.
+// if (TII->isPlaceHolderOpcode(MI.getOpcode())) {
+// return;
+// }
+
+ if(MI.getOpcode() == AMDGPU::PRED_X)
+ NumOperands = 2;
+
+ // XXX Check if instruction writes a result
+ if (NumOperands < 1) {
+ return;
+ }
+
+ // Emit instruction type
+ EmitByte(0, OS);
+
+ unsigned int OpIndex;
+ for (OpIndex = 1; OpIndex < NumOperands; OpIndex++) {
+ // Literal constants are always stored as the last operand.
+ if (MI.getOperand(OpIndex).isImm() || MI.getOperand(OpIndex).isFPImm()) {
+ break;
+ }
+ EmitSrc(MI, OpIndex, OS);
+ }
+
+ // Emit zeros for unused sources
+ for ( ; OpIndex < 4; OpIndex++) {
+ EmitNullBytes(SRC_BYTE_COUNT, OS);
+ }
+
+ EmitDst(MI, OS);
+
+ EmitALU(MI, NumOperands - 1, Fixups, OS);
+}
+
+void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
+ raw_ostream &OS) const {
+ const MCOperand &MO = MI.getOperand(OpIdx);
+ union {
+ float f;
+ uint32_t i;
+ } Value;
+ Value.i = 0;
+ // Emit the source select (2 bytes). For GPRs, this is the register index.
+ // For other potential instruction operands, (e.g. constant registers) the
+ // value of the source select is defined in the r600isa docs.
+ if (MO.isReg()) {
+ unsigned reg = MO.getReg();
+ EmitTwoBytes(getHWReg(reg), OS);
+ if (reg == AMDGPU::ALU_LITERAL_X) {
+ unsigned ImmOpIndex = MI.getNumOperands() - 1;
+ MCOperand ImmOp = MI.getOperand(ImmOpIndex);
+ if (ImmOp.isFPImm()) {
+ Value.f = ImmOp.getFPImm();
+ } else {
+ assert(ImmOp.isImm());
+ Value.i = ImmOp.getImm();
+ }
+ }
+ } else {
+ // XXX: Handle other operand types.
+ EmitTwoBytes(0, OS);
+ }
+
+ // Emit the source channel (1 byte)
+ if (MO.isReg()) {
+ EmitByte(getHWRegChan(MO.getReg()), OS);
+ } else {
+ EmitByte(0, OS);
+ }
+
+ // XXX: Emit isNegated (1 byte)
+ if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
+ && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
+ (MO.isReg() &&
+ (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
+ EmitByte(1, OS);
+ } else {
+ EmitByte(0, OS);
+ }
+
+ // Emit isAbsolute (1 byte)
+ if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
+ EmitByte(1, OS);
+ } else {
+ EmitByte(0, OS);
+ }
+
+ // XXX: Emit relative addressing mode (1 byte)
+ EmitByte(0, OS);
+
+ // Emit kc_bank, This will be adjusted later by r600_asm
+ EmitByte(0, OS);
+
+ // Emit the literal value, if applicable (4 bytes).
+ Emit(Value.i, OS);
+
+}
+
+void R600MCCodeEmitter::EmitDst(const MCInst &MI, raw_ostream &OS) const {
+
+ const MCOperand &MO = MI.getOperand(0);
+ if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
+ // Emit the destination register index (1 byte)
+ EmitByte(getHWReg(MO.getReg()), OS);
+
+ // Emit the element of the destination register (1 byte)
+ EmitByte(getHWRegChan(MO.getReg()), OS);
+
+ // Emit isClamped (1 byte)
+ if (isFlagSet(MI, 0, MO_FLAG_CLAMP)) {
+ EmitByte(1, OS);
+ } else {
+ EmitByte(0, OS);
+ }
+
+ // Emit writemask (1 byte).
+ if (isFlagSet(MI, 0, MO_FLAG_MASK)) {
+ EmitByte(0, OS);
+ } else {
+ EmitByte(1, OS);
+ }
+
+ // XXX: Emit relative addressing mode
+ EmitByte(0, OS);
+ } else {
+ // XXX: Handle other operand types. Are there any for destination regs?
+ EmitNullBytes(DST_BYTE_COUNT, OS);
+ }
+}
+
+void R600MCCodeEmitter::EmitALU(const MCInst &MI, unsigned numSrc,
+ SmallVectorImpl<MCFixup> &Fixups,
+ raw_ostream &OS) const {
+ const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
+
+ // Emit the instruction (2 bytes)
+ EmitTwoBytes(getBinaryCodeForInstr(MI, Fixups), OS);
+
+ // Emit IsLast (for this instruction group) (1 byte)
+ if (isFlagSet(MI, 0, MO_FLAG_NOT_LAST)) {
+ EmitByte(0, OS);
+ } else {
+ EmitByte(1, OS);
+ }
+
+ // Emit isOp3 (1 byte)
+ if (numSrc == 3) {
+ EmitByte(1, OS);
+ } else {
+ EmitByte(0, OS);
+ }
+
+ // XXX: Emit push modifier
+ if(isFlagSet(MI, 1, MO_FLAG_PUSH)) {
+ EmitByte(1, OS);
+ } else {
+ EmitByte(0, OS);
+ }
+
+ // XXX: Emit predicate (1 byte)
+ int PredIdx = MCDesc.findFirstPredOperandIdx();
+ if (PredIdx > -1)
+ switch(MI.getOperand(PredIdx).getReg()) {
+ case AMDGPU::PRED_SEL_ZERO:
+ EmitByte(2, OS);
+ break;
+ case AMDGPU::PRED_SEL_ONE:
+ EmitByte(3, OS);
+ break;
+ default:
+ EmitByte(0, OS);
+ break;
+ }
+ else {
+ EmitByte(0, OS);
+ }
+
+
+ // XXX: Emit bank swizzle. (1 byte) Do we need this? It looks like
+ // r600_asm.c sets it.
+ EmitByte(0, OS);
+
+ // XXX: Emit bank_swizzle_force (1 byte) Not sure what this is for.
+ EmitByte(0, OS);
+
+ // XXX: Emit OMOD (1 byte) Not implemented.
+ EmitByte(0, OS);
+
+ // XXX: Emit index_mode. I think this is for indirect addressing, so we
+ // don't need to worry about it.
+ EmitByte(0, OS);
+}
+
+void R600MCCodeEmitter::EmitTexInstr(const MCInst &MI,
+ SmallVectorImpl<MCFixup> &Fixups,
+ raw_ostream &OS) const {
+
+ unsigned opcode = MI.getOpcode();
+ bool hasOffsets = (opcode == AMDGPU::TEX_LD);
+ unsigned op_offset = hasOffsets ? 3 : 0;
+ int64_t sampler = MI.getOperand(op_offset+2).getImm();
+ int64_t textureType = MI.getOperand(op_offset+3).getImm();
+ unsigned srcSelect[4] = {0, 1, 2, 3};
+
+ // Emit instruction type
+ EmitByte(1, OS);
+
+ // Emit instruction
+ EmitByte(getBinaryCodeForInstr(MI, Fixups), OS);
+
+ // XXX: Emit resource id r600_shader.c uses sampler + 1. Why?
+ EmitByte(sampler + 1 + 1, OS);
+
+ // Emit source register
+ EmitByte(getHWReg(MI.getOperand(1).getReg()), OS);
+
+ // XXX: Emit src isRelativeAddress
+ EmitByte(0, OS);
+
+ // Emit destination register
+ EmitByte(getHWReg(MI.getOperand(0).getReg()), OS);
+
+ // XXX: Emit dst isRealtiveAddress
+ EmitByte(0, OS);
+
+ // XXX: Emit dst select
+ EmitByte(0, OS); // X
+ EmitByte(1, OS); // Y
+ EmitByte(2, OS); // Z
+ EmitByte(3, OS); // W
+
+ // XXX: Emit lod bias
+ EmitByte(0, OS);
+
+ // XXX: Emit coord types
+ unsigned coordType[4] = {1, 1, 1, 1};
+
+ if (textureType == TEXTURE_RECT
+ || textureType == TEXTURE_SHADOWRECT) {
+ coordType[ELEMENT_X] = 0;
+ coordType[ELEMENT_Y] = 0;
+ }
+
+ if (textureType == TEXTURE_1D_ARRAY
+ || textureType == TEXTURE_SHADOW1D_ARRAY) {
+ if (opcode == AMDGPU::TEX_SAMPLE_C_L || opcode == AMDGPU::TEX_SAMPLE_C_LB) {
+ coordType[ELEMENT_Y] = 0;
+ } else {
+ coordType[ELEMENT_Z] = 0;
+ srcSelect[ELEMENT_Z] = ELEMENT_Y;
+ }
+ } else if (textureType == TEXTURE_2D_ARRAY
+ || textureType == TEXTURE_SHADOW2D_ARRAY) {
+ coordType[ELEMENT_Z] = 0;
+ }
+
+ for (unsigned i = 0; i < 4; i++) {
+ EmitByte(coordType[i], OS);
+ }
+
+ // XXX: Emit offsets
+ if (hasOffsets)
+ for (unsigned i = 2; i < 5; i++)
+ EmitByte(MI.getOperand(i).getImm()<<1, OS);
+ else
+ EmitNullBytes(3, OS);
+
+ // Emit sampler id
+ EmitByte(sampler, OS);
+
+ // XXX:Emit source select
+ if ((textureType == TEXTURE_SHADOW1D
+ || textureType == TEXTURE_SHADOW2D
+ || textureType == TEXTURE_SHADOWRECT
+ || textureType == TEXTURE_SHADOW1D_ARRAY)
+ && opcode != AMDGPU::TEX_SAMPLE_C_L
+ && opcode != AMDGPU::TEX_SAMPLE_C_LB) {
+ srcSelect[ELEMENT_W] = ELEMENT_Z;
+ }
+
+ for (unsigned i = 0; i < 4; i++) {
+ EmitByte(srcSelect[i], OS);
+ }
+}
+
+void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
+
+ // Emit instruction type
+ EmitByte(INSTR_FC, OS);
+
+ // Emit SRC
+ unsigned NumOperands = MI.getNumOperands();
+ if (NumOperands > 0) {
+ assert(NumOperands == 1);
+ EmitSrc(MI, 0, OS);
+ } else {
+ EmitNullBytes(SRC_BYTE_COUNT, OS);
+ }
+
+ // Emit FC Instruction
+ enum FCInstr instr;
+ switch (MI.getOpcode()) {
+ case AMDGPU::BREAK_LOGICALZ_f32:
+ instr = FC_BREAK;
+ break;
+ case AMDGPU::BREAK_LOGICALNZ_f32:
+ instr = FC_BREAK_NZ;
+ break;
+ case AMDGPU::BREAK_LOGICALNZ_i32:
+ instr = FC_BREAK_NZ_INT;
+ break;
+ case AMDGPU::BREAK_LOGICALZ_i32:
+ instr = FC_BREAK_Z_INT;
+ break;
+ case AMDGPU::CONTINUE_LOGICALNZ_f32:
+ case AMDGPU::CONTINUE_LOGICALNZ_i32:
+ instr = FC_CONTINUE;
+ break;
+ case AMDGPU::IF_LOGICALNZ_f32:
+ instr = FC_IF;
+ case AMDGPU::IF_LOGICALNZ_i32:
+ instr = FC_IF_INT;
+ break;
+ case AMDGPU::IF_LOGICALZ_f32:
+ abort();
+ break;
+ case AMDGPU::ELSE:
+ instr = FC_ELSE;
+ break;
+ case AMDGPU::ENDIF:
+ instr = FC_ENDIF;
+ break;
+ case AMDGPU::ENDLOOP:
+ instr = FC_ENDLOOP;
+ break;
+ case AMDGPU::WHILELOOP:
+ instr = FC_BGNLOOP;
+ break;
+ default:
+ abort();
+ break;
+ }
+ EmitByte(instr, OS);
+}
+
+void R600MCCodeEmitter::EmitNullBytes(unsigned int ByteCount,
+ raw_ostream &OS) const {
+
+ for (unsigned int i = 0; i < ByteCount; i++) {
+ EmitByte(0, OS);
+ }
+}
+
+void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
+ OS.write((uint8_t) Byte & 0xff);
+}
+
+void R600MCCodeEmitter::EmitTwoBytes(unsigned int Bytes,
+ raw_ostream &OS) const {
+ OS.write((uint8_t) (Bytes & 0xff));
+ OS.write((uint8_t) ((Bytes >> 8) & 0xff));
+}
+
+void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
+ for (unsigned i = 0; i < 4; i++) {
+ OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
+ }
+}
+
+void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
+ for (unsigned i = 0; i < 8; i++) {
+ EmitByte((Value >> (8 * i)) & 0xff, OS);
+ }
+}
+
+unsigned R600MCCodeEmitter::getHWRegIndex(unsigned reg) const {
+ switch(reg) {
+ case AMDGPU::ZERO: return 248;
+ case AMDGPU::ONE:
+ case AMDGPU::NEG_ONE: return 249;
+ case AMDGPU::ONE_INT: return 250;
+ case AMDGPU::HALF:
+ case AMDGPU::NEG_HALF: return 252;
+ case AMDGPU::ALU_LITERAL_X: return 253;
+ case AMDGPU::PREDICATE_BIT:
+ case AMDGPU::PRED_SEL_OFF:
+ case AMDGPU::PRED_SEL_ZERO:
+ case AMDGPU::PRED_SEL_ONE:
+ return 0;
+ default: return getHWRegIndexGen(reg);
+ }
+}
+
+unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
+ switch(reg) {
+ case AMDGPU::ZERO:
+ case AMDGPU::ONE:
+ case AMDGPU::ONE_INT:
+ case AMDGPU::NEG_ONE:
+ case AMDGPU::HALF:
+ case AMDGPU::NEG_HALF:
+ case AMDGPU::ALU_LITERAL_X:
+ case AMDGPU::PREDICATE_BIT:
+ case AMDGPU::PRED_SEL_OFF:
+ case AMDGPU::PRED_SEL_ZERO:
+ case AMDGPU::PRED_SEL_ONE:
+ return 0;
+ default: return getHWRegChanGen(reg);
+ }
+}
+unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
+ unsigned HWReg;
+
+ HWReg = getHWRegIndex(RegNo);
+ if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(RegNo)) {
+ HWReg += 512;
+ }
+ return HWReg;
+}
+
+uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
+ const MCOperand &MO,
+ SmallVectorImpl<MCFixup> &Fixup) const {
+ if (MO.isReg()) {
+ return getHWReg(MO.getReg());
+ } else {
+ return MO.getImm();
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// Encoding helper functions
+//===----------------------------------------------------------------------===//
+
+bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
+ switch(opcode) {
+ default: return false;
+ case AMDGPU::BREAK_LOGICALZ_f32:
+ case AMDGPU::BREAK_LOGICALNZ_i32:
+ case AMDGPU::BREAK_LOGICALZ_i32:
+ case AMDGPU::BREAK_LOGICALNZ_f32:
+ case AMDGPU::CONTINUE_LOGICALNZ_f32:
+ case AMDGPU::IF_LOGICALNZ_i32:
+ case AMDGPU::IF_LOGICALZ_f32:
+ case AMDGPU::ELSE:
+ case AMDGPU::ENDIF:
+ case AMDGPU::ENDLOOP:
+ case AMDGPU::IF_LOGICALNZ_f32:
+ case AMDGPU::WHILELOOP:
+ return true;
+ }
+}
+
+bool R600MCCodeEmitter::isTexOp(unsigned opcode) const {
+ switch(opcode) {
+ default: return false;
+ case AMDGPU::TEX_LD:
+ case AMDGPU::TEX_GET_TEXTURE_RESINFO:
+ case AMDGPU::TEX_SAMPLE:
+ case AMDGPU::TEX_SAMPLE_C:
+ case AMDGPU::TEX_SAMPLE_L:
+ case AMDGPU::TEX_SAMPLE_C_L:
+ case AMDGPU::TEX_SAMPLE_LB:
+ case AMDGPU::TEX_SAMPLE_C_LB:
+ case AMDGPU::TEX_SAMPLE_G:
+ case AMDGPU::TEX_SAMPLE_C_G:
+ case AMDGPU::TEX_GET_GRADIENTS_H:
+ case AMDGPU::TEX_GET_GRADIENTS_V:
+ case AMDGPU::TEX_SET_GRADIENTS_H:
+ case AMDGPU::TEX_SET_GRADIENTS_V:
+ return true;
+ }
+}
+
+bool R600MCCodeEmitter::isFlagSet(const MCInst &MI, unsigned Operand,
+ unsigned Flag) const {
+ const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
+ unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MCDesc.TSFlags);
+ if (FlagIndex == 0) {
+ return false;
+ }
+ assert(MI.getOperand(FlagIndex).isImm());
+ return !!((MI.getOperand(FlagIndex).getImm() >>
+ (NUM_MO_FLAGS * Operand)) & Flag);
+}
+#define R600RegisterInfo R600MCCodeEmitter
+#include "R600HwRegInfo.include"
+#undef R600RegisterInfo
+
+#include "AMDGPUGenMCCodeEmitter.inc"
} // End anonymous namespace
-MCCodeEmitter *llvm::createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
- return new SIMCCodeEmitter(MCII, STI, Ctx);
- } else {
- return NULL;
- }
+MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
+ return new SIMCCodeEmitter(MCII, STI, Ctx);
}
void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
#define SIRegisterInfo SIMCCodeEmitter
#include "SIRegisterGetHWRegNum.inc"
#undef SIRegisterInfo
-
-#include "AMDGPUGenMCCodeEmitter.inc"
AMDGPUConvertToISA.cpp \
AMDGPUInstrInfo.cpp \
AMDGPURegisterInfo.cpp \
- R600CodeEmitter.cpp \
R600ExpandSpecialInstrs.cpp \
R600ISelLowering.cpp \
R600InstrInfo.cpp \
MCTargetDesc/AMDGPUAsmBackend.cpp \
MCTargetDesc/AMDILMCTargetDesc.cpp \
MCTargetDesc/SIMCCodeEmitter.cpp \
+ MCTargetDesc/R600MCCodeEmitter.cpp \
TargetInfo/AMDILTargetInfo.cpp \
radeon_llvm_emit.cpp
+++ /dev/null
-//===-- R600CodeEmitter.cpp - Code Emitter for R600->Cayman GPU families --===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This code emitters outputs bytecode that is understood by the r600g driver
-// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
-// except that the size of the instruction fields are rounded up to the
-// nearest byte.
-//
-// [1] http://www.mesa3d.org/
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "AMDGPUCodeEmitter.h"
-#include "AMDGPUInstrInfo.h"
-#include "AMDILUtilityFunctions.h"
-#include "R600InstrInfo.h"
-#include "R600RegisterInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/DataTypes.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/Target/TargetMachine.h"
-
-#include <stdio.h>
-
-#define SRC_BYTE_COUNT 11
-#define DST_BYTE_COUNT 5
-
-using namespace llvm;
-
-namespace {
-
-class R600CodeEmitter : public MachineFunctionPass, public AMDGPUCodeEmitter {
-
-private:
-
- static char ID;
- formatted_raw_ostream &_OS;
- const TargetMachine * TM;
- const MachineRegisterInfo * MRI;
- const R600RegisterInfo * TRI;
- const R600InstrInfo * TII;
-
- unsigned currentElement;
-
- unsigned section_start;
-
-public:
-
- R600CodeEmitter(formatted_raw_ostream &OS) : MachineFunctionPass(ID),
- _OS(OS), TM(NULL) { }
-
- const char *getPassName() const { return "AMDGPU Machine Code Emitter"; }
-
- bool runOnMachineFunction(MachineFunction &MF);
- virtual uint64_t getMachineOpValue(const MachineInstr &MI,
- const MachineOperand &MO) const;
-
-private:
-
- void EmitALUInstr(MachineInstr &MI);
- void EmitSrc(const MachineOperand & MO, unsigned SrcIdx);
- void EmitDst(const MachineOperand & MO);
- void EmitALU(MachineInstr &MI, unsigned numSrc);
- void EmitTexInstr(MachineInstr &MI);
- void EmitFCInstr(MachineInstr &MI);
-
- void EmitNullBytes(unsigned int byteCount);
-
- void EmitByte(unsigned int byte);
-
- void EmitTwoBytes(uint32_t bytes);
-
- void Emit(uint32_t value);
- void Emit(uint64_t value);
-
- unsigned getHWReg(unsigned regNo) const;
-
-};
-
-} // End anonymous namespace
-
-enum RegElement {
- ELEMENT_X = 0,
- ELEMENT_Y,
- ELEMENT_Z,
- ELEMENT_W
-};
-
-enum InstrTypes {
- INSTR_ALU = 0,
- INSTR_TEX,
- INSTR_FC,
- INSTR_NATIVE,
- INSTR_VTX
-};
-
-enum FCInstr {
- FC_IF = 0,
- FC_IF_INT,
- FC_ELSE,
- FC_ENDIF,
- FC_BGNLOOP,
- FC_ENDLOOP,
- FC_BREAK,
- FC_BREAK_NZ_INT,
- FC_CONTINUE,
- FC_BREAK_Z_INT,
- FC_BREAK_NZ
-};
-
-enum TextureTypes {
- TEXTURE_1D = 1,
- TEXTURE_2D,
- TEXTURE_3D,
- TEXTURE_CUBE,
- TEXTURE_RECT,
- TEXTURE_SHADOW1D,
- TEXTURE_SHADOW2D,
- TEXTURE_SHADOWRECT,
- TEXTURE_1D_ARRAY,
- TEXTURE_2D_ARRAY,
- TEXTURE_SHADOW1D_ARRAY,
- TEXTURE_SHADOW2D_ARRAY
-};
-
-char R600CodeEmitter::ID = 0;
-
-FunctionPass *llvm::createR600CodeEmitterPass(formatted_raw_ostream &OS) {
- return new R600CodeEmitter(OS);
-}
-
-bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
-
- TM = &MF.getTarget();
- MRI = &MF.getRegInfo();
- TRI = static_cast<const R600RegisterInfo *>(TM->getRegisterInfo());
- TII = static_cast<const R600InstrInfo *>(TM->getInstrInfo());
- const AMDGPUSubtarget &STM = TM->getSubtarget<AMDGPUSubtarget>();
- std::string gpu = STM.getDeviceName();
-
- if (STM.dumpCode()) {
- MF.dump();
- }
-
- for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
- BB != BB_E; ++BB) {
- MachineBasicBlock &MBB = *BB;
- for (MachineBasicBlock::instr_iterator I = MBB.instr_begin(),
- E = MBB.instr_end(); I != E; ++I) {
- MachineInstr &MI = *I;
- if (MI.getNumOperands() > 1 && MI.getOperand(0).isReg() && MI.getOperand(0).isDead()) {
- continue;
- }
- if (TII->isTexOp(MI.getOpcode())) {
- EmitTexInstr(MI);
- } else if (TII->isFCOp(MI.getOpcode())){
- EmitFCInstr(MI);
- } else if (MI.getOpcode() == AMDGPU::RETURN ||
- MI.getOpcode() == AMDGPU::BUNDLE ||
- MI.getOpcode() == AMDGPU::KILL) {
- continue;
- } else {
- switch(MI.getOpcode()) {
- case AMDGPU::RAT_WRITE_CACHELESS_eg:
- {
- uint64_t inst = getBinaryCodeForInstr(MI);
- // Set End Of Program bit
- // XXX: Need better check of end of program. EOP should be
- // encoded in one of the operands of the MI, and it should be
- // set in a prior pass.
- MachineBasicBlock::iterator NextI = llvm::next(I);
- MachineInstr &NextMI = *NextI;
- if (NextMI.getOpcode() == AMDGPU::RETURN) {
- inst |= (((uint64_t)1) << 53);
- }
- EmitByte(INSTR_NATIVE);
- Emit(inst);
- break;
- }
- case AMDGPU::VTX_READ_PARAM_i32_eg:
- case AMDGPU::VTX_READ_PARAM_f32_eg:
- case AMDGPU::VTX_READ_GLOBAL_i32_eg:
- case AMDGPU::VTX_READ_GLOBAL_f32_eg:
- case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
- case AMDGPU::VTX_READ_GLOBAL_v4f32_eg:
- {
- uint64_t InstWord01 = getBinaryCodeForInstr(MI);
- uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
-
- EmitByte(INSTR_VTX);
- Emit(InstWord01);
- Emit(InstWord2);
- break;
- }
-
- default:
- EmitALUInstr(MI);
- break;
- }
- }
- }
- }
- return false;
-}
-
-void R600CodeEmitter::EmitALUInstr(MachineInstr &MI)
-{
-
- unsigned numOperands = MI.getNumExplicitOperands();
- if(MI.findFirstPredOperandIdx() > -1)
- numOperands--;
- if (TII->HasFlagOperand(MI))
- numOperands--;
-
- // Some instructions are just place holder instructions that represent
- // operations that the GPU does automatically. They should be ignored.
- if (TII->isPlaceHolderOpcode(MI.getOpcode())) {
- return;
- }
-
- if(MI.getOpcode() == AMDGPU::PRED_X)
- numOperands = 2;
-
- // XXX Check if instruction writes a result
- if (numOperands < 1) {
- return;
- }
- const MachineOperand dstOp = MI.getOperand(0);
-
- // Emit instruction type
- EmitByte(0);
-
- unsigned int opIndex;
- for (opIndex = 1; opIndex < numOperands; opIndex++) {
- // Literal constants are always stored as the last operand.
- if (MI.getOperand(opIndex).isImm() || MI.getOperand(opIndex).isFPImm()) {
- break;
- }
- EmitSrc(MI.getOperand(opIndex), opIndex);
- }
-
- // Emit zeros for unused sources
- for ( ; opIndex < 4; opIndex++) {
- EmitNullBytes(SRC_BYTE_COUNT);
- }
-
- EmitDst(dstOp);
-
- EmitALU(MI, numOperands - 1);
-}
-
-void R600CodeEmitter::EmitSrc(const MachineOperand & MO, unsigned SrcIdx)
-{
- const MachineInstr *MI = MO.getParent();
- uint32_t value = 0;
- // Emit the source select (2 bytes). For GPRs, this is the register index.
- // For other potential instruction operands, (e.g. constant registers) the
- // value of the source select is defined in the r600isa docs.
- if (MO.isReg()) {
- unsigned reg = MO.getReg();
- EmitTwoBytes(getHWReg(reg));
- if (reg == AMDGPU::ALU_LITERAL_X) {
- const MachineInstr * parent = MO.getParent();
- unsigned immOpIndex = parent->getNumExplicitOperands() - 1;
- MachineOperand immOp = parent->getOperand(immOpIndex);
- if (immOp.isFPImm()) {
- value = immOp.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue();
- } else {
- assert(immOp.isImm());
- value = immOp.getImm();
- }
- }
- } else {
- // XXX: Handle other operand types.
- EmitTwoBytes(0);
- }
-
- // Emit the source channel (1 byte)
- if (MO.isReg()) {
- EmitByte(TRI->getHWRegChan(MO.getReg()));
- } else {
- EmitByte(0);
- }
-
- // XXX: Emit isNegated (1 byte)
- if ((!(TII->IsFlagSet(*MI, SrcIdx, MO_FLAG_ABS)))
- && (TII->IsFlagSet(*MI, SrcIdx, MO_FLAG_NEG) ||
- (MO.isReg() &&
- (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
- EmitByte(1);
- } else {
- EmitByte(0);
- }
-
- // Emit isAbsolute (1 byte)
- if (TII->IsFlagSet(*MI, SrcIdx, MO_FLAG_ABS)) {
- EmitByte(1);
- } else {
- EmitByte(0);
- }
-
- // XXX: Emit relative addressing mode (1 byte)
- EmitByte(0);
-
- // Emit kc_bank, This will be adjusted later by r600_asm
- EmitByte(0);
-
- // Emit the literal value, if applicable (4 bytes).
- Emit(value);
-
-}
-
-void R600CodeEmitter::EmitDst(const MachineOperand & MO)
-{
- const MachineInstr *MI = MO.getParent();
- if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
- // Emit the destination register index (1 byte)
- EmitByte(getHWReg(MO.getReg()));
-
- // Emit the element of the destination register (1 byte)
- EmitByte(TRI->getHWRegChan(MO.getReg()));
-
- // Emit isClamped (1 byte)
- if (TII->IsFlagSet(*MI, 0, MO_FLAG_CLAMP)) {
- EmitByte(1);
- } else {
- EmitByte(0);
- }
-
- // Emit writemask (1 byte).
- if (TII->IsFlagSet(*MI, 0, MO_FLAG_MASK)) {
- EmitByte(0);
- } else {
- EmitByte(1);
- }
-
- // XXX: Emit relative addressing mode
- EmitByte(0);
- } else {
- // XXX: Handle other operand types. Are there any for destination regs?
- EmitNullBytes(DST_BYTE_COUNT);
- }
-}
-
-void R600CodeEmitter::EmitALU(MachineInstr &MI, unsigned numSrc)
-{
- // Emit the instruction (2 bytes)
- EmitTwoBytes(getBinaryCodeForInstr(MI));
-
- // Emit IsLast (for this instruction group) (1 byte)
- if (MI.isInsideBundle() && !TII->IsFlagSet(MI, 0, MO_FLAG_LAST)) {
- EmitByte(0);
- } else {
- EmitByte(1);
- }
-
- // Emit isOp3 (1 byte)
- if (numSrc == 3) {
- EmitByte(1);
- } else {
- EmitByte(0);
- }
-
- // XXX: Emit push modifier
- if(MI.getOperand(1).getTargetFlags() & MO_FLAG_PUSH) {
- EmitByte(1);
- } else {
- EmitByte(0);
- }
-
- // XXX: Emit predicate (1 byte)
- int predidx = MI.findFirstPredOperandIdx();
- if (predidx > -1)
- switch(MI.getOperand(predidx).getReg()) {
- case AMDGPU::PRED_SEL_ZERO:
- EmitByte(2);
- break;
- case AMDGPU::PRED_SEL_ONE:
- EmitByte(3);
- break;
- default:
- EmitByte(0);
- break;
- }
- else {
- EmitByte(0);
- }
-
-
- // XXX: Emit bank swizzle. (1 byte) Do we need this? It looks like
- // r600_asm.c sets it.
- EmitByte(0);
-
- // XXX: Emit bank_swizzle_force (1 byte) Not sure what this is for.
- EmitByte(0);
-
- // XXX: Emit OMOD (1 byte) Not implemented.
- EmitByte(0);
-
- // XXX: Emit index_mode. I think this is for indirect addressing, so we
- // don't need to worry about it.
- EmitByte(0);
-}
-
-void R600CodeEmitter::EmitTexInstr(MachineInstr &MI)
-{
-
- unsigned opcode = MI.getOpcode();
- bool hasOffsets = (opcode == AMDGPU::TEX_LD);
- unsigned op_offset = hasOffsets ? 3 : 0;
- int64_t sampler = MI.getOperand(op_offset+2).getImm();
- int64_t textureType = MI.getOperand(op_offset+3).getImm();
- unsigned srcSelect[4] = {0, 1, 2, 3};
-
- // Emit instruction type
- EmitByte(1);
-
- // Emit instruction
- EmitByte(getBinaryCodeForInstr(MI));
-
- // XXX: Emit resource id r600_shader.c uses sampler + 1. Why?
- EmitByte(sampler + 1 + 1);
-
- // Emit source register
- EmitByte(getHWReg(MI.getOperand(1).getReg()));
-
- // XXX: Emit src isRelativeAddress
- EmitByte(0);
-
- // Emit destination register
- EmitByte(getHWReg(MI.getOperand(0).getReg()));
-
- // XXX: Emit dst isRealtiveAddress
- EmitByte(0);
-
- // XXX: Emit dst select
- EmitByte(0); // X
- EmitByte(1); // Y
- EmitByte(2); // Z
- EmitByte(3); // W
-
- // XXX: Emit lod bias
- EmitByte(0);
-
- // XXX: Emit coord types
- unsigned coordType[4] = {1, 1, 1, 1};
-
- if (textureType == TEXTURE_RECT
- || textureType == TEXTURE_SHADOWRECT) {
- coordType[ELEMENT_X] = 0;
- coordType[ELEMENT_Y] = 0;
- }
-
- if (textureType == TEXTURE_1D_ARRAY
- || textureType == TEXTURE_SHADOW1D_ARRAY) {
- if (opcode == AMDGPU::TEX_SAMPLE_C_L || opcode == AMDGPU::TEX_SAMPLE_C_LB) {
- coordType[ELEMENT_Y] = 0;
- } else {
- coordType[ELEMENT_Z] = 0;
- srcSelect[ELEMENT_Z] = ELEMENT_Y;
- }
- } else if (textureType == TEXTURE_2D_ARRAY
- || textureType == TEXTURE_SHADOW2D_ARRAY) {
- coordType[ELEMENT_Z] = 0;
- }
-
- for (unsigned i = 0; i < 4; i++) {
- EmitByte(coordType[i]);
- }
-
- // XXX: Emit offsets
- if (hasOffsets)
- for (unsigned i = 2; i < 5; i++)
- EmitByte(MI.getOperand(i).getImm()<<1);
- else
- EmitNullBytes(3);
-
- // Emit sampler id
- EmitByte(sampler);
-
- // XXX:Emit source select
- if ((textureType == TEXTURE_SHADOW1D
- || textureType == TEXTURE_SHADOW2D
- || textureType == TEXTURE_SHADOWRECT
- || textureType == TEXTURE_SHADOW1D_ARRAY)
- && opcode != AMDGPU::TEX_SAMPLE_C_L
- && opcode != AMDGPU::TEX_SAMPLE_C_LB) {
- srcSelect[ELEMENT_W] = ELEMENT_Z;
- }
-
- for (unsigned i = 0; i < 4; i++) {
- EmitByte(srcSelect[i]);
- }
-}
-
-void R600CodeEmitter::EmitFCInstr(MachineInstr &MI)
-{
- // Emit instruction type
- EmitByte(INSTR_FC);
-
- // Emit SRC
- unsigned numOperands = MI.getNumOperands();
- if (numOperands > 0) {
- assert(numOperands == 1);
- EmitSrc(MI.getOperand(0), 0);
- } else {
- EmitNullBytes(SRC_BYTE_COUNT);
- }
-
- // Emit FC Instruction
- enum FCInstr instr;
- switch (MI.getOpcode()) {
- case AMDGPU::BREAK_LOGICALZ_f32:
- instr = FC_BREAK;
- break;
- case AMDGPU::BREAK_LOGICALNZ_f32:
- instr = FC_BREAK_NZ;
- break;
- case AMDGPU::BREAK_LOGICALNZ_i32:
- instr = FC_BREAK_NZ_INT;
- break;
- case AMDGPU::BREAK_LOGICALZ_i32:
- instr = FC_BREAK_Z_INT;
- break;
- case AMDGPU::CONTINUE_LOGICALNZ_f32:
- case AMDGPU::CONTINUE_LOGICALNZ_i32:
- instr = FC_CONTINUE;
- break;
- case AMDGPU::IF_LOGICALNZ_f32:
- instr = FC_IF;
- case AMDGPU::IF_LOGICALNZ_i32:
- instr = FC_IF_INT;
- break;
- case AMDGPU::IF_LOGICALZ_f32:
- abort();
- break;
- case AMDGPU::ELSE:
- instr = FC_ELSE;
- break;
- case AMDGPU::ENDIF:
- instr = FC_ENDIF;
- break;
- case AMDGPU::ENDLOOP:
- instr = FC_ENDLOOP;
- break;
- case AMDGPU::WHILELOOP:
- instr = FC_BGNLOOP;
- break;
- default:
- abort();
- break;
- }
- EmitByte(instr);
-}
-
-void R600CodeEmitter::EmitNullBytes(unsigned int byteCount)
-{
- for (unsigned int i = 0; i < byteCount; i++) {
- EmitByte(0);
- }
-}
-
-void R600CodeEmitter::EmitByte(unsigned int byte)
-{
- _OS.write((uint8_t) byte & 0xff);
-}
-void R600CodeEmitter::EmitTwoBytes(unsigned int bytes)
-{
- _OS.write((uint8_t) (bytes & 0xff));
- _OS.write((uint8_t) ((bytes >> 8) & 0xff));
-}
-
-void R600CodeEmitter::Emit(uint32_t value)
-{
- for (unsigned i = 0; i < 4; i++) {
- _OS.write((uint8_t) ((value >> (8 * i)) & 0xff));
- }
-}
-
-void R600CodeEmitter::Emit(uint64_t value)
-{
- for (unsigned i = 0; i < 8; i++) {
- EmitByte((value >> (8 * i)) & 0xff);
- }
-}
-
-unsigned R600CodeEmitter::getHWReg(unsigned regNo) const
-{
- unsigned HWReg;
-
- HWReg = TRI->getHWRegIndex(regNo);
- if (AMDGPU::R600_CReg32RegClass.contains(regNo)) {
- HWReg += 512;
- }
- return HWReg;
-}
-
-uint64_t R600CodeEmitter::getMachineOpValue(const MachineInstr &MI,
- const MachineOperand &MO) const
-{
- if (MO.isReg()) {
- return getHWReg(MO.getReg());
- } else {
- return MO.getImm();
- }
-}
-
-#include "AMDGPUGenCodeEmitter.inc"
-
--- /dev/null
+//===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+// Operand Flags
+#define MO_FLAG_CLAMP (1 << 0)
+#define MO_FLAG_NEG (1 << 1)
+#define MO_FLAG_ABS (1 << 2)
+#define MO_FLAG_MASK (1 << 3)
+#define MO_FLAG_PUSH (1 << 4)
+#define MO_FLAG_NOT_LAST (1 << 5)
+#define NUM_MO_FLAGS 6
+
+// Helper for finding getting the operand index for the instruction flags
+// operand.
+#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
+
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
+#include "R600Defines.h"
#include "R600InstrInfo.h"
#include "R600RegisterInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
}
// Set the IsLast bit
- Flags |= (Chan == 3 ? MO_FLAG_LAST : 0);
+ Flags |= (Chan != 3 ? MO_FLAG_NOT_LAST : 0);
// Add the new instruction
unsigned Opcode;
//===----------------------------------------------------------------------===//
#include "R600ISelLowering.h"
+#include "R600Defines.h"
#include "R600InstrInfo.h"
#include "R600MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "R600InstrInfo.h"
#include "AMDGPUTargetMachine.h"
#include "AMDGPUSubtarget.h"
+#include "R600Defines.h"
#include "R600RegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "AMDILUtilityFunctions.h"
}
}
-bool R600InstrInfo::isTexOp(unsigned opcode) const
-{
- switch(opcode) {
- default: return false;
- case AMDGPU::TEX_LD:
- case AMDGPU::TEX_GET_TEXTURE_RESINFO:
- case AMDGPU::TEX_SAMPLE:
- case AMDGPU::TEX_SAMPLE_C:
- case AMDGPU::TEX_SAMPLE_L:
- case AMDGPU::TEX_SAMPLE_C_L:
- case AMDGPU::TEX_SAMPLE_LB:
- case AMDGPU::TEX_SAMPLE_C_LB:
- case AMDGPU::TEX_SAMPLE_G:
- case AMDGPU::TEX_SAMPLE_C_G:
- case AMDGPU::TEX_GET_GRADIENTS_H:
- case AMDGPU::TEX_GET_GRADIENTS_V:
- case AMDGPU::TEX_SET_GRADIENTS_H:
- case AMDGPU::TEX_SET_GRADIENTS_V:
- return true;
- }
-}
-
bool R600InstrInfo::isReductionOp(unsigned opcode) const
{
switch(opcode) {
}
}
-
-bool R600InstrInfo::isFCOp(unsigned opcode) const
-{
- switch(opcode) {
- default: return false;
- case AMDGPU::BREAK_LOGICALZ_f32:
- case AMDGPU::BREAK_LOGICALNZ_i32:
- case AMDGPU::BREAK_LOGICALZ_i32:
- case AMDGPU::BREAK_LOGICALNZ_f32:
- case AMDGPU::CONTINUE_LOGICALNZ_f32:
- case AMDGPU::IF_LOGICALNZ_i32:
- case AMDGPU::IF_LOGICALZ_f32:
- case AMDGPU::ELSE:
- case AMDGPU::ENDIF:
- case AMDGPU::ENDLOOP:
- case AMDGPU::IF_LOGICALNZ_f32:
- case AMDGPU::WHILELOOP:
- return true;
- }
-}
-
DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const
{
// Instruction flag getters/setters
//===----------------------------------------------------------------------===//
-#define GET_FLAG_OPERAND_IDX(MI) (((MI).getDesc().TSFlags >> 7) & 0x3)
-
bool R600InstrInfo::HasFlagOperand(const MachineInstr &MI) const
{
- return GET_FLAG_OPERAND_IDX(MI) != 0;
+ return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
}
MachineOperand &R600InstrInfo::GetFlagOp(MachineInstr *MI) const
{
- unsigned FlagIndex = GET_FLAG_OPERAND_IDX(*MI);
+ unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
assert(FlagIndex != 0 &&
"Instruction flags not supported for this instruction");
MachineOperand &FlagOp = MI->getOperand(FlagIndex);
FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
}
-bool R600InstrInfo::IsFlagSet(const MachineInstr &MI, unsigned Operand,
- unsigned Flag) const
-{
- unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MI);
- if (FlagIndex == 0) {
- return false;
- }
- assert(MI.getOperand(FlagIndex).isImm());
- return !!((MI.getOperand(FlagIndex).getImm() >>
- (NUM_MO_FLAGS * Operand)) & Flag);
-}
-
void R600InstrInfo::ClearFlag(MachineInstr *MI, unsigned Operand,
unsigned Flag) const
{
bool isTrig(const MachineInstr &MI) const;
bool isPlaceHolderOpcode(unsigned opcode) const;
- bool isTexOp(unsigned opcode) const;
bool isReductionOp(unsigned opcode) const;
bool isCubeOp(unsigned opcode) const;
- bool isFCOp(unsigned opcode) const;
/// isVector - Vector instructions are instructions that must fill all
/// instruction slots within an instruction group.
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