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[ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.
author
Bradley Smith
<bradley.smith@arm.com>
Wed, 9 Apr 2014 14:43:27 +0000
(14:43 +0000)
committer
Bradley Smith
<bradley.smith@arm.com>
Wed, 9 Apr 2014 14:43:27 +0000
(14:43 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM64/ARM64InstrFormats.td
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diff --git
a/lib/Target/ARM64/ARM64InstrFormats.td
b/lib/Target/ARM64/ARM64InstrFormats.td
index
6b80754
..
f1981bf
100644
(file)
--- a/
lib/Target/ARM64/ARM64InstrFormats.td
+++ b/
lib/Target/ARM64/ARM64InstrFormats.td
@@
-3071,7
+3071,7
@@
class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
bits<5> Rd;
bits<5> Rn;
bits<6> scale;
- let Inst{30
} =
0;
+ let Inst{30
-29} = 0b0
0;
let Inst{28-24} = 0b11110;
let Inst{23-22} = type;
let Inst{21} = 0;