eliminated latch!! a big surgery is gonna come!!!

diff --git a/de1_nes/cpu/cpu_registers.vhd b/de1_nes/cpu/cpu_registers.vhd
index 7519078..6d25f14 100644 (file)
--- a/de1_nes/cpu/cpu_registers.vhd
+++ b/de1_nes/cpu/cpu_registers.vhd
@@ -90,28 +90,14 @@ entity data_bus_buffer is
             dsize : integer := 8
             );
     port (  
-    signal dbg_dbb_r     : out std_logic_vector (7 downto 0);
-    signal dbg_dbb_w     : out std_logic_vector (7 downto 0);
-
-            clk         : in std_logic;
-            r_nw        : in std_logic;
             int_oe_n    : in std_logic;
+            ext_oe_n    : in std_logic;
             int_dbus : inout std_logic_vector (dsize - 1 downto 0);
             ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
         );
 end data_bus_buffer;
 
 architecture rtl of data_bus_buffer is
-component data_latch
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk     : in std_logic;
-            d       : in std_logic_vector (dsize - 1 downto 0);
-            q       : out std_logic_vector (dsize - 1 downto 0)
-        );
-end component;
 
 component tri_state_buffer
     generic (
@@ -124,27 +110,13 @@ component tri_state_buffer
         );
 end component;
 
-signal rd_clk : std_logic;
-signal wr_clk : std_logic;
-signal read_buf : std_logic_vector (dsize - 1 downto 0);
-signal write_buf : std_logic_vector (dsize - 1 downto 0);
 begin
-    dbg_dbb_r <= read_buf;
-    dbg_dbb_w <= write_buf;
-    
-    rd_clk <= r_nw and clk;
-    wr_clk <= (not r_nw) and clk;
-
     --read from i/o to cpu
-    latch_r : data_latch generic map (dsize) 
-                    port map(rd_clk, ext_dbus, read_buf);
     read_tsb : tri_state_buffer generic map (dsize) 
-                    port map(int_oe_n, read_buf, int_dbus);
+                    port map(int_oe_n, ext_dbus, int_dbus);
     --write from cpu to io
-    latch_w : data_latch generic map (dsize) 
-                    port map(wr_clk, int_dbus, write_buf);
     write_tsb : tri_state_buffer generic map (dsize) 
-                    port map(r_nw, write_buf, ext_dbus);
+                    port map(ext_oe_n, int_dbus, ext_dbus);
 end rtl;
 
 ------------------------------------------

diff --git a/de1_nes/cpu/mos6502.vhd b/de1_nes/cpu/mos6502.vhd
index 6817bf5..f1dee14 100644 (file)
--- a/de1_nes/cpu/mos6502.vhd
+++ b/de1_nes/cpu/mos6502.vhd
@@ -10,17 +10,13 @@ entity mos6502 is
     signal dbg_int_d_bus    : out std_logic_vector(7 downto 0);\r
     signal dbg_exec_cycle   : out std_logic_vector (5 downto 0);\r
     signal dbg_ea_carry     : out std_logic;\r
-\r
---    signal dbg_index_bus    : out std_logic_vector(7 downto 0);\r
---    signal dbg_acc_bus      : out std_logic_vector(7 downto 0);\r
     signal dbg_status       : out std_logic_vector(7 downto 0);\r
     signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc       : out std_logic_vector(7 downto 0);\r
     signal dbg_dec_oe_n    : out std_logic;\r
     signal dbg_dec_val     : out std_logic_vector (7 downto 0);\r
     signal dbg_int_dbus    : out std_logic_vector (7 downto 0);\r
---    signal dbg_status_val    : out std_logic_vector (7 downto 0);\r
     signal dbg_stat_we_n    : out std_logic;\r
-    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : out std_logic_vector (7 downto 0);\r
+    signal dbg_idl_h, dbg_idl_l     : out std_logic_vector (7 downto 0);\r
 \r
             input_clk   : in std_logic; --phi0 input pin.
             rdy         : in std_logic;
@@ -179,12 +175,8 @@ component data_bus_buffer
             dsize : integer := 8
             );
     port (  
-    signal dbg_dbb_r     : out std_logic_vector (7 downto 0);\r
-    signal dbg_dbb_w     : out std_logic_vector (7 downto 0);\r
-\r
-            clk         : in std_logic;
-            r_nw        : in std_logic;
-            int_oe_n    : in std_logic;
+            int_oe_n    : in std_logic;\r
+            ext_oe_n    : in std_logic;\r
             int_dbus : inout std_logic_vector (dsize - 1 downto 0);
             ext_dbus : inout std_logic_vector (dsize - 1 downto 0)
         );
@@ -488,7 +480,7 @@ begin
 
     --io data buffer
     dbus_buf : data_bus_buffer generic map (dsize) 
-            port map(dbg_dbb_r, dbg_dbb_w, set_clk, dbuf_r_nw, dbuf_int_oe_n, int_d_bus, d_io);
+            port map(dbuf_int_oe_n, dbuf_r_nw, int_d_bus, d_io);
 
     --address operand data buffer.
     idl_l : input_data_latch generic map (dsize) 

diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd
index 5bc4609..66b1176 100644 (file)
--- a/de1_nes/de1_nes.vhd
+++ b/de1_nes/de1_nes.vhd
@@ -24,17 +24,11 @@ entity de1_nes is
     signal dbg_int_d_bus    : out std_logic_vector(7 downto 0);
     signal dbg_exec_cycle   : out std_logic_vector (5 downto 0);
     signal dbg_ea_carry     : out std_logic;
---    signal dbg_index_bus    : out std_logic_vector(7 downto 0);
---    signal dbg_acc_bus      : out std_logic_vector(7 downto 0);
     signal dbg_status       : out std_logic_vector(7 downto 0);
---    signal dbg_pcl, dbg_pch : out std_logic_vector(7 downto 0);
     signal dbg_sp, dbg_x, dbg_y, dbg_acc       : out std_logic_vector(7 downto 0);
     signal dbg_dec_oe_n    : out std_logic;
     signal dbg_dec_val     : out std_logic_vector (7 downto 0);
     signal dbg_int_dbus    : out std_logic_vector (7 downto 0);
---    signal dbg_status_val    : out std_logic_vector (7 downto 0);
---    signal dbg_stat_we_n    : out std_logic;
---    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : out std_logic_vector (7 downto 0);
 
 --ppu debug pins
     signal dbg_ppu_ce_n    : out std_logic;
@@ -79,7 +73,7 @@ architecture rtl of de1_nes is
     signal dbg_int_dbus    : out std_logic_vector (7 downto 0);
 --    signal dbg_status_val    : out std_logic_vector (7 downto 0);
     signal dbg_stat_we_n    : out std_logic;
-    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : out std_logic_vector (7 downto 0);
+    signal dbg_idl_h, dbg_idl_l     : out std_logic_vector (7 downto 0);
     
                 input_clk   : in std_logic; --phi0 input pin.
                 rdy         : in std_logic;
@@ -281,7 +275,7 @@ architecture rtl of de1_nes is
 --    signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0);
     signal dbg_pcl, dbg_pch : std_logic_vector(7 downto 0);
     signal dbg_stat_we_n    : std_logic;
-    signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w    : std_logic_vector (7 downto 0);
+    signal dbg_idl_h, dbg_idl_l     : std_logic_vector (7 downto 0);
 
     signal dbg_vga_clk                      : std_logic;
     signal dbg_ppu_addr_we_n                : std_logic;
@@ -341,7 +335,7 @@ begin
     dbg_int_dbus,
 --    dbg_status_val    ,
     dbg_stat_we_n    ,
-    dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w,
+    dbg_idl_h, dbg_idl_l,
 
                 cpu_clk, rdy,
                 rst_n, irq_n, nmi_n, dbe, r_nw, 

diff --git a/de1_nes/motonesfpga_common.vhd b/de1_nes/motonesfpga_common.vhd
index 22b3a99..5ad52ba 100644 (file)
--- a/de1_nes/motonesfpga_common.vhd
+++ b/de1_nes/motonesfpga_common.vhd
@@ -156,36 +156,6 @@ begin
 end rtl;
 
 ----------------------------------------
---- data latch declaration
-----------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity data_latch is 
-    generic (
-            dsize : integer := 8
-            );
-    port (  
-            clk     : in std_logic;
-            d       : in std_logic_vector (dsize - 1 downto 0);
-            q       : out std_logic_vector (dsize - 1 downto 0)
-        );
-end data_latch;
-
-architecture rtl of data_latch is
-begin
-
-    process (clk, d)
-    begin
-        if ( clk = '1') then
-            --latch only when clock is high
-            q <= d;
-        end if;
-    end process;
-end rtl;
-
-----------------------------------------
 --- tri-state buffer
 ----------------------------------------