int reg = irq / 32;
u32 val;
+ if (irq != 0)
+ return; /* Only IRQ 0 / the ENMI needs to be acked */
+
val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
writel(val | (1 << irq_off),
sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
static struct irq_chip sun4i_irq_chip = {
.name = "sun4i_irq",
- .irq_mask = sun4i_irq_mask,
- .irq_unmask = sun4i_irq_unmask,
-};
-
-/* IRQ 0 / the ENMI needs a late eoi call */
-static struct irq_chip sun4i_irq_chip_enmi = {
- .name = "sun4i_irq",
.irq_eoi = sun4i_irq_ack,
.irq_mask = sun4i_irq_mask,
.irq_unmask = sun4i_irq_unmask,
static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
- if (hw == 0)
- irq_set_chip_and_handler(virq, &sun4i_irq_chip_enmi,
- handle_fasteoi_irq);
- else
- irq_set_chip_and_handler(virq, &sun4i_irq_chip,
- handle_level_irq);
-
+ irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
return 0;