plt_w_n <= r_nw when plt_bus_ce_n = '0' else\r
'1';\r
plt_d_buf_w : tri_state_buffer generic map (dsize)\r
- port map (r_nw, oam_plt_data, plt_data);\r
+ port map (plt_w_n, oam_plt_data, plt_data);\r
plt_d_buf_r : tri_state_buffer generic map (dsize)\r
- port map (r_n, plt_data, oam_plt_data);\r
+ port map (plt_r_n, plt_data, oam_plt_data);\r
plt_ram_ctl : ram_ctrl\r
port map (mem_clk, plt_ram_ce_n_in, plt_r_n, plt_w_n, plt_ram_ce_n);\r
palette_inst : palette_ram generic map (5, dsize)\r