drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info

For consistency (and elegance!), add intel_device_info.has_rps.
The immediate boon is that RPS support is now emitted along the other
capabilities in the debug log and after errors.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419134836.5626-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 066fd2a..71612e7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2585,6 +2585,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RC6p(dev_priv)              (INTEL_INFO(dev_priv)->has_rc6p)
 #define HAS_RC6pp(dev_priv)             (false) /* HW was never validated */
 
+#define HAS_RPS(dev_priv)      (INTEL_INFO(dev_priv)->has_rps)
+
 #define HAS_CSR(dev_priv)      (INTEL_INFO(dev_priv)->display.has_csr)
 
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f893c2c..ffa2ee7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -370,6 +370,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
        .has_llc = 1, \
        .has_rc6 = 1, \
        .has_rc6p = 1, \
+       .has_rps = true, \
        .ppgtt_type = INTEL_PPGTT_ALIASING, \
        .ppgtt_size = 31, \
        I9XX_PIPE_OFFSETS, \
@@ -417,6 +418,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
        .has_llc = 1, \
        .has_rc6 = 1, \
        .has_rc6p = 1, \
+       .has_rps = true, \
        .ppgtt_type = INTEL_PPGTT_FULL, \
        .ppgtt_size = 31, \
        IVB_PIPE_OFFSETS, \
@@ -470,6 +472,7 @@ static const struct intel_device_info intel_valleyview_info = {
        .num_pipes = 2,
        .has_runtime_pm = 1,
        .has_rc6 = 1,
+       .has_rps = true,
        .display.has_gmch = 1,
        .display.has_hotplug = 1,
        .ppgtt_type = INTEL_PPGTT_FULL,
@@ -565,6 +568,7 @@ static const struct intel_device_info intel_cherryview_info = {
        .has_64bit_reloc = 1,
        .has_runtime_pm = 1,
        .has_rc6 = 1,
+       .has_rps = true,
        .has_logical_ring_contexts = 1,
        .display.has_gmch = 1,
        .ppgtt_type = INTEL_PPGTT_FULL,
@@ -640,6 +644,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
        .has_runtime_pm = 1, \
        .display.has_csr = 1, \
        .has_rc6 = 1, \
+       .has_rps = true, \
        .display.has_dp_mst = 1, \
        .has_logical_ring_contexts = 1, \
        .has_logical_ring_preemption = 1, \

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0e579f1..7a2f14e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -118,6 +118,7 @@ enum intel_ppgtt_type {
        func(has_pooled_eu); \
        func(has_rc6); \
        func(has_rc6p); \
+       func(has_rps); \
        func(has_runtime_pm); \
        func(has_snoop); \
        func(has_coherent_ggtt); \

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 87f6fc6..7aa9a8c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7013,8 +7013,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
        struct intel_device_info *info = mkwrite_device_info(i915);
 
        /* Powersaving is controlled by the host when inside a VM */
-       if (intel_vgpu_active(i915))
+       if (intel_vgpu_active(i915)) {
                info->has_rc6 = 0;
+               info->has_rps = false;
+       }
 
        if (info->has_rc6 &&
            IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
@@ -8716,7 +8718,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 
        if (HAS_RC6(dev_priv))
                intel_enable_rc6(dev_priv);
-       intel_enable_rps(dev_priv);
+       if (HAS_RPS(dev_priv))
+               intel_enable_rps(dev_priv);
        if (HAS_LLC(dev_priv))
                intel_enable_llc_pstate(dev_priv);