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drm/amd/pm: correct Renoir UMD Stable Pstate settings
authorEvan Quan <evan.quan@amd.com>
Fri, 4 Sep 2020 08:08:15 +0000 (16:08 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 17 Sep 2020 21:48:58 +0000 (17:48 -0400)
Update the UMD stable Pstate settings with correct clocks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.h

index 63c72e3..55a254b 100644 (file)
@@ -832,9 +832,59 @@ static int renoir_set_performance_level(struct smu_context *smu,
                ret = renoir_force_dpm_limit_value(smu, false);
                break;
        case AMD_DPM_FORCED_LEVEL_AUTO:
-       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
                ret = renoir_unforce_dpm_levels(smu);
                break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetHardMinGfxClk,
+                                                     RENOIR_UMD_PSTATE_GFXCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetHardMinFclkByFreq,
+                                                     RENOIR_UMD_PSTATE_FCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetHardMinSocclkByFreq,
+                                                     RENOIR_UMD_PSTATE_SOCCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetHardMinVcn,
+                                                     RENOIR_UMD_PSTATE_VCNCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetSoftMaxGfxClk,
+                                                     RENOIR_UMD_PSTATE_GFXCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetSoftMaxFclkByFreq,
+                                                     RENOIR_UMD_PSTATE_FCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetSoftMaxSocclkByFreq,
+                                                     RENOIR_UMD_PSTATE_SOCCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_SetSoftMaxVcn,
+                                                     RENOIR_UMD_PSTATE_VCNCLK,
+                                                     NULL);
+               if (ret)
+                       return ret;
+               break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
                ret = renoir_get_profiling_clk_mask(smu, level,
index 8c3f004..11c3c22 100644 (file)
@@ -29,5 +29,6 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
 #define RENOIR_UMD_PSTATE_GFXCLK       700
 #define RENOIR_UMD_PSTATE_SOCCLK       678
 #define RENOIR_UMD_PSTATE_FCLK         800
+#define RENOIR_UMD_PSTATE_VCNCLK       0x022D01D8
 
 #endif