drm/msm/sde: move current performance setting to crtc object

Current performance setting is maintained in crtc state, and its
update is synchronized to commit cycle. However, the setting may be
committed to clock and bandwidth driver out of sync with respect to
commit cycle, e.g. update at end of frame while another commit is
validating. As a result, requested settings may be missed and result
in older settings being used. Move current performance setting
to crtc object, from crtc state, so it can be updated at the
same time as the setting is committed to clock and bandwidth
driver.

CRs-Fixed: 2048612
Change-Id: I0c3047e8e806460105eaba5d46145798bd98d721
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>

diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.c b/drivers/gpu/drm/msm/sde/sde_core_perf.c
index 4d98b89..8c312b7 100644 (file)
--- a/drivers/gpu/drm/msm/sde/sde_core_perf.c
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.c
@@ -127,8 +127,6 @@ int sde_core_perf_crtc_check(struct drm_crtc *crtc,
 
        sde_cstate = to_sde_crtc_state(state);
 
-       /* swap state and obtain new values */
-       sde_cstate->cur_perf = sde_cstate->new_perf;
        _sde_core_perf_calc_crtc(crtc, state, &sde_cstate->new_perf);
 
        bw_sum_of_intfs = sde_cstate->new_perf.bw_ctl;
@@ -155,11 +153,9 @@ int sde_core_perf_crtc_check(struct drm_crtc *crtc,
        SDE_DEBUG("final threshold bw limit = %d\n", threshold);
 
        if (!threshold) {
-               sde_cstate->new_perf = sde_cstate->cur_perf;
                SDE_ERROR("no bandwidth limits specified\n");
                return -E2BIG;
        } else if (bw > threshold) {
-               sde_cstate->new_perf = sde_cstate->cur_perf;
                SDE_DEBUG("exceeds bandwidth: %ukb > %ukb\n", bw, threshold);
                return -E2BIG;
        }
@@ -258,6 +254,7 @@ static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms,
 void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
 {
        struct drm_crtc *tmp_crtc;
+       struct sde_crtc *sde_crtc;
        struct sde_crtc_state *sde_cstate;
        struct sde_kms *kms;
 
@@ -272,6 +269,7 @@ void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
                return;
        }
 
+       sde_crtc = to_sde_crtc(crtc);
        sde_cstate = to_sde_crtc_state(crtc->state);
 
        /* only do this for command panel or writeback */
@@ -294,8 +292,7 @@ void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
        /* Release the bandwidth */
        if (kms->perf.enable_bw_release) {
                trace_sde_cmd_release_bw(crtc->base.id);
-               sde_cstate->cur_perf.bw_ctl = 0;
-               sde_cstate->new_perf.bw_ctl = 0;
+               sde_crtc->cur_perf.bw_ctl = 0;
                SDE_DEBUG("Release BW crtc=%d\n", crtc->base.id);
                _sde_core_perf_crtc_update_bus(kms, crtc, 0);
        }
@@ -362,7 +359,7 @@ void sde_core_perf_crtc_update(struct drm_crtc *crtc,
 
        SDE_ATRACE_BEGIN(__func__);
 
-       old = &sde_cstate->cur_perf;
+       old = &sde_crtc->cur_perf;
        new = &sde_cstate->new_perf;
 
        if (_sde_core_perf_crtc_is_power_on(crtc) && !stop_req) {

diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index f66c135..2a31bc7 100644 (file)
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -1888,15 +1888,18 @@ static const struct file_operations __prefix ## _fops = {               \
 static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
 {
        struct drm_crtc *crtc = (struct drm_crtc *) s->private;
+       struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
        struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
 
        seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
        seq_printf(s, "is_rt: %d\n", cstate->is_rt);
        seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc));
-       seq_printf(s, "bw_ctl: %llu\n", cstate->cur_perf.bw_ctl);
-       seq_printf(s, "core_clk_rate: %u\n", cstate->cur_perf.core_clk_rate);
+
+       seq_printf(s, "bw_ctl: %llu\n", sde_crtc->cur_perf.bw_ctl);
+       seq_printf(s, "core_clk_rate: %u\n",
+                       sde_crtc->cur_perf.core_clk_rate);
        seq_printf(s, "max_per_pipe_ib: %llu\n",
-                       cstate->cur_perf.max_per_pipe_ib);
+                       sde_crtc->cur_perf.max_per_pipe_ib);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 0eed615..531b790 100644 (file)
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -95,6 +95,7 @@ struct sde_crtc_frame_event {
  * @frame_event_list : available frame event list
  * @pending       : Whether any page-flip events are pending signal
  * @spin_lock     : spin lock for frame event, transaction status, etc...
+ * @cur_perf      : current performance committed to clock/bandwidth driver
  */
 struct sde_crtc {
        struct drm_crtc base;
@@ -134,6 +135,8 @@ struct sde_crtc {
        struct sde_crtc_frame_event frame_events[SDE_CRTC_FRAME_EVENT_SIZE];
        struct list_head frame_event_list;
        spinlock_t spin_lock;
+
+       struct sde_core_perf_params cur_perf;
 };
 
 #define to_sde_crtc(x) container_of(x, struct sde_crtc, base)
@@ -148,6 +151,7 @@ struct sde_crtc {
  * @property_values: Current crtc property values
  * @input_fence_timeout_ns : Cached input fence timeout, in ns
  * @property_blobs: Reference pointers for blob properties
+ * @new_perf: new performance state being requested
  */
 struct sde_crtc_state {
        struct drm_crtc_state base;
@@ -161,7 +165,6 @@ struct sde_crtc_state {
        uint64_t input_fence_timeout_ns;
        struct drm_property_blob *property_blobs[CRTC_PROP_COUNT];
 
-       struct sde_core_perf_params cur_perf;
        struct sde_core_perf_params new_perf;
 };