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drm/amdkfd: report pcie bandwidth to the kfd
authorJonathan Kim <jonathan.kim@amd.com>
Wed, 2 Jun 2021 13:46:16 +0000 (09:46 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 23 Jul 2021 14:07:59 +0000 (10:07 -0400)
Similar to xGMI reporting the min/max bandwidth between direct peers, PCIe
will report the min/max bandwidth to the KFD.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
drivers/gpu/drm/amd/amdkfd/kfd_crat.c

index 801403d..7b46ba5 100644 (file)
@@ -21,6 +21,7 @@
  */
 
 #include "amdgpu_amdkfd.h"
+#include "amd_pcie.h"
 #include "amd_shared.h"
 
 #include "amdgpu.h"
@@ -577,6 +578,64 @@ int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev
        return (num_links * 16 * 25000)/BITS_PER_BYTE;
 }
 
+int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)dev;
+       int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
+                                                       fls(adev->pm.pcie_mlw_mask)) - 1;
+       int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
+                                               CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
+                                       fls(adev->pm.pcie_gen_mask &
+                                               CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
+       uint32_t num_lanes_mask = 1 << num_lanes_shift;
+       uint32_t gen_speed_mask = 1 << gen_speed_shift;
+       int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
+
+       switch (num_lanes_mask) {
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
+               num_lanes_factor = 1;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
+               num_lanes_factor = 2;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
+               num_lanes_factor = 4;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
+               num_lanes_factor = 8;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
+               num_lanes_factor = 12;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
+               num_lanes_factor = 16;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
+               num_lanes_factor = 32;
+               break;
+       }
+
+       switch (gen_speed_mask) {
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
+               gen_speed_mbits_factor = 2500;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
+               gen_speed_mbits_factor = 5000;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
+               gen_speed_mbits_factor = 8000;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
+               gen_speed_mbits_factor = 16000;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
+               gen_speed_mbits_factor = 32000;
+               break;
+       }
+
+       return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
+}
+
 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
index 9b98ce2..a8b05c6 100644 (file)
@@ -227,6 +227,7 @@ uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd);
 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min);
+int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min);
 
 /* Read user wptr from a specified user address space with page fault
  * disabled. The memory must be pinned and mapped to the hardware when
index 40ce623..eada22b 100644 (file)
@@ -1998,6 +1998,10 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
                }
        } else {
                sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
+               sub_type_hdr->minimum_bandwidth_mbs =
+                               amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->kgd, true);
+               sub_type_hdr->maximum_bandwidth_mbs =
+                               amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->kgd, false);
        }
 
        sub_type_hdr->proximity_domain_from = proximity_domain;