ASoC: fsl_sai: Replace synchronous check with fsl_sai_dir_is_synced

As new function fsl_sai_dir_is_synced is included for checking if
stream is synced by the opposite stream, then replace the existing
synchronous checking with this new function.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20200805063413.4610-4-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 334090d..f6969a5 100644 (file)
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -350,6 +350,8 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
        unsigned int ofs = sai->soc_data->reg_offset;
        unsigned long clk_rate;
        u32 savediv = 0, ratio, savesub = freq;
+       int adir = tx ? RX : TX;
+       int dir = tx ? TX : RX;
        u32 id;
        int ret = 0;
 
@@ -408,19 +410,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
         * 4) For Tx and Rx are both Synchronous with another SAI, we just
         *    ignore it.
         */
-       if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
-           (!tx && !sai->synchronous[RX])) {
-               regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
+       if (fsl_sai_dir_is_synced(sai, adir)) {
+               regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
                                   FSL_SAI_CR2_MSEL_MASK,
                                   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
-               regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
+               regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
                                   FSL_SAI_CR2_DIV_MASK, savediv - 1);
-       } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
-                  (tx && !sai->synchronous[TX])) {
-               regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
+       } else if (!sai->synchronous[dir]) {
+               regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
                                   FSL_SAI_CR2_MSEL_MASK,
                                   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
-               regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
+               regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
                                   FSL_SAI_CR2_DIV_MASK, savediv - 1);
        }
 
@@ -442,6 +442,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
        u32 val_cr4 = 0, val_cr5 = 0;
        u32 slots = (channels == 1) ? 2 : channels;
        u32 slot_width = word_width;
+       int adir = tx ? RX : TX;
        int ret;
 
        if (sai->slots)
@@ -491,22 +492,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
         * RCR5(TCR5) for playback(capture), or there will be sync error.
         */
 
-       if (!sai->is_slave_mode) {
-               if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
-                       regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
-                               FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
-                               val_cr4);
-                       regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
-                               FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
-                               FSL_SAI_CR5_FBT_MASK, val_cr5);
-               } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
-                       regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
-                               FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
-                               val_cr4);
-                       regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
-                               FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
-                               FSL_SAI_CR5_FBT_MASK, val_cr5);
-               }
+       if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
+               regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
+                                  FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+                                  val_cr4);
+               regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
+                                  FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
+                                  FSL_SAI_CR5_FBT_MASK, val_cr5);
        }
 
        regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),