[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cpp

Making sure that an instruction has fewer operands than required, then
attempting to access one out of range is going to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316785 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonConstExtenders.cpp b/lib/Target/Hexagon/HexagonConstExtenders.cpp
index 40e1145..1f4304f 100644 (file)
--- a/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -1759,7 +1759,7 @@ bool HCE::replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI) {
     // Update offsets of the def's uses.
     for (std::pair<MachineInstr*,unsigned> P : RegOps) {
       unsigned J = P.second;
-      assert(P.first->getNumOperands() < J+1 &&
+      assert(P.first->getNumOperands() > J+1 &&
              P.first->getOperand(J+1).isImm());
       MachineOperand &ImmOp = P.first->getOperand(J+1);
       ImmOp.setImm(ImmOp.getImm() + Diff);

diff --git a/test/CodeGen/Hexagon/cext-opt-numops.mir b/test/CodeGen/Hexagon/cext-opt-numops.mir
new file mode 100644 (file)
index 0000000..03d6408
--- /dev/null
+++ b/test/CodeGen/Hexagon/cext-opt-numops.mir
@@ -0,0 +1,45 @@
+# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s
+
+# An incorrect assertion was triggered on this code, while attempting to
+# perform a valid transformation.
+
+# CHECK: PS_jmpret
+
+--- |
+  define void @fred() { ret void }
+
+  @array = global [1024 x i8] zeroinitializer, align 8
+...
+
+---
+name: fred
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: intregs }
+  - { id: 1, class: intregs }
+  - { id: 2, class: intregs }
+  - { id: 3, class: predregs }
+  - { id: 4, class: intregs }
+  - { id: 5, class: intregs }
+  - { id: 6, class: intregs }
+  - { id: 7, class: intregs }
+  - { id: 8, class: intregs }
+  - { id: 9, class: intregs }
+
+body: |
+  bb.0:
+    liveins: %r0, %r1
+      %0 = COPY %r1
+      %1 = COPY %r0
+      %2 = A2_tfrsi @array
+      %3 = IMPLICIT_DEF
+      %4 = A2_tfrsi @array+424
+      %5 = M2_macsip %0, %1, 5
+      %6 = A2_addi %2, 704
+      %7 = A2_tfrsi 0
+      S4_pstorerif_rr %3, %6, %5, 2, %7
+      %8 = A2_tfrsi @array+144
+      %9 = C2_mux %3, %4, %8
+      S4_storeiri_io %9, 0, 0
+      PS_jmpret %r31, implicit-def %pc
+...