arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes

IPQ8074 PCIe PHY nodes are broken in the many ways:

- '#address-cells', '#size-cells' and 'ranges' are missing.
- Child phy/lane node is missing, and the child properties like
  '#phy-cells' and 'clocks' are mistakenly put into parent node.
- The clocks properties for parent node are missing.

Fix them to get the nodes comply with the bindings schema.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 3e30e1a..6c6a0f8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -174,34 +174,60 @@
                        status = "disabled";
                };
 
-               pcie_phy0: phy@86000 {
+               pcie_qmp0: phy@86000 {
                        compatible = "qcom,ipq8074-qmp-pcie-phy";
                        reg = <0x00086000 0x1000>;
-                       #phy-cells = <0>;
-                       clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-                       clock-names = "pipe_clk";
-                       clock-output-names = "pcie20_phy0_pipe_clk";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
 
+                       clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+                               <&gcc GCC_PCIE0_AHB_CLK>;
+                       clock-names = "aux", "cfg_ahb";
                        resets = <&gcc GCC_PCIE0_PHY_BCR>,
                                <&gcc GCC_PCIE0PHY_PHY_BCR>;
                        reset-names = "phy",
                                      "common";
                        status = "disabled";
+
+                       pcie_phy0: phy@86200 {
+                               reg = <0x86200 0x16c>,
+                                     <0x86400 0x200>,
+                                     <0x86800 0x4f4>;
+                               #phy-cells = <0>;
+                               #clock-cells = <0>;
+                               clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+                               clock-names = "pipe0";
+                               clock-output-names = "pcie_0_pipe_clk";
+                       };
                };
 
-               pcie_phy1: phy@8e000 {
+               pcie_qmp1: phy@8e000 {
                        compatible = "qcom,ipq8074-qmp-pcie-phy";
                        reg = <0x0008e000 0x1000>;
-                       #phy-cells = <0>;
-                       clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-                       clock-names = "pipe_clk";
-                       clock-output-names = "pcie20_phy1_pipe_clk";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
 
+                       clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+                               <&gcc GCC_PCIE1_AHB_CLK>;
+                       clock-names = "aux", "cfg_ahb";
                        resets = <&gcc GCC_PCIE1_PHY_BCR>,
                                <&gcc GCC_PCIE1PHY_PHY_BCR>;
                        reset-names = "phy",
                                      "common";
                        status = "disabled";
+
+                       pcie_phy1: phy@8e200 {
+                               reg = <0x8e200 0x16c>,
+                                     <0x8e400 0x200>,
+                                     <0x8e800 0x4f4>;
+                               #phy-cells = <0>;
+                               #clock-cells = <0>;
+                               clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+                               clock-names = "pipe0";
+                               clock-output-names = "pcie_1_pipe_clk";
+                       };
                };
 
                prng: rng@e3000 {