static inline enum dsi_physical_lane_id mdss_dsi_logical_to_physical_lane(
struct mdss_dsi_ctrl_pdata *ctrl, enum dsi_logical_lane_id id)
{
+ int i;
+
if (id >= DSI_LOGICAL_LANE_MAX)
return DSI_PHYSICAL_LANE_INVALID;
- return ctrl->lane_map[id];
+ for (i = DSI_LOGICAL_LANE_0; i < DSI_LOGICAL_LANE_MAX; i++) {
+ if (BIT(i) == ctrl->lane_map[id])
+ break;
+ }
+
+ return i;
}
#endif /* MDSS_DSI_H */
}
}
+static void mdss_dsi_phy_v3_config_lpcdrx(struct mdss_dsi_ctrl_pdata *ctrl,
+ bool enable)
+{
+ struct mdss_dsi_phy_ctrl *pd =
+ &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
+ enum dsi_physical_lane_id phy_lane_0 =
+ mdss_dsi_logical_to_physical_lane(ctrl, DSI_LOGICAL_LANE_0);
+
+ /*
+ * LPRX and CDRX need to enabled only for physical data lane
+ * corresponding to the logical data lane 0
+ */
+ if (enable)
+ DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(phy_lane_0),
+ pd->strength[(phy_lane_0 * 2) + 1]);
+ else
+ DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(phy_lane_0), 0);
+}
+
static void mdss_dsi_phy_v3_config_lane_settings(
struct mdss_dsi_ctrl_pdata *ctrl)
{
for (i = 0; i < 5; i++) {
DSI_PHY_W32(ctrl->phy_io.base, LNX_LPTX_STR_CTRL(i),
pd->strength[(i * 2)]);
- DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(i),
- pd->strength[(i * 2) + 1]);
+ /*
+ * Disable LPRX and CDRX for all lanes. And later on, it will
+ * be only enabled for the physical data lane corresponding
+ * to the logical data lane 0
+ */
+ DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(i), 0);
+
DSI_PHY_W32(ctrl->phy_io.base, LNX_HSTX_STR_CTRL(i), 0x88);
DSI_PHY_W32(ctrl->phy_io.base, LNX_PIN_SWAP(i), 0x0);
}
+ mdss_dsi_phy_v3_config_lpcdrx(ctrl, true);
/* Other settings */
for (i = 0; i < 5; i++) {
if (mdss_dsi_phy_v3_is_pll_on(ctrl))
pr_warn("Disabling phy with PLL still enabled\n");
+ mdss_dsi_phy_v3_config_lpcdrx(ctrl, false);
mdss_dsi_phy_v3_lanes_disable(ctrl);
/* Turn off all PHY blocks */