drm/i915/chv: Add new workarounds for chv

+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv

For: VIZ-4090
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d43fa0e..97d3479 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5131,6 +5131,7 @@ enum punit_power_well {
 /* GEN8 chicken */
 #define HDC_CHICKEN0                           0x7300
 #define  HDC_FORCE_NON_COHERENT                        (1<<4)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
 
 /* WaCatErrorRejectionIssue */

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1df79a9..a09aae7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -793,6 +793,16 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
                          STALL_DOP_GATING_DISABLE);
 
+       /* Use Force Non-Coherent whenever executing a 3D context. This is a
+        * workaround for a possible hang in the unlikely event a TLB
+        * invalidation occurs during a PSD flush.
+        */
+       /* WaForceEnableNonCoherent:chv */
+       /* WaHdcDisableFetchWhenMasked:chv */
+       WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                         HDC_FORCE_NON_COHERENT |
+                         HDC_DONOT_FETCH_MEM_WHEN_MASKED);
+
        return 0;
 }