drm/amd/display: BIOS LTTPR Caps Interface

[WHY]
Some platforms will have LTTPR capabilities forced on by VBIOS flags;
the functions added here will access those flags.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index b208f06..2ee0c6f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -916,6 +916,143 @@ static enum bp_result bios_parser_get_soc_bb_info(
        return result;
 }
 
+static enum bp_result get_lttpr_caps_v4_1(
+       struct bios_parser *bp,
+       uint8_t *dce_caps)
+{
+       enum bp_result result = BP_RESULT_OK;
+       struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
+
+       if (!dce_caps)
+               return BP_RESULT_BADINPUT;
+
+       if (!DATA_TABLES(dce_info))
+               return BP_RESULT_BADBIOSTABLE;
+
+       disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
+                                                       DATA_TABLES(dce_info));
+
+       if (!disp_cntl_tbl)
+               return BP_RESULT_BADBIOSTABLE;
+
+       *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+       return result;
+}
+
+static enum bp_result get_lttpr_caps_v4_2(
+       struct bios_parser *bp,
+       uint8_t *dce_caps)
+{
+       enum bp_result result = BP_RESULT_OK;
+       struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
+
+       if (!dce_caps)
+               return BP_RESULT_BADINPUT;
+
+       if (!DATA_TABLES(dce_info))
+               return BP_RESULT_BADBIOSTABLE;
+
+       disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
+                                                       DATA_TABLES(dce_info));
+
+       if (!disp_cntl_tbl)
+               return BP_RESULT_BADBIOSTABLE;
+
+       *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+       return result;
+}
+
+static enum bp_result get_lttpr_caps_v4_3(
+       struct bios_parser *bp,
+       uint8_t *dce_caps)
+{
+       enum bp_result result = BP_RESULT_OK;
+       struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
+
+       if (!dce_caps)
+               return BP_RESULT_BADINPUT;
+
+       if (!DATA_TABLES(dce_info))
+               return BP_RESULT_BADBIOSTABLE;
+
+       disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
+                                                       DATA_TABLES(dce_info));
+
+       if (!disp_cntl_tbl)
+               return BP_RESULT_BADBIOSTABLE;
+
+       *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+       return result;
+}
+
+static enum bp_result get_lttpr_caps_v4_4(
+       struct bios_parser *bp,
+       uint8_t *dce_caps)
+{
+       enum bp_result result = BP_RESULT_OK;
+       struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
+
+       if (!dce_caps)
+               return BP_RESULT_BADINPUT;
+
+       if (!DATA_TABLES(dce_info))
+               return BP_RESULT_BADBIOSTABLE;
+
+       disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
+                                                       DATA_TABLES(dce_info));
+
+       if (!disp_cntl_tbl)
+               return BP_RESULT_BADBIOSTABLE;
+
+       *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+       return result;
+}
+
+static enum bp_result bios_parser_get_lttpr_caps(
+       struct dc_bios *dcb,
+       uint8_t *dce_caps)
+{
+       struct bios_parser *bp = BP_FROM_DCB(dcb);
+       enum bp_result result = BP_RESULT_UNSUPPORTED;
+       struct atom_common_table_header *header;
+       struct atom_data_revision tbl_revision;
+
+       if (!DATA_TABLES(dce_info))
+               return BP_RESULT_UNSUPPORTED;
+
+       header = GET_IMAGE(struct atom_common_table_header,
+                                               DATA_TABLES(dce_info));
+       get_atom_data_table_revision(header, &tbl_revision);
+       switch (tbl_revision.major) {
+       case 4:
+               switch (tbl_revision.minor) {
+               case 1:
+                       result = get_lttpr_caps_v4_1(bp, dce_caps);
+                       break;
+               case 2:
+                       result = get_lttpr_caps_v4_2(bp, dce_caps);
+                       break;
+               case 3:
+                       result = get_lttpr_caps_v4_3(bp, dce_caps);
+                       break;
+               case 4:
+                       result = get_lttpr_caps_v4_4(bp, dce_caps);
+                       break;
+               default:
+                       break;
+               }
+               break;
+       default:
+               break;
+       }
+
+       return result;
+}
+
 static enum bp_result get_embedded_panel_info_v2_1(
                struct bios_parser *bp,
                struct embedded_panel_info *info)
@@ -2531,6 +2668,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
        .get_soc_bb_info = bios_parser_get_soc_bb_info,
 
        .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
+
+       .get_lttpr_caps = bios_parser_get_lttpr_caps,
 };
 
 static bool bios_parser2_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 86ab8f1..1b957c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -150,6 +150,9 @@ struct dc_vbios_funcs {
                        struct dc_bios *dcb,
                        struct graphics_object_id object_id,
                        struct bp_disp_connector_caps_info *info);
+       enum bp_result (*get_lttpr_caps)(
+                       struct dc_bios *dcb,
+                       uint8_t *dce_caps);
 };
 
 struct bios_registers {

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 58364a8..82b3cd8 100644 (file)
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -981,6 +981,40 @@ struct atom_display_controller_info_v4_2
   uint8_t  reserved3[8];
 };
 
+struct atom_display_controller_info_v4_3
+{
+  struct  atom_common_table_header  table_header;
+  uint32_t display_caps;
+  uint32_t bootup_dispclk_10khz;
+  uint16_t dce_refclk_10khz;
+  uint16_t i2c_engine_refclk_10khz;
+  uint16_t dvi_ss_percentage;       // in unit of 0.001%
+  uint16_t dvi_ss_rate_10hz;
+  uint16_t hdmi_ss_percentage;      // in unit of 0.001%
+  uint16_t hdmi_ss_rate_10hz;
+  uint16_t dp_ss_percentage;        // in unit of 0.001%
+  uint16_t dp_ss_rate_10hz;
+  uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
+  uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
+  uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
+  uint8_t  ss_reserved;
+  uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
+  uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
+  uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+  uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+  uint16_t dpphy_refclk_10khz;
+  uint16_t reserved2;
+  uint8_t  dcnip_min_ver;
+  uint8_t  dcnip_max_ver;
+  uint8_t  max_disp_pipe_num;
+  uint8_t  max_vbios_active_disp_pipe_num;
+  uint8_t  max_ppll_num;
+  uint8_t  max_disp_phy_num;
+  uint8_t  max_aux_pairs;
+  uint8_t  remotedisplayconfig;
+  uint8_t  reserved3[8];
+};
+
 struct atom_display_controller_info_v4_4 {
        struct atom_common_table_header table_header;
        uint32_t display_caps;
@@ -1043,7 +1077,8 @@ enum dce_info_caps_def
   DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2      =0x04,
   // only for VBIOS
   DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING   =0x08,
-
+  // only for VBIOS
+  DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE    =0x20,
 };
 
 /*