Merge branch 'fixes' into next

Merge our fixes branch from the 4.16 cycle.

There were a number of important fixes merged, in particular some Power9
workarounds that we want in next for testing purposes. There's also been
some conflicting changes in the CPU features code which are best merged
and tested before going upstream.

diff --cc arch/powerpc/include/asm/book3s/64/mmu.h
Simple merge

diff --cc arch/powerpc/include/asm/cputable.h
index 734ff97,2e2bacb..66eba1e
--- 1/arch/powerpc/include/asm/cputable.h
--- 2/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@@ -181,40 -174,38 +181,41 @@@ static inline void cpu_feature_keys_ini
  #define LONG_ASM_CONST(x)             0
  #endif
  
 -#define CPU_FTR_HVMODE                        LONG_ASM_CONST(0x0000000100000000)
 -#define CPU_FTR_ARCH_201              LONG_ASM_CONST(0x0000000200000000)
 -#define CPU_FTR_ARCH_206              LONG_ASM_CONST(0x0000000400000000)
 -#define CPU_FTR_ARCH_207S             LONG_ASM_CONST(0x0000000800000000)
 -#define CPU_FTR_ARCH_300              LONG_ASM_CONST(0x0000001000000000)
 -#define CPU_FTR_MMCRA                 LONG_ASM_CONST(0x0000002000000000)
 -#define CPU_FTR_CTRL                  LONG_ASM_CONST(0x0000004000000000)
 -#define CPU_FTR_SMT                   LONG_ASM_CONST(0x0000008000000000)
 -#define CPU_FTR_PAUSE_ZERO            LONG_ASM_CONST(0x0000010000000000)
 -#define CPU_FTR_PURR                  LONG_ASM_CONST(0x0000020000000000)
 -#define CPU_FTR_CELL_TB_BUG           LONG_ASM_CONST(0x0000040000000000)
 -#define CPU_FTR_SPURR                 LONG_ASM_CONST(0x0000080000000000)
 -#define CPU_FTR_DSCR                  LONG_ASM_CONST(0x0000100000000000)
 -#define CPU_FTR_VSX                   LONG_ASM_CONST(0x0000200000000000)
 -#define CPU_FTR_SAO                   LONG_ASM_CONST(0x0000400000000000)
 -#define CPU_FTR_CP_USE_DCBTZ          LONG_ASM_CONST(0x0000800000000000)
 -#define CPU_FTR_UNALIGNED_LD_STD      LONG_ASM_CONST(0x0001000000000000)
 -#define CPU_FTR_ASYM_SMT              LONG_ASM_CONST(0x0002000000000000)
 -#define CPU_FTR_STCX_CHECKS_ADDRESS   LONG_ASM_CONST(0x0004000000000000)
 -#define CPU_FTR_POPCNTB                       LONG_ASM_CONST(0x0008000000000000)
 -#define CPU_FTR_POPCNTD                       LONG_ASM_CONST(0x0010000000000000)
 -#define CPU_FTR_PKEY                  LONG_ASM_CONST(0x0020000000000000)
 -#define CPU_FTR_VMX_COPY              LONG_ASM_CONST(0x0040000000000000)
 -#define CPU_FTR_TM                    LONG_ASM_CONST(0x0080000000000000)
 -#define CPU_FTR_CFAR                  LONG_ASM_CONST(0x0100000000000000)
 -#define       CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 -#define CPU_FTR_DAWR                  LONG_ASM_CONST(0x0400000000000000)
 -#define CPU_FTR_DABRX                 LONG_ASM_CONST(0x0800000000000000)
 -#define CPU_FTR_PMAO_BUG              LONG_ASM_CONST(0x1000000000000000)
 -#define CPU_FTR_P9_TLBIE_BUG          LONG_ASM_CONST(0x2000000000000000)
 -#define CPU_FTR_POWER9_DD1            LONG_ASM_CONST(0x4000000000000000)
 -#define CPU_FTR_POWER9_DD2_1          LONG_ASM_CONST(0x8000000000000000)
 +#define CPU_FTR_REAL_LE                       LONG_ASM_CONST(0x0000000000001000)
 +#define CPU_FTR_HVMODE                        LONG_ASM_CONST(0x0000000000002000)
 +#define CPU_FTR_ARCH_201              LONG_ASM_CONST(0x0000000000004000)
 +#define CPU_FTR_ARCH_206              LONG_ASM_CONST(0x0000000000008000)
 +#define CPU_FTR_ARCH_207S             LONG_ASM_CONST(0x0000000000010000)
 +#define CPU_FTR_ARCH_300              LONG_ASM_CONST(0x0000000000020000)
 +#define CPU_FTR_MMCRA                 LONG_ASM_CONST(0x0000000000040000)
 +#define CPU_FTR_CTRL                  LONG_ASM_CONST(0x0000000000080000)
 +#define CPU_FTR_SMT                   LONG_ASM_CONST(0x0000000000100000)
 +#define CPU_FTR_PAUSE_ZERO            LONG_ASM_CONST(0x0000000000200000)
 +#define CPU_FTR_PURR                  LONG_ASM_CONST(0x0000000000400000)
 +#define CPU_FTR_CELL_TB_BUG           LONG_ASM_CONST(0x0000000000800000)
 +#define CPU_FTR_SPURR                 LONG_ASM_CONST(0x0000000001000000)
 +#define CPU_FTR_DSCR                  LONG_ASM_CONST(0x0000000002000000)
 +#define CPU_FTR_VSX                   LONG_ASM_CONST(0x0000000004000000)
 +#define CPU_FTR_SAO                   LONG_ASM_CONST(0x0000000008000000)
 +#define CPU_FTR_CP_USE_DCBTZ          LONG_ASM_CONST(0x0000000010000000)
 +#define CPU_FTR_UNALIGNED_LD_STD      LONG_ASM_CONST(0x0000000020000000)
 +#define CPU_FTR_ASYM_SMT              LONG_ASM_CONST(0x0000000040000000)
 +#define CPU_FTR_STCX_CHECKS_ADDRESS   LONG_ASM_CONST(0x0000000080000000)
 +#define CPU_FTR_POPCNTB                       LONG_ASM_CONST(0x0000000100000000)
 +#define CPU_FTR_POPCNTD                       LONG_ASM_CONST(0x0000000200000000)
 +#define CPU_FTR_PKEY                  LONG_ASM_CONST(0x0000000400000000)
 +#define CPU_FTR_VMX_COPY              LONG_ASM_CONST(0x0000000800000000)
 +#define CPU_FTR_TM                    LONG_ASM_CONST(0x0000001000000000)
 +#define CPU_FTR_CFAR                  LONG_ASM_CONST(0x0000002000000000)
 +#define       CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0000004000000000)
 +#define CPU_FTR_DAWR                  LONG_ASM_CONST(0x0000008000000000)
 +#define CPU_FTR_DABRX                 LONG_ASM_CONST(0x0000010000000000)
 +#define CPU_FTR_PMAO_BUG              LONG_ASM_CONST(0x0000020000000000)
 +#define CPU_FTR_POWER9_DD1            LONG_ASM_CONST(0x0000040000000000)
 +#define CPU_FTR_POWER9_DD2_1          LONG_ASM_CONST(0x0000080000000000)
 +#define CPU_FTR_P9_TM_HV_ASSIST               LONG_ASM_CONST(0x0000100000000000)
 +#define CPU_FTR_P9_TM_XER_SO_BUG      LONG_ASM_CONST(0x0000200000000000)
++#define CPU_FTR_P9_TLBIE_BUG          LONG_ASM_CONST(0x0000400000000000)
  
  #ifndef __ASSEMBLY__
  
@@@ -464,8 -464,9 +465,9 @@@
            CPU_FTR_DSCR | CPU_FTR_SAO  | \
            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
            CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 -          CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
 -          CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | \
 -          CPU_FTR_PKEY | CPU_FTR_P9_TLBIE_BUG)
 +          CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
-           CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY)
++          CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
++          CPU_FTR_P9_TLBIE_BUG)
  #define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
                             (~CPU_FTR_SAO))
  #define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9

diff --cc arch/powerpc/kernel/dt_cpu_ftrs.c
index 0af2c5d,8ca5d5b..4313ff0
--- 1/arch/powerpc/kernel/dt_cpu_ftrs.c
--- 2/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@@ -710,12 -709,9 +710,14 @@@ static __init void cpufeatures_cpu_quir
                cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
        else if ((version & 0xffffefff) == 0x004e0201)
                cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
 +      else if ((version & 0xffffefff) == 0x004e0202)
 +              cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST |
 +                      CPU_FTR_P9_TM_XER_SO_BUG;
  
--      if ((version & 0xffff0000) == 0x004e0000)
++      if ((version & 0xffff0000) == 0x004e0000) {
 +              cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
+               cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG;
++      }
  }
  
  static void __init cpufeatures_setup_finished(void)

diff --cc arch/powerpc/kernel/exceptions-64s.S
Simple merge

diff --cc arch/powerpc/kernel/prom_init.c
Simple merge

diff --cc arch/powerpc/mm/hash_native_64.c
Simple merge

diff --cc arch/powerpc/mm/mmu_context_book3s64.c
Simple merge

diff --cc arch/powerpc/mm/tlb-radix.c
index 001c1f6,a07f537..291eab4
--- 1/arch/powerpc/mm/tlb-radix.c
--- 2/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@@ -119,6 -119,49 +119,49 @@@ static inline void __tlbie_pid(unsigne
        trace_tlbie(0, 0, rb, rs, ric, prs, r);
  }
  
 -      r = 1;   /* raidx format */
+ static inline void __tlbiel_va(unsigned long va, unsigned long pid,
+                              unsigned long ap, unsigned long ric)
+ {
+       unsigned long rb,rs,prs,r;
+ 
+       rb = va & ~(PPC_BITMASK(52, 63));
+       rb |= ap << PPC_BITLSHIFT(58);
+       rs = pid << PPC_BITLSHIFT(31);
+       prs = 1; /* process scoped */
 -      r = 1;   /* raidx format */
++      r = 1;   /* radix format */
+ 
+       asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
+                    : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
+       trace_tlbie(0, 1, rb, rs, ric, prs, r);
+ }
+ 
+ static inline void __tlbie_va(unsigned long va, unsigned long pid,
+                             unsigned long ap, unsigned long ric)
+ {
+       unsigned long rb,rs,prs,r;
+ 
+       rb = va & ~(PPC_BITMASK(52, 63));
+       rb |= ap << PPC_BITLSHIFT(58);
+       rs = pid << PPC_BITLSHIFT(31);
+       prs = 1; /* process scoped */
++      r = 1;   /* radix format */
+ 
+       asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+                    : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
+       trace_tlbie(0, 0, rb, rs, ric, prs, r);
+ }
+ 
+ static inline void fixup_tlbie(void)
+ {
+       unsigned long pid = 0;
+       unsigned long va = ((1UL << 52) - 1);
+ 
+       if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
+               asm volatile("ptesync": : :"memory");
+               __tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
+       }
+ }
+ 
  /*
   * We use 128 set in radix mode and 256 set in hpt mode.
   */

diff --cc tools/testing/selftests/powerpc/tm/Makefile
Simple merge