// Integer registers are 32 bits.
Ret += "-n32";
- // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
- if (ST.isAAPCS_ABI())
+ // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
+ // aligned everywhere else.
+ if (ST.isTargetNaCl())
+ Ret += "-S128";
+ else if (ST.isAAPCS_ABI())
Ret += "-S64";
else
Ret += "-S32";
/// Is this x86_64 with the ILP32 programming model (x32 ABI)?
bool isTarget64BitILP32() const {
- return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
+ return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
+ TargetTriple.getOS() == Triple::NaCl);
}
/// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Ret += "-p:32:32";
// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
- if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
+ if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
+ ST.isTargetNaCl())
Ret += "-i64:64";
else
Ret += "-f64:32:64";
// Some ABIs align long double to 128 bits, others to 32.
- if (ST.is64Bit() || ST.isTargetDarwin())
+ if (ST.isTargetNaCl())
+ ; // No f80
+ else if (ST.is64Bit() || ST.isTargetDarwin())
Ret += "-f80:128";
else
Ret += "-f80:32";