Move ARM if-conversion before post-ra scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 06c893a..e69349d 100644 (file)
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -27,11 +27,6 @@ EarlyITBlockFormation("thumb2-early-it-blocks", cl::Hidden,
   cl::desc("Form IT blocks early before register allocation"),
   cl::init(false));
 
-static cl::opt<bool>
-EarlyIfConvert("arm-early-if-convert", cl::Hidden,
-  cl::desc("Run if-conversion before post-ra scheduling"),
-  cl::init(false));
-
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -130,7 +125,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
   // proper scheduling.
   PM.add(createARMExpandPseudoPass());
 
-  if (EarlyIfConvert && OptLevel != CodeGenOpt::None) {
+  if (OptLevel != CodeGenOpt::None) {
     if (!Subtarget.isThumb1Only())
       PM.add(createIfConverterPass());
     if (Subtarget.isThumb2())
@@ -142,16 +137,8 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 
 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel) {
-  if (!EarlyIfConvert && OptLevel != CodeGenOpt::None) {
-    if (!Subtarget.isThumb1Only())
-      PM.add(createIfConverterPass());
-  }
-
-  if (Subtarget.isThumb2()) {
-    if (!EarlyIfConvert)
-      PM.add(createThumb2ITBlockPass());
+  if (Subtarget.isThumb2())
     PM.add(createThumb2SizeReductionPass());
-  }
 
   PM.add(createARMConstantIslandPass());
   return true;

diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll
index 7fc2e2a..56cb1f6 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-select_xform.ll
+++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll
@@ -3,8 +3,8 @@
 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
 ; CHECK: t1
 ; CHECK: sub.w r0, r1, #-2147483648
+; CHECK: subs r0, #1
 ; CHECK: cmp r2, #10
-; CHECK: sub.w r0, r0, #1
 ; CHECK: it  gt
 ; CHECK: movgt r0, r1
         %tmp1 = icmp sgt i32 %c, 10