i965: Fix flat integral varyings.

Previously, the vertex and fragment shader back-ends assumed that all
varyings were floats.  In GLSL 1.30 this is no longer true--they can
also be of integral types provided that they have an interpolation
qualifier of "flat".

This required two changes in each back-end: assigning the correct type
to the register that holds the varying value during shader execution,
and assigning the correct type to the register that ties the varying
value to the rest of the graphics pipeline (the message register in
the case of VS, and the payload register in the case of FS).

Fixes piglit tests fs-int-interpolation and fs-uint-interpolation.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 31c3116..e58545b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -424,8 +424,7 @@ fs_reg *
 fs_visitor::emit_general_interpolation(ir_variable *ir)
 {
    fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
-   /* Interpolation is always in floating point regs. */
-   reg->type = BRW_REGISTER_TYPE_F;
+   reg->type = brw_type_for_base_type(ir->type->get_scalar_type());
    fs_reg attr = *reg;
 
    unsigned int array_elements;
@@ -465,6 +464,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
            for (unsigned int k = 0; k < type->vector_elements; k++) {
               struct brw_reg interp = interp_reg(location, k);
               interp = suboffset(interp, 3);
+               interp.type = reg->type;
               emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
               attr.reg_offset++;
            }

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 1312c0d..e5d5997 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -853,7 +853,8 @@ vec4_visitor::visit(ir_variable *ir)
       for (int i = 0; i < type_size(ir->type); i++) {
         output_reg[ir->location + i] = *reg;
         output_reg[ir->location + i].reg_offset = i;
-        output_reg[ir->location + i].type = BRW_REGISTER_TYPE_F;
+        output_reg[ir->location + i].type =
+            brw_type_for_base_type(ir->type->get_scalar_type());
         output_reg_annotation[ir->location + i] = ir->name;
       }
       break;
@@ -1915,6 +1916,7 @@ void
 vec4_visitor::emit_generic_urb_slot(dst_reg reg, int vert_result)
 {
    assert (vert_result < VERT_RESULT_MAX);
+   reg.type = output_reg[vert_result].type;
    current_annotation = output_reg_annotation[vert_result];
    /* Copy the register, saturating if necessary */
    vec4_instruction *inst = emit(MOV(reg,