drm/amd/display: add renoir specific watermark range and clk helper

Doing this allows us to split it for diffrent asics. This design will
be helpful for future Asciis.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index ba959f0..93e46e3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = {
        }
 };
 
-void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 {
        int i, num_valid_sets;
 
@@ -529,7 +529,7 @@ void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_ra
 
 }
 
-unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 {
        int i;
 
@@ -542,7 +542,7 @@ unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned in
        return 0;
 }
 
-void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
+void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
 {
        int i, j = 0;
 
@@ -557,22 +557,15 @@ void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct d
                }
        }
 
-       for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
-               if (j < 0) {
-                       /* Invalid entries */
-                       bw_params->clk_table.entries[i].fclk_mhz = 0;
-                       continue;
-               }
+       bw_params->clk_table.num_entries = j + 1;
+
+       for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
                bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
                bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
                bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
                bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
-               j--;
        }
 
-
-       bw_params->clk_table.num_entries = i;
-
        bw_params->vram_type = asic_id->vram_type;
        bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH;
 
@@ -658,7 +651,7 @@ void rn_clk_mgr_construct(
 
        if (pp_smu) {
                pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
-               clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
+               rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
        }
 
        /*
@@ -669,7 +662,7 @@ void rn_clk_mgr_construct(
        if (!debug->disable_pplib_wm_range) {
                struct pp_smu_wm_range_sets ranges = {0};
 
-               build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
+               rn_build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
 
                /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
                if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
index 9589390..761bfda 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
@@ -26,10 +26,20 @@
 #ifndef __RN_CLK_MGR_H__
 #define __RN_CLK_MGR_H__
 
+#include "clk_mgr.h"
+#include "dm_pp_smu.h"
+
 struct rn_clk_registers {
        uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
 };
 
+void rn_build_watermark_ranges(
+               struct clk_bw_params *bw_params,
+               struct pp_smu_wm_range_sets *ranges);
+void rn_clk_mgr_helper_populate_bw_params(
+               struct clk_bw_params *bw_params,
+               struct dpm_clocks *clock_table,
+               struct hw_asic_id *asic_id);
 void rn_clk_mgr_construct(struct dc_context *ctx,
                struct clk_mgr_internal *clk_mgr,
                struct pp_smu_funcs *pp_smu,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 5486fc6..d2fc614 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1278,7 +1278,6 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
        dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
        dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
        dcn2_1_soc.num_chans = bw_params->num_channels;
-       dcn2_1_soc.num_states = 0;
 
        for (i = 0; i < clk_table->num_entries; i++) {
 
@@ -1288,8 +1287,9 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
                dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
                /* This is probably wrong, TODO: find correct calculation */
                dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
-               dcn2_1_soc.num_states++;
        }
+       dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
+       dcn2_1_soc.num_states = i;
 }
 
 /* Temporary Place holder until we can get them from fuse */
@@ -1317,20 +1317,20 @@ static struct dpm_clocks dummy_clocks = {
 
 };
 
-enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
+static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
                struct pp_smu_wm_range_sets *ranges)
 {
        return PP_SMU_RESULT_OK;
 }
 
-enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
+static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
                struct dpm_clocks *clock_table)
 {
        *clock_table = dummy_clocks;
        return PP_SMU_RESULT_OK;
 }
 
-struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
+static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
 {
        struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
 
@@ -1352,7 +1352,7 @@ struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
        return pp_smu;
 }
 
-void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
 {
        if (pp_smu && *pp_smu) {
                kfree(*pp_smu);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index f0f3d42..f2e21cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -47,7 +47,7 @@
 #ifdef CONFIG_DRM_AMD_DC_DCN2_1
 /* Will these bw structures be ASIC specific? */
 
-#define MAX_NUM_DPM_LVL                4
+#define MAX_NUM_DPM_LVL                8
 #define WM_SET_COUNT           4
 
 
@@ -149,6 +149,7 @@ struct wm_table {
 struct clk_bw_params {
        unsigned int vram_type;
        unsigned int num_channels;
+       unsigned int dispclk_vco_khz;
        struct clk_limit_table clk_table;
        struct wm_table wm_table;
 };