Fix wording regarding Intel's IA-64 architecture.

diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index e2422d5..e5b6e70 100644 (file)
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,8 @@
+2000-02-15  Kevin Buettner  <kevinb@redhat.com>
+
+       * agentexpr.texi: Fix wording regarding Intel's IA-64
+       architecture.
+
 2000-01-16  Tom Tromey  <tromey@cygnus.com>
 
        * gdb.texinfo (Breakpoints): Mention breakpoint ranges.

diff --git a/gdb/doc/agentexpr.texi b/gdb/doc/agentexpr.texi
index 8484aa2..e49232c 100644 (file)
--- a/gdb/doc/agentexpr.texi
+++ b/gdb/doc/agentexpr.texi
@@ -798,7 +798,7 @@ When we add side-effects, we should add this.
 
 @item Why does the @code{reg} bytecode take a 16-bit register number?
 
-Intel's IA64-architecture, Merced, has 128 general-purpose registers,
+Intel's IA-64 architecture has 128 general-purpose registers,
 and 128 floating-point registers, and I'm sure it has some random
 control registers.