Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
link->dpcd_caps.panel_mode_edp =
edp_config_cap.bits.ALT_SCRAMBLER_RESET;
+ link->dpcd_caps.dpcd_display_control_capable =
+ edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
link->test_pattern_enabled = false;
link->compliance_test_state.raw = 0;
bool allow_invalid_MSA_timing_param;
bool panel_mode_edp;
+ bool dpcd_display_control_capable;
};
struct dc_link_status {
struct dpcd_caps dpcd_caps;
unsigned short chip_caps;
unsigned int dpcd_sink_count;
-
enum edp_revision edp_revision;
bool psr_enabled;