[SelectionDAG] fold 'fneg undef' to undef

This is extracted from the original draft of D61419 with some additional tests.
We don't currently get this in IR (it's conservatively turned into a NaN),
but presumably that'll get updated as we add real IR support for 'fneg'
rather than 'fsub -0.0, x'.

The x86-32 run shows the following, and I haven't looked further to see why,
but that seems to be independent:
  Legalizing: t1: f32 = undef
  Trying to expand node
  Creating fp constant: t4: f32 = ConstantFP<0.000000e+00>

Differential Revision: https://reviews.llvm.org/D61516

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360296 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3b14e00..3597c6d 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4482,6 +4482,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
       return Operand.getOperand(0);
     break;
   case ISD::FNEG:
+    // Negation of an unknown bag of bits is still completely undefined.
+    if (OpOpcode == ISD::UNDEF)
+      return getUNDEF(VT);
+
     // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
     if ((getTarget().Options.UnsafeFPMath || Flags.hasNoSignedZeros()) &&
         OpOpcode == ISD::FSUB)

diff --git a/test/CodeGen/X86/vec_fneg.ll b/test/CodeGen/X86/vec_fneg.ll
index 3b16a05..4d5539f 100644 (file)
--- a/test/CodeGen/X86/vec_fneg.ll
+++ b/test/CodeGen/X86/vec_fneg.ll
@@ -24,105 +24,51 @@ define <4 x float> @t1(<4 x float> %Q) nounwind {
 ; Possibly misplaced test, but since we're checking undef scenarios...
 
 define float @scalar_fsub_neg0_undef(float %x) nounwind {
-; X32-SSE1-LABEL: scalar_fsub_neg0_undef:
-; X32-SSE1:       # %bb.0:
-; X32-SSE1-NEXT:    pushl %eax
-; X32-SSE1-NEXT:    xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT:    movss %xmm0, (%esp)
-; X32-SSE1-NEXT:    flds (%esp)
-; X32-SSE1-NEXT:    popl %eax
-; X32-SSE1-NEXT:    retl
-;
-; X32-SSE2-LABEL: scalar_fsub_neg0_undef:
-; X32-SSE2:       # %bb.0:
-; X32-SSE2-NEXT:    pushl %eax
-; X32-SSE2-NEXT:    movss %xmm0, (%esp)
-; X32-SSE2-NEXT:    flds (%esp)
-; X32-SSE2-NEXT:    popl %eax
-; X32-SSE2-NEXT:    retl
-;
-; X64-SSE1-LABEL: scalar_fsub_neg0_undef:
-; X64-SSE1:       # %bb.0:
-; X64-SSE1-NEXT:    xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT:    retq
+; X32-SSE-LABEL: scalar_fsub_neg0_undef:
+; X32-SSE:       # %bb.0:
+; X32-SSE-NEXT:    fldz
+; X32-SSE-NEXT:    retl
 ;
-; X64-SSE2-LABEL: scalar_fsub_neg0_undef:
-; X64-SSE2:       # %bb.0:
-; X64-SSE2-NEXT:    retq
+; X64-SSE-LABEL: scalar_fsub_neg0_undef:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    retq
   %r = fsub float -0.0, undef
   ret float %r
 }
 
 define float @scalar_fneg_undef(float %x) nounwind {
-; X32-SSE1-LABEL: scalar_fneg_undef:
-; X32-SSE1:       # %bb.0:
-; X32-SSE1-NEXT:    pushl %eax
-; X32-SSE1-NEXT:    xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT:    movss %xmm0, (%esp)
-; X32-SSE1-NEXT:    flds (%esp)
-; X32-SSE1-NEXT:    popl %eax
-; X32-SSE1-NEXT:    retl
-;
-; X32-SSE2-LABEL: scalar_fneg_undef:
-; X32-SSE2:       # %bb.0:
-; X32-SSE2-NEXT:    pushl %eax
-; X32-SSE2-NEXT:    movss %xmm0, (%esp)
-; X32-SSE2-NEXT:    flds (%esp)
-; X32-SSE2-NEXT:    popl %eax
-; X32-SSE2-NEXT:    retl
-;
-; X64-SSE1-LABEL: scalar_fneg_undef:
-; X64-SSE1:       # %bb.0:
-; X64-SSE1-NEXT:    xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT:    retq
+; X32-SSE-LABEL: scalar_fneg_undef:
+; X32-SSE:       # %bb.0:
+; X32-SSE-NEXT:    fldz
+; X32-SSE-NEXT:    retl
 ;
-; X64-SSE2-LABEL: scalar_fneg_undef:
-; X64-SSE2:       # %bb.0:
-; X64-SSE2-NEXT:    retq
+; X64-SSE-LABEL: scalar_fneg_undef:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    retq
   %r = fneg float undef
   ret float %r
 }
 
 define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind {
-; X32-SSE1-LABEL: fsub_neg0_undef:
-; X32-SSE1:       # %bb.0:
-; X32-SSE1-NEXT:    xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT:    retl
-;
-; X32-SSE2-LABEL: fsub_neg0_undef:
-; X32-SSE2:       # %bb.0:
-; X32-SSE2-NEXT:    retl
-;
-; X64-SSE1-LABEL: fsub_neg0_undef:
-; X64-SSE1:       # %bb.0:
-; X64-SSE1-NEXT:    xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT:    retq
+; X32-SSE-LABEL: fsub_neg0_undef:
+; X32-SSE:       # %bb.0:
+; X32-SSE-NEXT:    retl
 ;
-; X64-SSE2-LABEL: fsub_neg0_undef:
-; X64-SSE2:       # %bb.0:
-; X64-SSE2-NEXT:    retq
+; X64-SSE-LABEL: fsub_neg0_undef:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    retq
   %r = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
   ret <4 x float> %r
 }
 
 define <4 x float> @fneg_undef(<4 x float> %Q) nounwind {
-; X32-SSE1-LABEL: fneg_undef:
-; X32-SSE1:       # %bb.0:
-; X32-SSE1-NEXT:    xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT:    retl
-;
-; X32-SSE2-LABEL: fneg_undef:
-; X32-SSE2:       # %bb.0:
-; X32-SSE2-NEXT:    retl
-;
-; X64-SSE1-LABEL: fneg_undef:
-; X64-SSE1:       # %bb.0:
-; X64-SSE1-NEXT:    xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT:    retq
+; X32-SSE-LABEL: fneg_undef:
+; X32-SSE:       # %bb.0:
+; X32-SSE-NEXT:    retl
 ;
-; X64-SSE2-LABEL: fneg_undef:
-; X64-SSE2:       # %bb.0:
-; X64-SSE2-NEXT:    retq
+; X64-SSE-LABEL: fneg_undef:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    retq
   %r = fneg <4 x float> undef
   ret <4 x float> %r
 }