net/mlx5: A write memory barrier is sufficient in EQ ci update

Soften the memory barrier call of mb() by a sufficient wmb() in the
consumer index update of the event queues.

Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index 46a747f..e9837ae 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@ -707,7 +707,7 @@ void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
 
        __raw_writel((__force u32)cpu_to_be32(val), addr);
        /* We still want ordering, just not swabbing, so add a barrier */
-       mb();
+       wmb();
 }
 EXPORT_SYMBOL(mlx5_eq_update_ci);