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net/mlx5: A write memory barrier is sufficient in EQ ci update
author
Tariq Toukan
<tariqt@mellanox.com>
Sun, 16 Dec 2018 15:20:31 +0000
(17:20 +0200)
committer
Saeed Mahameed
<saeedm@mellanox.com>
Fri, 5 Apr 2019 21:10:35 +0000
(14:10 -0700)
Soften the memory barrier call of mb() by a sufficient wmb() in the
consumer index update of the event queues.
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/eq.c
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diff --git
a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index
46a747f
..
e9837ae
100644
(file)
--- a/
drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/
drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@
-707,7
+707,7
@@
void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
__raw_writel((__force u32)cpu_to_be32(val), addr);
/* We still want ordering, just not swabbing, so add a barrier */
- mb();
+
w
mb();
}
EXPORT_SYMBOL(mlx5_eq_update_ci);