+2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * archures.c (bfd_mach_m32r2): Add new machine type.
+ * bfd-in2.h: Regenerate.
+ * cpu-m32r.c : Add new machine type.
+ * elf32-m32r.c (m32r_elf_object_p, m32r_elf_final_write_processing,
+ m32r_elf_merge_private_bfd_data): Add support for new machine
+ type.
+
2003-12-03 Dave Airlie <airlied@linux.ie>
* config.bfd: Add vax-linux-gnu target.
. bfd_arch_m32r, {* Renesas M32R (formerly Mitsubishi M32R/D) *}
.#define bfd_mach_m32r 1 {* For backwards compatibility. *}
.#define bfd_mach_m32rx 'x'
+.#define bfd_mach_m32r2 '2'
. bfd_arch_mn10200, {* Matsushita MN10200 *}
. bfd_arch_mn10300, {* Matsushita MN10300 *}
.#define bfd_mach_mn10300 300
bfd_arch_m32r, /* Renesas M32R (formerly Mitsubishi M32R/D) */
#define bfd_mach_m32r 1 /* For backwards compatibility. */
#define bfd_mach_m32rx 'x'
+#define bfd_mach_m32r2 '2'
bfd_arch_mn10200, /* Matsushita MN10200 */
bfd_arch_mn10300, /* Matsushita MN10300 */
#define bfd_mach_mn10300 300
/* BFD support for the M32R processor.
- Copyright 1996, 1999, 2000, 2002 Free Software Foundation, Inc.
+ Copyright 1996, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
{ 32, 32, 8, bfd_arch_m32r, number, "m32r", print, 4, default, \
bfd_default_compatible, bfd_default_scan, next }
-#define NEXT NULL
+#define M32R2_NEXT & arch_info_struct [1]
+#define NEXT & arch_info_struct [0]
static const bfd_arch_info_type arch_info_struct[] =
{
- N (bfd_mach_m32rx, "m32rx", FALSE, NULL)
+ N (bfd_mach_m32rx, "m32rx", FALSE, M32R2_NEXT) ,
+ N (bfd_mach_m32r2, "m32r2", FALSE, NULL)
};
-#undef NEXT
-#define NEXT &arch_info_struct[0]
-
const bfd_arch_info_type bfd_m32r_arch =
N (bfd_mach_m32r, "m32r", TRUE, NEXT);
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
default:
case E_M32R_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_m32r, bfd_mach_m32r); break;
case E_M32RX_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_m32r, bfd_mach_m32rx); break;
+ case E_M32R2_ARCH: (void) bfd_default_set_arch_mach (abfd, bfd_arch_m32r, bfd_mach_m32r2); break;
}
return TRUE;
}
default:
case bfd_mach_m32r: val = E_M32R_ARCH; break;
case bfd_mach_m32rx: val = E_M32RX_ARCH; break;
+ case bfd_mach_m32r2: val = E_M32R2_ARCH; break;
}
elf_elfheader (abfd)->e_flags &=~ EF_M32R_ARCH;
if ((in_flags & EF_M32R_ARCH) != (out_flags & EF_M32R_ARCH))
{
- if ((in_flags & EF_M32R_ARCH) != E_M32R_ARCH)
+ if ( ((in_flags & EF_M32R_ARCH) != E_M32R_ARCH)
+ || ((out_flags & EF_M32R_ARCH) == E_M32R_ARCH)
+ || ((in_flags & EF_M32R_ARCH) == E_M32R2_ARCH))
{
(*_bfd_error_handler)
(_("%s: Instruction set mismatch with previous modules"),
default:
case E_M32R_ARCH: fprintf (file, _(": m32r instructions")); break;
case E_M32RX_ARCH: fprintf (file, _(": m32rx instructions")); break;
+ case E_M32R2_ARCH: fprintf (file, _(": m32r2 instructions")); break;
}
fputc ('\n', file);
+2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * cpu/m32r.cpu : Add new model m32r2.
+ Add new instructions.
+ Replace occurrances of 'Mitsubishi' with 'Renesas'.
+ Changed PIPE attr of push from O to OS.
+ Care for Little-endian of M32R.
+ * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
+ Care for Little-endian of M32R.
+ (parse_slo16): signed extension for value.
+
2003-10-26 Dave Brolley <brolley@redhat.com>
* sid-decode.scm (-gen-record-profile-args): Test trace_counter_p
-; Mitsubishi M32R CPU description. -*- Scheme -*-
-; Copyright (C) 2000 Red Hat, Inc.
+; Renesas M32R CPU description. -*- Scheme -*-
+; Copyright (C) 2000, 2003 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
(define-arch
(name m32r) ; name of cpu family
- (comment "Mitsubishi M32R")
+ (comment "Renesas M32R")
(default-alignment aligned)
(insn-lsb0? #f)
- (machs m32r m32rx)
+ (machs m32r m32rx m32r2)
(isas m32r)
)
; Attributes.
; An attribute to describe which pipeline an insn runs in.
+; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
+; These instructions have O attribute for m32rx and OS attribute for m32r2.
(define-attr
(for insn)
(type enum)
(name PIPE)
(comment "parallel execution pipeline selection")
- (values NONE O S OS)
+ (values NONE O S OS O_OS)
)
; A derived attribute that says which insns can be executed in parallel
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m32rbf)
- (comment "Mitsubishi M32R base family")
- (endian big)
+ (comment "Renesas M32R base family")
+ (endian either)
(word-bitsize 32)
; Override isa spec (??? keeps things simpler, though it was more true
; in the early days and not so much now).
(define-cpu
(name m32rxf)
- (comment "Mitsubishi M32Rx family")
- (endian big)
+ (comment "Renesas M32Rx family")
+ (endian either)
(word-bitsize 32)
; Generated files have an "x" suffix.
(file-transform "x")
)
+(define-cpu
+ (name m32r2f)
+ (comment "Renesas M32R2 family")
+ (endian either)
+ (word-bitsize 32)
+ ; Generated files have an "2" suffix.
+ (file-transform "2")
+)
+
(define-mach
(name m32r)
(comment "Generic M32R cpu")
(comment "M32RX cpu")
(cpu m32rxf)
)
+
+(define-mach
+ (name m32r2)
+ (comment "M32R2 cpu")
+ (cpu m32r2f)
+)
\f
; Model descriptions.
() ; profile action (default)
)
)
+
+(define-model
+ (name m32r2) (comment "m32r2") (attrs)
+ (mach m32r2)
+
+ ; ??? It's 6 stages but I forget the details right now.
+ (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
+ (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
+ (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
+
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((sr INT -1) (dr INT -1)) ; inputs
+ ((dr INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-cmp "Compare Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((src1 INT -1) (src2 INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ (unit u-mac "Multiply/Accumulate Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((src1 INT -1) (src2 INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ (unit u-cti "Branch Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((sr INT -1)) ; inputs
+ ((pc)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-load "Memory Load Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((sr INT)) ; inputs
+ ((dr INT)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-store "Memory Store Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((src1 INT) (src2 INT)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+)
\f
; The instruction fetch/execute cycle.
; This is split into two parts as sometimes more than one instruction is
(df f-simm8 "simm8" () 8 8 INT #f #f)
(df f-simm16 "simm16" () 16 16 INT #f #f)
(dnf f-shift-op2 "shift op2" () 8 3)
+(dnf f-uimm3 "uimm3" () 5 3)
(dnf f-uimm4 "uimm4" () 12 4)
(dnf f-uimm5 "uimm5" () 11 5)
+(dnf f-uimm8 "uimm8" () 8 8)
(dnf f-uimm16 "uimm16" () 16 16)
(dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24)
(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
(dnf f-accs "accs" () 12 2)
(dnf f-accd "accd" () 4 2)
(dnf f-bits67 "bits67" () 6 2)
+(dnf f-bit4 "bit4" () 4 1)
(dnf f-bit14 "bit14" () 14 1)
(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
(print-name h-cr)
(prefix "")
(values (psw 0) (cbr 1) (spi 2) (spu 3)
- (bpc 6) (bbpsw 8) (bbpc 14)
+ (bpc 6) (bbpsw 8) (bbpc 14) (evb 5)
(cr0 0) (cr1 1) (cr2 2) (cr3 3)
(cr4 4) (cr5 5) (cr6 6) (cr7 7)
(cr8 8) (cr9 9) (cr10 10) (cr11 11)
(define-hardware
(name h-accums)
(comment "accumulators")
- (attrs (MACH m32rx))
+ (attrs (MACH m32rx,m32r2))
(type register DI (2))
(indices keyword "" ((a0 0) (a1 1)))
; get/set so a0 accesses are redirected to h-accum.
(dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)
(dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
+(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3)
(dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)
(dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
+(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
-(dnop imm1 "1 bit immediate" ((MACH m32rx) HASH-PREFIX) h-uint f-imm1)
-(dnop accd "accumulator destination register" ((MACH m32rx)) h-accums f-accd)
-(dnop accs "accumulator source register" ((MACH m32rx)) h-accums f-accs)
-(dnop acc "accumulator reg (d)" ((MACH m32rx)) h-accums f-acc)
+(dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
+(dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)
+(dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs)
+(dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc)
; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX.
(comment "non-public m32rx insn")
)
+(define-attr
+ (for insn)
+ (type boolean)
+ (name SPECIAL_M32R)
+ (comment "non-public m32r insn")
+)
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name SPECIAL_FLOAT)
+ (comment "floating point insn")
+)
+
; IDOC attribute for instruction documentation.
(define-attr
(+ OP1_4 dr simm8)
(set dr (add dr simm8))
((m32r/d (unit u-exec))
- (m32rx (unit u-exec)))
+ (m32rx (unit u-exec))
+ (m32r2 (unit u-exec)))
)
(dni addv "addv"
(+ OP1_7 (f-r1 12) disp8)
(if condbit (set pc disp8))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bc8r "relaxable bc8"
(+ OP1_15 (f-r1 12) disp24)
(if condbit (set pc disp24))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bc24r "relaxable bc24"
(+ OP1_11 OP2_0 src1 src2 disp16)
(if (eq src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
- (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
+ (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
+ (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
(define-pmacro (cbranch sym comment op2-op comp-op)
(+ OP1_11 op2-op (f-r1 0) src2 disp16)
(if (comp-op src2 (const WI 0)) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
- (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
+ (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
+ (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
)
(cbranch beqz "beqz" OP2_8 eq)
(add (and pc (const -4)) (const 4)))
(set pc disp8))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bl8r "relaxable bl8"
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bl24r "relaxable bl24"
)
(dni bcl8 "bcl with 8 bit displacement"
- (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))
+ (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
"bcl.s $disp8"
(+ OP1_7 (f-r1 8) disp8)
(if condbit
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
- ((m32rx (unit u-cti)))
+ ((m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bcl8r "relaxable bcl8"
- (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))
+ (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
"bcl $disp8"
(emit bcl8 disp8)
)
(dni bcl24 "bcl with 24 bit displacement"
- (COND-CTI (MACH m32rx) (IDOC BR))
+ (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
"bcl.l $disp24"
(+ OP1_15 (f-r1 8) disp24)
(if condbit
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
- ((m32rx (unit u-cti)))
+ ((m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bcl24r "relaxable bcl24"
- (COND-CTI (MACH m32rx) RELAXED (IDOC BR))
+ (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
"bcl $disp24"
(emit bcl24 disp24)
)
(+ OP1_7 (f-r1 13) disp8)
(if (not condbit) (set pc disp8))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bnc8r "relaxable bnc8"
(+ OP1_15 (f-r1 13) disp24)
(if (not condbit) (set pc disp24))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bnc24r "relaxable bnc24"
(+ OP1_11 OP2_1 src1 src2 disp16)
(if (ne src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
- (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
+ (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
+ (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
(dni bra8 "bra with 8 bit displacement"
(+ OP1_7 (f-r1 15) disp8)
(set pc disp8)
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bra8r "relaxable bra8"
(+ OP1_15 (f-r1 15) disp24)
(set pc disp24)
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bra24r "relaxable bra24"
)
(dni bncl8 "bncl with 8 bit displacement"
- (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))
+ (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
"bncl.s $disp8"
(+ OP1_7 (f-r1 9) disp8)
(if (not condbit)
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
- ((m32rx (unit u-cti)))
+ ((m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bncl8r "relaxable bncl8"
- (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))
+ (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
"bncl $disp8"
(emit bncl8 disp8)
)
(dni bncl24 "bncl with 24 bit displacement"
- (COND-CTI (MACH m32rx) (IDOC BR))
+ (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
"bncl.l $disp24"
(+ OP1_15 (f-r1 9) disp24)
(if (not condbit)
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
- ((m32rx (unit u-cti)))
+ ((m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dnmi bncl24r "relaxable bncl24"
- (COND-CTI (MACH m32rx) RELAXED (IDOC BR))
+ (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
"bncl $disp24"
(emit bncl24 disp24)
)
(+ OP1_0 OP2_4 src1 src2)
(set condbit (lt src1 src2))
((m32r/d (unit u-cmp))
- (m32rx (unit u-cmp)))
+ (m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
(dni cmpi "cmpi"
(+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
(set condbit (lt src2 simm16))
((m32r/d (unit u-cmp))
- (m32rx (unit u-cmp)))
+ (m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
(dni cmpu "cmpu"
(+ OP1_0 OP2_5 src1 src2)
(set condbit (ltu src1 src2))
((m32r/d (unit u-cmp))
- (m32rx (unit u-cmp)))
+ (m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
(dni cmpui "cmpui"
(+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
(set condbit (ltu src2 simm16))
((m32r/d (unit u-cmp))
- (m32rx (unit u-cmp)))
+ (m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
(dni cmpeq "cmpeq"
- ((MACH m32rx) (PIPE OS) (IDOC ALU))
+ ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
"cmpeq $src1,$src2"
(+ OP1_0 OP2_6 src1 src2)
(set condbit (eq src1 src2))
- ((m32rx (unit u-cmp)))
+ ((m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
(dni cmpz "cmpz"
- ((MACH m32rx) (PIPE OS) (IDOC ALU))
+ ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
"cmpz $src2"
(+ OP1_0 OP2_7 (f-r1 0) src2)
(set condbit (eq src2 (const 0)))
- ((m32rx (unit u-cmp)))
+ ((m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
(dni div "div"
(+ OP1_9 OP2_0 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (div dr sr)))
((m32r/d (unit u-exec (cycles 37)))
- (m32rx (unit u-exec (cycles 37))))
+ (m32rx (unit u-exec (cycles 37)))
+ (m32r2 (unit u-exec (cycles 37))))
)
(dni divu "divu"
(+ OP1_9 OP2_1 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (udiv dr sr)))
((m32r/d (unit u-exec (cycles 37)))
- (m32rx (unit u-exec (cycles 37))))
+ (m32rx (unit u-exec (cycles 37)))
+ (m32r2 (unit u-exec (cycles 37))))
)
(dni rem "rem"
; FIXME: Check rounding direction.
(if (ne sr (const 0)) (set dr (mod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
- (m32rx (unit u-exec (cycles 37))))
+ (m32rx (unit u-exec (cycles 37)))
+ (m32r2 (unit u-exec (cycles 37))))
)
(dni remu "remu"
; FIXME: Check rounding direction.
(if (ne sr (const 0)) (set dr (umod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
- (m32rx (unit u-exec (cycles 37))))
+ (m32rx (unit u-exec (cycles 37)))
+ (m32r2 (unit u-exec (cycles 37))))
+)
+
+(dni remh "remh"
+ ((MACH m32r2))
+ "remh $dr,$sr"
+ (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
+ ; FIXME: Check rounding direction.
+ (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni remuh "remuh"
+ ((MACH m32r2))
+ "remuh $dr,$sr"
+ (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
+ ; FIXME: Check rounding direction.
+ (if (ne sr (const 0)) (set dr (umod dr sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni remb "remb"
+ ((MACH m32r2))
+ "remb $dr,$sr"
+ (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
+ ; FIXME: Check rounding direction.
+ (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni remub "remub"
+ ((MACH m32r2))
+ "remub $dr,$sr"
+ (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
+ ; FIXME: Check rounding direction.
+ (if (ne sr (const 0)) (set dr (umod dr sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divuh "divuh"
+ ((MACH m32r2))
+ "divuh $dr,$sr"
+ (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
+ (if (ne sr (const 0)) (set dr (udiv dr sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divb "divb"
+ ((MACH m32r2))
+ "divb $dr,$sr"
+ (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
+ (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
+)
+
+(dni divub "divub"
+ ((MACH m32r2))
+ "divub $dr,$sr"
+ (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
+ (if (ne sr (const 0)) (set dr (udiv dr sr)))
+ ((m32r2 (unit u-exec (cycles 21))))
)
(dni divh "divh"
- ((MACH m32rx) (IDOC ALU))
+ ((MACH m32rx,m32r2) (IDOC ALU))
"divh $dr,$sr"
(+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
- ((m32rx (unit u-exec (cycles 21))))
+ ((m32rx (unit u-exec (cycles 21)))
+ (m32r2 (unit u-exec (cycles 21))))
)
(dni jc "jc"
- (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
+ (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"jc $sr"
(+ OP1_1 (f-r1 12) OP2_12 sr)
(if condbit (set pc (and sr (const -4))))
- ((m32rx (unit u-cti)))
+ ((m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dni jnc "jnc"
- (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
+ (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"jnc $sr"
(+ OP1_1 (f-r1 13) OP2_12 sr)
(if (not condbit) (set pc (and sr (const -4))))
- ((m32rx (unit u-cti)))
+ ((m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dni jl "jl"
(add (and pc (const -4)) (const 4)))
(set pc (and sr (const -4))))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(dni jmp "jmp"
; (add WI (and WI pc (const WI -4)) (const WI 4))))
; (set WI pc sr))
((m32r/d (unit u-cti))
- (m32rx (unit u-cti)))
+ (m32rx (unit u-cti))
+ (m32r2 (unit u-cti)))
)
(define-pmacro (no-ext-expr mode expr) expr)
(+ OP1_2 op2-op dr sr)
(set dr (ext-op WI (mem mode sr)))
((m32r/d (unit u-load))
- (m32rx (unit u-load)))
+ (m32rx (unit u-load))
+ (m32r2 (unit u-load)))
)
(dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
(+ OP1_10 op2-op dr sr slo16)
(set dr (ext-op WI (mem mode (add sr slo16))))
((m32r/d (unit u-load (cycles 2)))
- (m32rx (unit u-load (cycles 2))))
+ (m32rx (unit u-load (cycles 2)))
+ (m32r2 (unit u-load (cycles 2))))
)
(dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
(NO-DIS (IDOC MEM))
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
(m32rx (unit u-load)
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
+ (m32r2 (unit u-load)
+ (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
)
)
(set (reg h-lock) (const BI 1))
(set dr (mem WI sr)))
((m32r/d (unit u-load))
- (m32rx (unit u-load)))
+ (m32rx (unit u-load))
+ (m32r2 (unit u-load)))
)
(dni machi "machi"
)
(dni machi-a "machi-a"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"machi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 4) src2)
(set acc
(ext DI (trunc HI (sra WI src2 (const 16))))))
(const 8))
(const 8)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni maclo "maclo"
)
(dni maclo-a "maclo-a"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 5) src2)
(set acc
(ext DI (trunc HI src2))))
(const 8))
(const 8)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni macwhi "macwhi"
)
(dni macwhi-a "macwhi-a"
- ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
"macwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 6) src2)
; Note that this doesn't do the sign extension, which is correct.
(add acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16)))))))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni macwlo "macwlo"
)
(dni macwlo-a "macwlo-a"
- ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
"macwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 7) src2)
; Note that this doesn't do the sign extension, which is correct.
(add acc
(mul (ext DI src1)
(ext DI (trunc HI src2)))))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni mul "mul"
(+ OP1_1 OP2_6 dr sr)
(set dr (mul dr sr))
((m32r/d (unit u-exec (cycles 4)))
- (m32rx (unit u-exec (cycles 4))))
+ (m32rx (unit u-exec (cycles 4)))
+ (m32r2 (unit u-exec (cycles 4))))
)
(dni mulhi "mulhi"
)
(dni mulhi-a "mulhi-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mulhi $src1,$src2,$acc"
(+ OP1_3 (f-op23 0) src1 acc src2)
(set acc
(ext DI (trunc HI (sra WI src2 (const 16)))))
(const 16))
(const 16)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni mullo "mullo"
)
(dni mullo-a "mullo-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mullo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 1) src2)
(set acc
(ext DI (trunc HI src2)))
(const 16))
(const 16)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni mulwhi "mulwhi"
)
(dni mulwhi-a "mulwhi-a"
- ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 2) src2)
; Note that this doesn't do the sign extension, which is correct.
(set acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16))))))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni mulwlo "mulwlo"
)
(dni mulwlo-a "mulwlo-a"
- ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 3) src2)
; Note that this doesn't do the sign extension, which is correct.
(set acc
(mul (ext DI src1)
(ext DI (trunc HI src2))))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dni mv "mv"
)
(dni mvfachi-a "mvfachi-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfachi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 0))
(set dr (trunc WI (sra DI accs (const 32))))
- ((m32rx (unit u-exec (cycles 2))))
+ ((m32rx (unit u-exec (cycles 2)))
+ (m32r2 (unit u-exec (cycles 2))))
)
(dni mvfaclo "mvfaclo"
)
(dni mvfaclo-a "mvfaclo-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfaclo $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 1))
(set dr (trunc WI accs))
- ((m32rx (unit u-exec (cycles 2))))
+ ((m32rx (unit u-exec (cycles 2)))
+ (m32r2 (unit u-exec (cycles 2))))
)
(dni mvfacmi "mvfacmi"
)
(dni mvfacmi-a "mvfacmi-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfacmi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 2))
(set dr (trunc WI (sra DI accs (const 16))))
- ((m32rx (unit u-exec (cycles 2))))
+ ((m32rx (unit u-exec (cycles 2)))
+ (m32r2 (unit u-exec (cycles 2))))
)
(dni mvfc "mvfc"
)
(dni mvtachi-a "mvtachi-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvtachi $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 0))
(set accs
(or DI
(and DI accs (const DI #xffffffff))
(sll DI (ext DI src1) (const 32))))
- ((m32rx (unit u-exec (in sr src1))))
+ ((m32rx (unit u-exec (in sr src1)))
+ (m32r2 (unit u-exec (in sr src1))))
)
(dni mvtaclo "mvtaclo"
)
(dni mvtaclo-a "mvtaclo-a"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvtaclo $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 1))
(set accs
(or DI
(and DI accs (const DI #xffffffff00000000))
(zext DI src1)))
- ((m32rx (unit u-exec (in sr src1))))
+ ((m32rx (unit u-exec (in sr src1)))
+ (m32r2 (unit u-exec (in sr src1))))
)
(dni mvtc "mvtc"
; FIXME: quick hack: parallel nops don't contribute to cycle count.
; Other kinds of nops do however (which we currently ignore).
((m32r/d (unit u-exec (cycles 0)))
- (m32rx (unit u-exec (cycles 0))))
+ (m32rx (unit u-exec (cycles 0)))
+ (m32r2 (unit u-exec (cycles 0))))
)
(dni not "not"
)
(dni rac-dsi "rac-dsi"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffffffff0000)))))
)
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dnmi rac-d "rac-d"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd"
(emit rac-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rac-ds "rac-ds"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd,$accs"
(emit rac-dsi accd accs (f-imm1 0))
)
)
(dni rach-dsi "rach-dsi"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffff00000000)))))
)
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
(dnmi rach-d "rach-d"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd"
(emit rach-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rach-ds "rach-ds"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd,$accs"
(emit rach-dsi accd accs (f-imm1 0))
)
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
(begin
- (dni sym sym ((PIPE O) (IDOC ALU))
+ (dni sym sym ((PIPE O_OS) (IDOC ALU))
(.str sym " $dr,$sr")
(+ OP1_1 op2-r-op dr sr)
(set dr (sem-op dr (and sr (const 31))))
(set dr (sem-op sr (and WI simm16 (const 31))))
()
)
- (dni (.sym sym "i") sym ((PIPE O) (IDOC ALU))
+ (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
(.str sym "i $dr,$uimm5")
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
(set dr (sem-op dr uimm5))
(+ OP1_2 op2-op src1 src2)
(set mode (mem mode src2) src1)
((m32r/d (unit u-store (cycles 1)))
- (m32rx (unit u-store (cycles 1))))
+ (m32rx (unit u-store (cycles 1)))
+ (m32r2 (unit u-store (cycles 1))))
)
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
(+ OP1_10 op2-op src1 src2 slo16)
(set mode (mem mode (add src2 slo16)) src1)
((m32r/d (unit u-store (cycles 2)))
- (m32rx (unit u-store (cycles 2))))
+ (m32rx (unit u-store (cycles 2)))
+ (m32r2 (unit u-store (cycles 2))))
)
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
(NO-DIS (IDOC MEM))
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ )
+)
+
+(dni sth-plus "sth+"
+ ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
+ "sth $src1,@$src2+"
+ (+ OP1_2 OP2_3 src1 src2)
+ ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+ (sequence ((HI new-src2))
+ (set (mem HI new-src2) src1)
+ (set new-src2 (add src2 (const 2)))
+ (set src2 new-src2))
+ ((m32rx (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ )
+)
+
+(dni stb-plus "stb+"
+ ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
+ "stb $src1,@$src2+"
+ (+ OP1_2 OP2_1 src1 src2)
+ ; This has to be coded carefully to avoid an "earlyclobber" of src2.
+ (sequence ((QI new-src2))
+ (set (mem QI new-src2) src1)
+ (set new-src2 (add src2 (const 1)))
+ (set src2 new-src2))
+ ((m32rx (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
+ (m32r2 (unit u-store)
+ (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
-(dnmi push "push" ((IDOC MEM))
+(dnmi push "push" ((PIPE O) (IDOC MEM))
"push $src1"
(emit st-minus src1 (src2 15)) ; "st %0,@-sp"
)
(set (mem WI src2) src1))
(set (reg h-lock) (const BI 0)))
((m32r/d (unit u-load))
- (m32rx (unit u-load)))
+ (m32rx (unit u-load))
+ (m32r2 (unit u-load)))
)
; Saturate into byte.
(dni satb "satb"
- ((MACH m32rx) (IDOC ALU))
+ ((MACH m32rx,m32r2) (IDOC ALU))
"satb $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
(set dr
; Saturate into half word.
(dni sath "sath"
- ((MACH m32rx) (IDOC ALU))
+ ((MACH m32rx,m32r2) (IDOC ALU))
"sath $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
(set dr
; Saturate word.
(dni sat "sat"
- ((MACH m32rx) SPECIAL (IDOC ALU))
+ ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
"sat $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
(set dr
; Parallel compare byte zeros.
; Set C bit in condition register if any byte in source register is zero.
(dni pcmpbz "pcmpbz"
- ((MACH m32rx) (PIPE OS) SPECIAL (IDOC ALU))
+ ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
"pcmpbz $src2"
(+ OP1_0 (f-r1 3) OP2_7 src2)
(set condbit
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
(else (const BI 0))))
- ((m32rx (unit u-cmp)))
+ ((m32rx (unit u-cmp))
+ (m32r2 (unit u-cmp)))
)
; Add accumulators
(dni sadd "sadd"
- ((MACH m32rx) (PIPE S) (IDOC ACCUM))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"sadd"
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
(set (reg h-accums 0)
(add (sra (reg h-accums 1) (const 16))
(reg h-accums 0)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni macwu1 "macwu1"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"macwu1 $src1,$src2"
(+ OP1_5 src1 OP2_11 src2)
(set (reg h-accums 1)
(ext DI (and src2 (const #xffff)))))
(const 8))
(const 8)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
; Multiply and subtract from accumulator 0
(dni msblo "msblo"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"msblo $src1,$src2"
(+ OP1_5 src1 OP2_13 src2)
(set accum
(const 16)))
(const 8))
(const 8)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
; Multiply into accumulator 1
(dni mulwu1 "mulwu1"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"mulwu1 $src1,$src2"
(+ OP1_5 src1 OP2_10 src2)
(set (reg h-accums 1)
(ext DI (and src2 (const #xffff))))
(const 16))
(const 16)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni maclh1 "maclh1"
- ((MACH m32rx) (PIPE S) (IDOC MAC))
+ ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclh1 $src1,$src2"
(+ OP1_5 src1 OP2_12 src2)
(set (reg h-accums 1)
(const 16)))
(const 8))
(const 8)))
- ((m32rx (unit u-mac)))
+ ((m32rx (unit u-mac))
+ (m32r2 (unit u-mac)))
)
; skip instruction if C
(dni sc "sc"
- ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
+ ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"sc"
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
(skip (zext INT condbit))
; skip instruction if not C
(dni snc "snc"
- ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
+ ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"snc"
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
(skip (zext INT (not condbit)))
()
)
+
+; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
+(dni clrpsw "clrpsw"
+ ((PIPE O) SPECIAL_M32R)
+ "clrpsw $uimm8"
+ (+ OP1_7 (f-r1 2) uimm8)
+ (set USI (reg h-cr 0)
+ (and USI (reg h-cr 0)
+ (or USI (inv BI uimm8) (const #xff00))))
+ ()
+)
+
+; PSW |= (unsigned char) uimm8
+(dni setpsw "setpsw"
+ ((PIPE O) SPECIAL_M32R)
+ "setpsw $uimm8"
+ (+ OP1_7 (f-r1 1) uimm8)
+ (set USI (reg h-cr 0) uimm8)
+ ()
+)
+
+; bset
+(dni bset "bset"
+ (SPECIAL_M32R)
+ "bset $uimm3,@($slo16,$sr)"
+ (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
+ (set QI (mem QI (add sr slo16))
+ (or QI (mem QI (add sr slo16))
+ (sll USI (const 1) (sub (const 7) uimm3))))
+ ()
+)
+
+; bclr
+(dni bclr "bclr"
+ (SPECIAL_M32R)
+ "bclr $uimm3,@($slo16,$sr)"
+ (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
+ (set QI (mem QI (add sr slo16))
+ (and QI (mem QI (add sr slo16))
+ (inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
+ ()
+)
+
+; btst
+(dni btst "btst"
+ (SPECIAL_M32R (PIPE O))
+ "btst $uimm3,$sr"
+ (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
+ (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
+ ()
+)
+
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
+#if 0
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+#else
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
+extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+#endif
/* -- */
\f
+/* -- opc.c */
+unsigned int
+m32r_cgen_dis_hash (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value;
+{
+ unsigned int x;
+
+ if (value & 0xffff0000) /* 32bit instructions */
+ value = (value >> 16) & 0xffff;
+
+ x = (value>>8) & 0xf0;
+ if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+ return x;
+
+ if (x == 0x70 || x == 0xf0)
+ return x | ((value>>8) & 0x0f);
+
+ if (x == 0x30)
+ return x | ((value & 0x70) >> 4);
+ else
+ return x | ((value & 0xf0) >> 4);
+}
+
+/* -- */
+\f
/* -- asm.c */
static const char * parse_hash
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
- value &= 0xffff;
+ {
+ value &= 0xffff;
+ if (value & 0x8000)
+ value |= 0xffff0000;
+ }
*valuep = value;
return errmsg;
}
char *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+ char *x;
/* Read the base part of the insn. */
}
/* 32 bit insn? */
- if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+ x = (big_p ? &buf[0] : &buf[3]);
+ if ((pc & 3) == 0 && (*x & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
+ buf += (big_p ? 0 : 2);
if ((pc & 3) == 0)
{
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- buf += 2;
}
+ buf += (big_p ? 2 : -2);
- if (buf[0] & 0x80)
+ x = (big_p ? &buf[0] : &buf[1]);
+ if (*x & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
- buf[0] &= 0x7f;
+ *x &= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
+2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * config/tc-m32r.h : Add support for new machine m32r2.
+ * config/tc-m32r.c : Likewise.
+ Add new command line switches and directives to allow endian-ness
+ to be selected and some warnings to be turned into errors.
+ (line_separator_chars) : Use '!'.
+ * doc/c-m32r.texi: Document new switches and directives.
+
2003-12-03 Dave Airlie <airlied@linux.ie>
* configure.in: Likewise.
#include "opcodes/m32r-desc.h"
#include "opcodes/m32r-opc.h"
#include "cgen.h"
+#include "elf/m32r.h"
/* Linked list of symbols that are debugging symbols to be defined as the
beginning of the current instruction. */
shouldn't assume or require it to). */
static int warn_unmatched_high = 0;
-/* Non-zero if -m32rx has been specified, in which case support for the
- extended M32RX instruction set should be enabled. */
-static int enable_m32rx = 0;
+/* 1 if -m32rx has been specified, in which case support for
+ the extended M32RX instruction set should be enabled.
+ 2 if -m32r2 has been specified, in which case support for
+ the extended M32R2 instruction set should be enabled. */
+static int enable_m32rx = 0; /* Default to M32R. */
/* Non-zero if -m32rx -hidden has been specified, in which case support for
the special M32RX instruction set should be enabled. */
static int enable_special = 0;
+/* Non-zero if -bitinst has been specified, in which case support
+ for extended M32R bit-field instruction set should be enabled. */
+static int enable_special_m32r = 0;
+
+/* Non-zero if -float has been specified, in which case support for
+ extended M32R floating point instruction set should be enabled. */
+static int enable_special_float = 0;
+
/* Non-zero if the programmer should be warned when an explicit parallel
instruction might have constraint violations. */
static int warn_explicit_parallel_conflicts = 1;
+/* Non-zero if the programmer should receive an error message when an
+ explicit parallel instruction might have constraint violations. */
+static int error_explicit_parallel_conflicts = 1;
+
/* Non-zero if insns can be made parallel. */
+static int use_parallel = 1;
+
+/* Non-zero if optimizations should be performed. */
static int optimize;
+/* m32r er_flags. */
+static int m32r_flags = 0;
+
/* Stuff for .scomm symbols. */
static segT sbss_section;
static asection scom_section;
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = "!";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
static struct m32r_hi_fixup *m32r_hi_fixup_list;
\f
-static void allow_m32rx PARAMS ((int));
+struct {
+ enum bfd_architecture bfd_mach;
+ int mach_flags;
+} mach_table[] =
+{
+ { bfd_mach_m32r, (1<<MACH_M32R) },
+ { bfd_mach_m32rx, (1<<MACH_M32RX) },
+ { bfd_mach_m32r2, (1<<MACH_M32R2) }
+};
+
+static void allow_m32rx (int);
static void
-allow_m32rx (on)
- int on;
+allow_m32rx (int on)
{
enable_m32rx = on;
if (stdoutput != NULL)
- bfd_set_arch_mach (stdoutput, TARGET_ARCH,
- enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
+ bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
+
+ if (gas_cgen_cpu_desc != NULL)
+ gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
}
\f
#define M32R_SHORTOPTS "O"
struct option md_longopts[] =
{
-#define OPTION_M32R (OPTION_MD_BASE)
-#define OPTION_M32RX (OPTION_M32R + 1)
-#define OPTION_WARN_PARALLEL (OPTION_M32RX + 1)
-#define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
-#define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1)
-#define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1)
+#define OPTION_M32R (OPTION_MD_BASE)
+#define OPTION_M32RX (OPTION_M32R + 1)
+#define OPTION_M32R2 (OPTION_M32RX + 1)
+#define OPTION_BIG (OPTION_M32R2 + 1)
+#define OPTION_LITTLE (OPTION_BIG + 1)
+#define OPTION_PARALLEL (OPTION_LITTLE + 1)
+#define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
+#define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
+#define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
+#define OPTION_ERROR_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
+#define OPTION_NO_ERROR_PARALLEL (OPTION_ERROR_PARALLEL + 1)
+#define OPTION_SPECIAL (OPTION_NO_ERROR_PARALLEL + 1)
+#define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
+#define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1)
+#define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
#define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
{"m32r", no_argument, NULL, OPTION_M32R},
{"m32rx", no_argument, NULL, OPTION_M32RX},
+ {"m32r2", no_argument, NULL, OPTION_M32R2},
+ {"big", no_argument, NULL, OPTION_BIG},
+ {"little", no_argument, NULL, OPTION_LITTLE},
+ {"EB", no_argument, NULL, OPTION_BIG},
+ {"EL", no_argument, NULL, OPTION_LITTLE},
+ {"parallel", no_argument, NULL, OPTION_PARALLEL},
+ {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
+ {"error-explicit-parallel-conflicts", no_argument, NULL, OPTION_ERROR_PARALLEL},
+ {"Ep", no_argument, NULL, OPTION_ERROR_PARALLEL},
+ {"no-error-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},
+ {"Enp", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},
{"hidden", no_argument, NULL, OPTION_SPECIAL},
+ {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
+ {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
/* Sigh. I guess all warnings must now have both variants. */
{"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
size_t md_longopts_size = sizeof (md_longopts);
+static void little (int);
+static int parallel (void);
+
+static void
+little (int on)
+{
+ target_big_endian = ! on;
+}
+
+/* Use parallel execution. */
+
+static int
+parallel (void)
+{
+ if (! enable_m32rx)
+ return 0;
+
+ if (use_parallel == 1)
+ return 1;
+
+ return 0;
+}
+
int
md_parse_option (c, arg)
int c;
{
case 'O':
optimize = 1;
+ use_parallel = 1;
break;
case OPTION_M32R:
allow_m32rx (1);
break;
+ case OPTION_M32R2:
+ allow_m32rx (2);
+ enable_special = 1;
+ enable_special_m32r = 1;
+ break;
+
+ case OPTION_BIG:
+ target_big_endian = 1;
+ break;
+
+ case OPTION_LITTLE:
+ target_big_endian = 0;
+ break;
+
+ case OPTION_PARALLEL:
+ use_parallel = 1;
+ break;
+
+ case OPTION_NO_PARALLEL:
+ use_parallel = 0;
+ break;
+
case OPTION_WARN_PARALLEL:
warn_explicit_parallel_conflicts = 1;
+ error_explicit_parallel_conflicts = 0;
break;
case OPTION_NO_WARN_PARALLEL:
warn_explicit_parallel_conflicts = 0;
+ error_explicit_parallel_conflicts = 0;
+ break;
+
+ case OPTION_ERROR_PARALLEL:
+ warn_explicit_parallel_conflicts = 1;
+ error_explicit_parallel_conflicts = 1;
+ break;
+
+ case OPTION_NO_ERROR_PARALLEL:
+ error_explicit_parallel_conflicts = 0;
+ warn_explicit_parallel_conflicts = 0;
break;
case OPTION_SPECIAL:
}
break;
+ case OPTION_SPECIAL_M32R:
+ enable_special_m32r = 1;
+ break;
+
+ case OPTION_SPECIAL_FLOAT:
+ enable_special_float = 1;
+ break;
+
case OPTION_WARN_UNMATCHED:
warn_unmatched_high = 1;
break;
fprintf (stream, _("\
-m32rx support the extended m32rx instruction set\n"));
fprintf (stream, _("\
- -O try to combine instructions in parallel\n"));
+ -m32r2 support the extended m32r2 instruction set\n"));
+ fprintf (stream, _("\
+ -EL,-little produce little endian code and data\n"));
+ fprintf (stream, _("\
+ -EB,-big produce big endian code and data\n"));
+ fprintf (stream, _("\
+ -parallel try to combine instructions in parallel\n"));
+ fprintf (stream, _("\
+ -no-parallel disable -parallel\n"));
+ fprintf (stream, _("\
+ -O try to optimize code. Implies -parallel\n"));
fprintf (stream, _("\
-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
+ fprintf (stream, _("\
+ -error-explicit-parallel-conflicts error when parallel instructions\n"));
+ fprintf (stream, _("\
+ violate contraints\n"));
+ fprintf (stream, _("\
+ -no-error-explicit-parallel-conflicts do not error when parallel\n"));
+ fprintf (stream, _("\
+ instructions violate contraints\n"));
+ fprintf (stream, _("\
+ -Ep synonym for -error-explicit-parallel-conflicts\n"));
+ fprintf (stream, _("\
+ -Enp synonym for -no-error-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
{ "fillinsn", fill_insn, 0 },
{ "scomm", m32r_scomm, 0 },
{ "debugsym", debug_sym, 0 },
- /* Not documented as so far there is no need for them.... */
{ "m32r", allow_m32rx, 0 },
{ "m32rx", allow_m32rx, 1 },
+ { "m32r2", allow_m32rx, 2 },
+ { "little", little, 1 },
+ { "big", little, 0 },
{ NULL, NULL, 0 }
};
/* FIXME: Should be machine generated. */
-#define NOP_INSN 0x7000
+#define NOP_INSN 0x7000
#define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
input_line_pointer = save_input_line;
}
+void
+m32r_flush_pending_output()
+{
+ if (debug_sym_link)
+ {
+ expand_debug_syms (debug_sym_link, 1);
+ debug_sym_link = (sym_linkS *) 0;
+ }
+}
+
/* Cover function to fill_insn called after a label and at end of assembly.
The result is always 1: we're called in a conditional to see if the
current line is a label. */
return 1;
}
\f
+/* The default target format to use. */
+
+const char *
+m32r_target_format ()
+{
+#ifdef TE_LINUX
+ if (target_big_endian)
+ return "elf32-m32r-linux";
+ else
+ return "elf32-m32rle-linux";
+#else
+ if (target_big_endian)
+ return "elf32-m32r";
+ else
+ return "elf32-m32rle";
+#endif
+}
+
void
md_begin ()
{
/* Set the machine number and endian. */
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
- CGEN_ENDIAN_BIG,
+ (target_big_endian ?
+ CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
CGEN_CPU_OPEN_END);
m32r_cgen_init_asm (gas_cgen_cpu_desc);
go away if the instructions are swapped, and we want to make
sure that any other errors are detected before this happens. */
if (a_pipe == PIPE_S
- || b_pipe == PIPE_O)
+ || b_pipe == PIPE_O
+ || (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
return _("Instructions share the same execution pipeline");
return NULL;
as_bad (_("not a 16 bit instruction '%s'"), str);
return;
}
+#ifdef E_M32R2_ARCH
+ else if ((enable_m32rx == 1)
+ /* FIXME: Need standard macro to perform this test. */
+ && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32R2))
+ && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32RX)))))
+ {
+ /* xgettext:c-format */
+ as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ return;
+ }
+ else if ((! enable_special
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
+ || (! enable_special_m32r
+ && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
+#else
else if (! enable_special
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
+#endif
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
as_bad (_("not a 16 bit instruction '%s'"), str);
return;
}
+#ifdef E_M32R2_ARCH
+ else if ((enable_m32rx == 1)
+ /* FIXME: Need standard macro to perform this test. */
+ && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32R2))
+ && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32RX)))))
+ {
+ /* xgettext:c-format */
+ as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ return;
+ }
+ else if ((! enable_special
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
+ || (! enable_special_m32r
+ && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
+#else
else if (! enable_special
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
+#endif
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
if (parallel_p && warn_explicit_parallel_conflicts)
{
+ void (* func)(const char *, ...);
+
+ func = error_explicit_parallel_conflicts ? as_bad : as_warn;
+
if (first_writes_to_seconds_operands (&first, &second, FALSE))
/* xgettext:c-format */
- as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
+ func (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
if (first_writes_to_seconds_operands (&second, &first, FALSE))
/* xgettext:c-format */
- as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
+ func (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
}
if (!parallel_p
return;
}
+ if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
+ || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
+ m32r_flags |= E_M32R_HAS_HIDDEN_INST;
+ if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
+ || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
+ m32r_flags |= E_M32R_HAS_BIT_INST;
+ if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
+ || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
+ m32r_flags |= E_M32R_HAS_FLOAT_INST;
+
/* Set these so m32r_fill_insn can use them. */
prev_seg = now_seg;
prev_subseg = now_subseg;
if ((str2 = strstr (str, "||")) != NULL)
{
assemble_two_insns (str, str2, 1);
+ m32r_flags |= E_M32R_HAS_PARALLEL;
return;
}
return;
}
+#ifdef E_M32R2_ARCH
+ if ((enable_m32rx == 1)
+ /* FIXME: Need standard macro to perform this test. */
+ && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32R2))
+ && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
+ & (1 << MACH_M32RX)))))
+ {
+ /* xgettext:c-format */
+ as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ return;
+ }
+ else if ((! enable_special
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
+ || (! enable_special_m32r
+ && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
+#else
if (! enable_special
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
+#endif
{
/* xgettext:c-format */
as_bad (_("unknown instruction '%s'"), str);
return;
}
+ if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
+ m32r_flags |= E_M32R_HAS_HIDDEN_INST;
+ if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
+ m32r_flags |= E_M32R_HAS_BIT_INST;
+ if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
+ m32r_flags |= E_M32R_HAS_FLOAT_INST;
+
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
{
/* 32 bit insns must live on 32 bit boundaries. */
Otherwise call can_make_parallel() with both orderings of the
instructions to see if they can be combined. */
if (! on_32bit_boundary_p
- && enable_m32rx
- && optimize
+ && parallel ()
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
&& ! writes_to_pc (&prev_insn)
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
return 1;
}
+
+void
+m32r_elf_final_processing ()
+{
+ if (use_parallel)
+ m32r_flags |= E_M32R_HAS_PARALLEL;
+ elf_elfheader (stdoutput)->e_flags |= m32r_flags;
+}
/* tc-m32r.h -- Header file for tc-m32r.c.
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#define TC_M32R
#ifndef BFD_ASSEMBLER
-/* leading space so will compile with cc */
+/* Leading space so will compile with cc. */
#error M32R support requires BFD_ASSEMBLER
#endif
-#define LISTING_HEADER "M32R GAS "
+#define LISTING_HEADER \
+ (target_big_endian ? "M32R GAS" : "M32R GAS Little Endian")
/* The target BFD architecture. */
#define TARGET_ARCH bfd_arch_m32r
-#define TARGET_FORMAT "elf32-m32r"
+/* The endianness of the target format may change based on command
+ line arguments. */
+#define TARGET_FORMAT m32r_target_format()
+extern const char *m32r_target_format PARAMS ((void));
+/* Default to big endian. */
+#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 1
+#endif
-/* call md_pcrel_from_section, not md_pcrel_from */
+/* Call md_pcrel_from_section, not md_pcrel_from. */
long md_pcrel_from_section PARAMS ((struct fix *, segT));
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
#define md_cleanup m32r_elf_section_change_hook
#define md_elf_section_change_hook m32r_elf_section_change_hook
extern void m32r_elf_section_change_hook PARAMS ((void));
+
+#define md_flush_pending_output() m32r_flush_pending_output ()
+extern void m32r_flush_pending_output PARAMS ((void));
+
+#define elf_tc_final_processing m32r_elf_final_processing
+extern void m32r_elf_final_processing PARAMS ((void));
dependent options:
@table @code
+
@item -m32rx
@cindex @samp{-m32rx} option, M32RX
@cindex architecture options, M32RX
basic M32R instruction set, and some additional parameters to some of
the original instructions.
+@item -m32r2
+@cindex @samp{-m32rx} option, M32R2
+@cindex architecture options, M32R2
+@cindex M32R architecture options
+This option changes the target processor to the the M32R2
+microprocessor.
+
@item -m32r
@cindex @samp{-m32r} option, M32R
@cindex architecture options, M32R
assembling for the M32R microprocessor. This can be useful if the
default has been changed by a previous command line option.
+@item -little
+@cindex @code{-little} option, M32R
+This option tells the assembler to produce little-endian code and
+data. The default is dependent upon how the toolchain was
+configured.
+
+@item -EL
+@cindex @code{-EL} option, M32R
+This is a synonum for @emph{-little}.
+
+@item -big
+@cindex @code{-big} option, M32R
+This option tells the assembler to produce big-endian code and
+data.
+
+@item -EB
+@cindex @code{-EB} option, M32R
+This is a synonum for @emph{-big}.
+
+@item -parallel
+@cindex @code{-parallel} option, M32RX
+This option tells the assembler to attempts to combine two sequential
+instructions into a single, parallel instruction, where it is legal to
+do so.
+
+@item -no-parallel
+@cindex @code{-no-parallel} option, M32RX
+This option disables a previously enabled @emph{-parallel} option.
+
+@item -O
+@cindex @code{-O} option, M32RX
+This option tells the assembler to attempt to optimize the
+instructions that it produces. This includes filling delay slots and
+converting sequential instructions into parallel ones. This option
+implies @emph{-parallel}.
+
@item -warn-explicit-parallel-conflicts
@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX
Instructs @code{@value{AS}} to produce warning messages when
This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts}
option.
+@item -error-explicit-parallel-conflicts
+@cindex @samp{-error-explicit-parallel-conflicts} option, M32RX
+This option performs the same thing as the
+@emph{-warn-explicit-parallel-conflicts} expcept that instead of
+warning messages being produced, error messages will be produced. If
+any error messages are generated then GAS will not produce an output
+file.
+
+@item -no-error-explicit-parallel-conflicts
+@cindex @samp{-no-error-explicit-parallel-conflicts} option, M32RX
+This option disables a previously enabled
+@emph{-error-explicit-parallel-conflicts} option.
+
+@item -Ep
+@cindex @samp{-Ep} option, M32RX
+This is a shorter synonym for the @emph{-error-explicit-parallel-conflicts}
+option.
+
+@item -Enp
+@cindex @samp{-Enp} option, M32RX
+This is a shorter synonym for the @emph{-no-error-explicit-parallel-conflicts}
+option.
+
+@item -warn-unmatched-high
+@cindex @samp{-warn-unmatched-high} option, M32R
+This option tells the assembler to produce a warning message if a
+@code{.high} pseudo op is encountered without a mathcing @code{.low}
+pseudo op. The presence of such an unmatches pseudo op usually
+indicates a programming error.
+
+@item -no-warn-unmatched-high
+@cindex @samp{-no-warn-unmatched-high} option, M32R
+Disables a previously enabled @emph{-warn-unmatched-high} option.
+
+@item -Wuh
+@cindex @samp{-Wuh} option, M32RX
+This is a shorter synonym for the @emph{-warn-unmatched-high} option.
+
+@item -Wnuh
+@cindex @samp{-Wnuh} option, M32RX
+This is a shorter synonym for the @emph{-no-warn-unmatched-high} option.
+
@end table
@node M32R-Directives
specific directives:
@table @code
-@cindex @code{.low} directive, M32R
-@item .low @var{expression}
-The @code{.low} directive computes the value of its expression and
+
+@cindex @code{low} directive, M32R
+@item low @var{expression}
+The @code{low} directive computes the value of its expression and
places the lower 16-bits of the result into the immediate-field of the
instruction. For example:
add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
@end smallexample
-@item .high @var{expression}
-@cindex @code{.high} directive, M32R
-The @code{.high} directive computes the value of its expression and
+@item high @var{expression}
+@cindex @code{high} directive, M32R
+The @code{high} directive computes the value of its expression and
places the upper 16-bits of the result into the immediate-field of the
instruction. For example:
seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
@end smallexample
-@item .shigh @var{expression}
-@cindex @code{.shigh} directive, M32R
-The @code{.shigh} directive is very similar to the @code{.high}
+@item shigh @var{expression}
+@cindex @code{shigh} directive, M32R
+The @code{shigh} directive is very similar to the @code{high}
directive. It also computes the value of its expression and places
the upper 16-bits of the result into the immediate-field of the
-instruction. The difference is that @code{.shigh} also checks to see
+instruction. The difference is that @code{shigh} also checks to see
if the lower 16-bits could be interpreted as a signed number, and if
so it assumes that a borrow will occur from the upper-16 bits. To
-compensate for this the @code{.shigh} directive pre-biases the upper
+compensate for this the @code{shigh} directive pre-biases the upper
16 bit value by adding one to it. For example:
For example:
check to make sure that an @code{or3} instruction is being used rather
than an @code{add3} instruction. It is up to the programmer to make
sure that correct directives are used.
+
+@cindex @code{.m32r} directive, M32R
+@item .m32r
+The directive performs a similar thing as the @emph{-m32r} command
+line option. It tells the assembler to only accept M32R instructions
+from now on. An instructions from later M32R architectures are
+refused.
+
+@cindex @code{.m32rx} directive, M32RX
+@item .m32rx
+The directive performs a similar thing as the @emph{-m32rx} command
+line option. It tells the assembler to start accepting the extra
+instructions in the M32RX ISA as well as the ordinary M32R ISA.
+
+@cindex @code{.m32r2} directive, M32R2
+@item .m32r2
+The directive performs a similar thing as the @emph{-m32r2} command
+line option. It tells the assembler to start accepting the extra
+instructions in the M32R2 ISA as well as the ordinary M32R ISA.
+
+@cindex @code{.little} directive, M32RX
+@item .little
+The directive performs a similar thing as the @emph{-little} command
+line option. It tells the assembler to start producing little-endian
+code and data. This option should be used with care as producing
+mixed-endian binary files is frought with danger.
+
+@cindex @code{.big} directive, M32RX
+@item .big
+The directive performs a similar thing as the @emph{-big} command
+line option. It tells the assembler to start producing big-endian
+code and data. This option should be used with care as producing
+mixed-endian binary files is frought with danger.
+
@end table
@node M32R-Warnings
+2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * gas/m32r/m32r2.exp: New file for m32r2.
+ * gas/m32r/m32r2.s: Likewise.
+ * gas/m32r/m32r2.d: Likewise.
+
2003-12-03 Nick Clifton <nickc@redhat.com>
* gas/vax/vax.exp (do_quad): Treat a vax-*-linux-gnu target as an
--- /dev/null
+#as: -m32r2
+#objdump: -dr
+#name: m32r2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <setpsw>:
+ 0: 71 c1 71 ff setpsw #0xc1 -> setpsw #0xff
+
+0+0004 <clrpsw>:
+ 4: 72 c1 72 ff clrpsw #0xc1 -> clrpsw #0xff
+
+0+0008 <bset>:
+ 8: a0 61 00 04 bset #0x0,@\(4,r1\)
+ c: a1 61 00 04 bset #0x1,@\(4,r1\)
+ 10: a7 61 00 04 bset #0x7,@\(4,r1\)
+
+0+0014 <bclr>:
+ 14: a0 71 00 04 bclr #0x0,@\(4,r1\)
+ 18: a1 71 00 04 bclr #0x1,@\(4,r1\)
+ 1c: a7 71 00 04 bclr #0x7,@\(4,r1\)
+
+0+0020 <btst>:
+ 20: 00 fd 01 fd btst #0x0,fp -> btst #0x1,fp
+ 24: 07 fd f0 00 btst #0x7,fp \|\| nop
+ 28: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2
+ 2c: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2
+
+0+0030 <divuh>:
+ 30: 9d 1d 00 10 divuh fp,fp
+
+0+0034 <divb>:
+ 34: 9d 0d 00 18 divb fp,fp
+
+0+0038 <divub>:
+ 38: 9d 1d 00 18 divub fp,fp
+
+0+003c <remh>:
+ 3c: 9d 2d 00 10 remh fp,fp
+
+0+0040 <remuh>:
+ 40: 9d 3d 00 10 remuh fp,fp
+
+0+0044 <remb>:
+ 44: 9d 2d 00 18 remb fp,fp
+
+0+0048 <remub>:
+ 48: 9d 3d 00 18 remub fp,fp
+
+0+004c <sll>:
+ 4c: 10 41 92 43 sll r0,r1 \|\| sll r2,r3
+ 50: 12 43 90 61 sll r2,r3 \|\| mul r0,r1
+ 54: 10 41 92 63 sll r0,r1 \|\| mul r2,r3
+ 58: 60 01 92 43 ldi r0,#1 \|\| sll r2,r3
+ 5c: 10 41 e2 01 sll r0,r1 \|\| ldi r2,#1
+
+0+0060 <slli>:
+ 60: 50 41 d2 5f slli r0,#0x1 \|\| slli r2,#0x1f
+ 64: 52 5f 90 61 slli r2,#0x1f \|\| mul r0,r1
+ 68: 50 41 92 63 slli r0,#0x1 \|\| mul r2,r3
+ 6c: 60 01 d2 5f ldi r0,#1 \|\| slli r2,#0x1f
+ 70: 50 41 e2 01 slli r0,#0x1 \|\| ldi r2,#1
+
+0+0074 <sra>:
+ 74: 10 21 92 23 sra r0,r1 \|\| sra r2,r3
+ 78: 12 23 90 61 sra r2,r3 \|\| mul r0,r1
+ 7c: 10 21 92 63 sra r0,r1 \|\| mul r2,r3
+ 80: 60 01 92 23 ldi r0,#1 \|\| sra r2,r3
+ 84: 10 21 e2 01 sra r0,r1 \|\| ldi r2,#1
+
+0+0088 <srai>:
+ 88: 50 21 d2 3f srai r0,#0x1 \|\| srai r2,#0x1f
+ 8c: 52 3f 90 61 srai r2,#0x1f \|\| mul r0,r1
+ 90: 50 21 92 63 srai r0,#0x1 \|\| mul r2,r3
+ 94: 60 01 d2 3f ldi r0,#1 \|\| srai r2,#0x1f
+ 98: 50 21 e2 01 srai r0,#0x1 \|\| ldi r2,#1
+
+0+009c <srl>:
+ 9c: 10 01 92 03 srl r0,r1 \|\| srl r2,r3
+ a0: 12 03 90 61 srl r2,r3 \|\| mul r0,r1
+ a4: 10 01 92 63 srl r0,r1 \|\| mul r2,r3
+ a8: 60 01 92 03 ldi r0,#1 \|\| srl r2,r3
+ ac: 10 01 e2 01 srl r0,r1 \|\| ldi r2,#1
+
+0+00b0 <srli>:
+ b0: 50 01 d2 1f srli r0,#0x1 \|\| srli r2,#0x1f
+ b4: 52 1f 90 61 srli r2,#0x1f \|\| mul r0,r1
+ b8: 50 01 92 63 srli r0,#0x1 \|\| mul r2,r3
+ bc: 60 01 d2 1f ldi r0,#1 \|\| srli r2,#0x1f
+ c0: 50 01 e2 01 srli r0,#0x1 \|\| ldi r2,#1
--- /dev/null
+# M32R2 assembler testsuite.
+
+if [istarget m32r*-*-*] {
+ run_dump_test "m32r2"
+}
--- /dev/null
+# Test new instructions
+
+ .text
+ .global setpsw
+setpsw:
+ setpsw 0xc1
+ setpsw 0xff
+
+ .text
+ .global clrpsw
+clrpsw:
+ clrpsw 0xc1
+ clrpsw 0xff
+
+ .text
+ .global bset
+bset:
+ bset #0,@(4,r1)
+ bset #1,@(4,r1)
+ bset #7,@(4,r1)
+
+ .text
+ .global bclr
+bclr:
+ bclr #0,@(4,r1)
+ bclr #1,@(4,r1)
+ bclr #7,@(4,r1)
+
+ .text
+ .global btst
+btst:
+ btst #0,fp
+ btst #1,fp
+ btst #7,fp
+ btst #1,fp || mv r0,r2
+ mv r0,r2 || btst #1,fp
+
+ .text
+ .global divuh
+divuh:
+ divuh fp,fp
+
+ .text
+ .global divb
+divb:
+ divb fp,fp
+
+ .text
+ .global divub
+divub:
+ divub fp,fp
+
+ .text
+ .global remh
+remh:
+ remh fp,fp
+
+ .text
+ .global remuh
+remuh:
+ remuh fp,fp
+
+ .text
+ .global remb
+remb:
+ remb fp,fp
+
+ .text
+ .global remub
+remub:
+ remub fp,fp
+
+ .text
+ .global sll
+sll:
+ sll r0,r1 || sll r2,r3
+ mul r0,r1 || sll r2,r3
+ sll r0,r1 || mul r2,r3
+ ldi r0,#1 || sll r2,r3
+ sll r0,r1 || ldi r2,#1
+
+ .text
+ .global slli
+slli:
+ slli r0,#1 || slli r2,#31
+ mul r0,r1 || slli r2,#31
+ slli r0,#1 || mul r2,r3
+ ldi r0,#1 || slli r2,#31
+ slli r0,#1 || ldi r2,#1
+
+ .text
+ .global sra
+sra:
+ sra r0,r1 || sra r2,r3
+ mul r0,r1 || sra r2,r3
+ sra r0,r1 || mul r2,r3
+ ldi r0,#1 || sra r2,r3
+ sra r0,r1 || ldi r2,#1
+
+ .text
+ .global srai
+srai:
+ srai r0,#1 || srai r2,#31
+ mul r0,r1 || srai r2,#31
+ srai r0,#1 || mul r2,r3
+ ldi r0,#1 || srai r2,#31
+ srai r0,#1 || ldi r2,#1
+
+ .text
+ .global sra
+srl:
+ srl r0,r1 || srl r2,r3
+ mul r0,r1 || srl r2,r3
+ srl r0,r1 || mul r2,r3
+ ldi r0,#1 || srl r2,r3
+ srl r0,r1 || ldi r2,#1
+
+ .text
+ .global srai
+srli:
+ srli r0,#1 || srli r2,#31
+ mul r0,r1 || srli r2,#31
+ srli r0,#1 || mul r2,r3
+ ldi r0,#1 || srli r2,#31
+ srli r0,#1 || ldi r2,#1
+
+2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * elf/m32r.h: Add new machine type m32r2 and instruction modes.
+
2003-11-06 Alan Modra <amodra@bigpond.net.au>
* ppc.h (R_PPC_RELAX32PC): Define.
/* M32R ELF support for BFD.
- Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _ELF_M32R_H
#define _ELF_M32R_H
/* m32r code. */
#define E_M32R_ARCH 0x00000000
/* m32rx code. */
-#define E_M32RX_ARCH 0x10000000
+#define E_M32RX_ARCH 0x10000000
+/* m32r2 code. */
+#define E_M32R2_ARCH 0x20000000
+
+/* 12 bit m32r new instructions field. */
+#define EF_M32R_INST 0x0FFF0000
+/* Parallel instructions. */
+#define E_M32R_HAS_PARALLEL 0x00010000
+/* Hidden instructions for m32rx:
+ jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz,
+ sc, snc. */
+#define E_M32R_HAS_HIDDEN_INST 0x00020000
+/* New bit instructions:
+ clrpsw, setpsw, bset, bclr, btst. */
+#define E_M32R_HAS_BIT_INST 0x00040000
+/* Floating point instructions. */
+#define E_M32R_HAS_FLOAT_INST 0x00080000
+
+/* 4 bit m32r ignore to check field. */
+#define EF_M32R_IGNORE 0x0000000F
#endif
+2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
+ * m32r-opinst.c: Regenerate.
+
2003-12-02 Kazu Hirata <kazu@cs.umass.edu>
* alpha-opc.c: Remove ARGSUSED.
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
- value &= 0xffff;
+ {
+ value &= 0xffff;
+ if (value & 0x8000)
+ value |= 0xffff0000;
+ }
*valuep = value;
return errmsg;
}
fields->f_uimm24 = value;
}
break;
+ case M32R_OPERAND_UIMM3 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM3, &fields->f_uimm3);
+ break;
case M32R_OPERAND_UIMM4 :
errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
break;
case M32R_OPERAND_UIMM5 :
errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
break;
+ case M32R_OPERAND_UIMM8 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM8, &fields->f_uimm8);
+ break;
case M32R_OPERAND_ULO16 :
errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
break;
{ "base", MACH_BASE },
{ "m32r", MACH_M32R },
{ "m32rx", MACH_M32RX },
+ { "m32r2", MACH_M32R2 },
{ "max", MACH_MAX },
{ 0, 0 }
};
{ "O", PIPE_O },
{ "S", PIPE_S },
{ "OS", PIPE_OS },
+ { "O_OS", PIPE_O_OS },
{ 0, 0 }
};
{ "PBB", &bool_attr[0], &bool_attr[0] },
{ "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
{ "SPECIAL", &bool_attr[0], &bool_attr[0] },
+ { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
+ { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
static const CGEN_MACH m32r_cgen_mach_table[] = {
{ "m32r", "m32r", MACH_M32R, 0 },
{ "m32rx", "m32rx", MACH_M32RX, 0 },
+ { "m32r2", "m32r2", MACH_M32R2, 0 },
{ 0, 0, 0, 0 }
};
{ "bpc", 6, {0, {0}}, 0, 0 },
{ "bbpsw", 8, {0, {0}}, 0, 0 },
{ "bbpc", 14, {0, {0}}, 0, 0 },
+ { "evb", 5, {0, {0}}, 0, 0 },
{ "cr0", 0, {0, {0}}, 0, 0 },
{ "cr1", 1, {0, {0}}, 0, 0 },
{ "cr2", 2, {0, {0}}, 0, 0 },
CGEN_KEYWORD m32r_cgen_opval_cr_names =
{
& m32r_cgen_opval_cr_names_entries[0],
- 23,
+ 24,
0, 0, 0, 0, ""
};
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
{ "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
+ { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
{ "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
{ M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+/* uimm3: 3 bit unsigned number */
+ { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
+ { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+/* uimm8: 8 bit unsigned immediate */
+ { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
+ { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
+ { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
- { 0, { (1<<MACH_M32RX) } } },
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
- { 0, { (1<<MACH_M32RX) } } },
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
- { 0, { (1<<MACH_M32RX) } } },
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
/* bcl.s $disp8 */
{
M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
- { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bcl.l $disp24 */
{
M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* bnc.s $disp8 */
{
/* bncl.s $disp8 */
{
M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
- { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bncl.l $disp24 */
{
M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* cmp $src1,$src2 */
{
/* cmpeq $src1,$src2 */
{
M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
- { 0, { (1<<MACH_M32RX), PIPE_OS } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
},
/* cmpz $src2 */
{
M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
- { 0, { (1<<MACH_M32RX), PIPE_OS } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
},
/* div $dr,$sr */
{
M32R_INSN_REMU, "remu", "remu", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
+/* remh $dr,$sr */
+ {
+ M32R_INSN_REMH, "remh", "remh", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* remuh $dr,$sr */
+ {
+ M32R_INSN_REMUH, "remuh", "remuh", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* remb $dr,$sr */
+ {
+ M32R_INSN_REMB, "remb", "remb", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* remub $dr,$sr */
+ {
+ M32R_INSN_REMUB, "remub", "remub", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* divuh $dr,$sr */
+ {
+ M32R_INSN_DIVUH, "divuh", "divuh", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* divb $dr,$sr */
+ {
+ M32R_INSN_DIVB, "divb", "divb", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* divub $dr,$sr */
+ {
+ M32R_INSN_DIVUB, "divub", "divub", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
/* divh $dr,$sr */
{
M32R_INSN_DIVH, "divh", "divh", 32,
- { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* jc $sr */
{
M32R_INSN_JC, "jc", "jc", 16,
- { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* jnc $sr */
{
M32R_INSN_JNC, "jnc", "jnc", 16,
- { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* jl $sr */
{
/* machi $src1,$src2,$acc */
{
M32R_INSN_MACHI_A, "machi-a", "machi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* maclo $src1,$src2 */
{
/* maclo $src1,$src2,$acc */
{
M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* macwhi $src1,$src2 */
{
/* macwhi $src1,$src2,$acc */
{
M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* macwlo $src1,$src2 */
{
/* macwlo $src1,$src2,$acc */
{
M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mul $dr,$sr */
{
/* mulhi $src1,$src2,$acc */
{
M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mullo $src1,$src2 */
{
/* mullo $src1,$src2,$acc */
{
M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mulwhi $src1,$src2 */
{
/* mulwhi $src1,$src2,$acc */
{
M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mulwlo $src1,$src2 */
{
/* mulwlo $src1,$src2,$acc */
{
M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mv $dr,$sr */
{
/* mvfachi $dr,$accs */
{
M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvfaclo $dr */
{
/* mvfaclo $dr,$accs */
{
M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvfacmi $dr */
{
/* mvfacmi $dr,$accs */
{
M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvfc $dr,$scr */
{
/* mvtachi $src1,$accs */
{
M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvtaclo $src1 */
{
/* mvtaclo $src1,$accs */
{
M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvtc $sr,$dcr */
{
/* rac $accd,$accs,$imm1 */
{
M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rach */
{
/* rach $accd,$accs,$imm1 */
{
M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rte */
{
/* sll $dr,$sr */
{
M32R_INSN_SLL, "sll", "sll", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* sll3 $dr,$sr,$simm16 */
{
/* slli $dr,$uimm5 */
{
M32R_INSN_SLLI, "slli", "slli", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* sra $dr,$sr */
{
M32R_INSN_SRA, "sra", "sra", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* sra3 $dr,$sr,$simm16 */
{
/* srai $dr,$uimm5 */
{
M32R_INSN_SRAI, "srai", "srai", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* srl $dr,$sr */
{
M32R_INSN_SRL, "srl", "srl", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* srl3 $dr,$sr,$simm16 */
{
/* srli $dr,$uimm5 */
{
M32R_INSN_SRLI, "srli", "srli", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* st $src1,@$src2 */
{
M32R_INSN_ST_PLUS, "st-plus", "st", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
+/* sth $src1,@$src2+ */
+ {
+ M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ },
+/* stb $src1,@$src2+ */
+ {
+ M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ },
/* st $src1,@-$src2 */
{
M32R_INSN_ST_MINUS, "st-minus", "st", 16,
/* satb $dr,$sr */
{
M32R_INSN_SATB, "satb", "satb", 32,
- { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* sath $dr,$sr */
{
M32R_INSN_SATH, "sath", "sath", 32,
- { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* sat $dr,$sr */
{
M32R_INSN_SAT, "sat", "sat", 32,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* pcmpbz $src2 */
{
M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
},
/* sadd */
{
M32R_INSN_SADD, "sadd", "sadd", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* macwu1 $src1,$src2 */
{
M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* msblo $src1,$src2 */
{
M32R_INSN_MSBLO, "msblo", "msblo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mulwu1 $src1,$src2 */
{
M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* maclh1 $src1,$src2 */
{
M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* sc */
{
M32R_INSN_SC, "sc", "sc", 16,
- { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* snc */
{
M32R_INSN_SNC, "snc", "snc", 16,
- { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ },
+/* clrpsw $uimm8 */
+ {
+ M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ },
+/* setpsw $uimm8 */
+ {
+ M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ },
+/* bset $uimm3,@($slo16,$sr) */
+ {
+ M32R_INSN_BSET, "bset", "bset", 32,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* bclr $uimm3,@($slo16,$sr) */
+ {
+ M32R_INSN_BCLR, "bclr", "bclr", 32,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* btst $uimm3,$sr */
+ {
+ M32R_INSN_BTST, "btst", "btst", 16,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
},
};
/* Selected cpu families. */
#define HAVE_CPU_M32RBF
#define HAVE_CPU_M32RXF
+#define HAVE_CPU_M32R2F
#define CGEN_INSN_LSB0_P 0
/* Enum declaration for . */
typedef enum cr_names {
H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
- , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
- , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
- , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
- , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
- , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
+ , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
+ , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
+ , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
+ , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
+ , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
} CR_NAMES;
/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
- MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
+ MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2
+ , MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
/* Enum declaration for parallel execution pipeline selection. */
typedef enum pipe_attr {
PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
+ , PIPE_O_OS
} PIPE_ATTR;
/* Number of architecture variants. */
typedef enum ifield_type {
M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
, M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
- , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5
- , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8
- , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3
- , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67
- , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX
+ , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4
+ , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24
+ , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24
+ , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS
+ , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14
+ , M32R_F_IMM1, M32R_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) M32R_F_MAX)
typedef enum cgen_operand_type {
M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
- , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
- , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC
- , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
- , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
- , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
+ , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5
+ , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD
+ , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16
+ , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8
+ , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM
+ , M32R_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 26
+#define MAX_OPERANDS 28
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 11
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
- , CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
+extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];
char *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+ char *x;
/* Read the base part of the insn. */
}
/* 32 bit insn? */
- if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+ x = (big_p ? &buf[0] : &buf[3]);
+ if ((pc & 3) == 0 && (*x & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
+ buf += (big_p ? 0 : 2);
if ((pc & 3) == 0)
{
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- buf += 2;
}
+ buf += (big_p ? 2 : -2);
- if (buf[0] & 0x80)
+ x = (big_p ? &buf[0] : &buf[1]);
+ if (*x & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
- buf[0] &= 0x7f;
+ *x &= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
case M32R_OPERAND_UIMM24 :
print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
break;
+ case M32R_OPERAND_UIMM3 :
+ print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+ break;
case M32R_OPERAND_UIMM4 :
print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case M32R_OPERAND_UIMM5 :
print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
+ case M32R_OPERAND_UIMM8 :
+ print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+ break;
case M32R_OPERAND_ULO16 :
print_normal (cd, info, fields->f_uimm16, 0, pc, length);
break;
case M32R_OPERAND_UIMM24 :
errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
break;
+ case M32R_OPERAND_UIMM3 :
+ errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
+ break;
case M32R_OPERAND_UIMM4 :
errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM5 :
errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
break;
+ case M32R_OPERAND_UIMM8 :
+ errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
+ break;
case M32R_OPERAND_ULO16 :
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM24 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
break;
+ case M32R_OPERAND_UIMM3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
+ break;
case M32R_OPERAND_UIMM4 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
break;
case M32R_OPERAND_UIMM5 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
break;
+ case M32R_OPERAND_UIMM8 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
+ break;
case M32R_OPERAND_ULO16 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
break;
case M32R_OPERAND_UIMM24 :
value = fields->f_uimm24;
break;
+ case M32R_OPERAND_UIMM3 :
+ value = fields->f_uimm3;
+ break;
case M32R_OPERAND_UIMM4 :
value = fields->f_uimm4;
break;
case M32R_OPERAND_UIMM5 :
value = fields->f_uimm5;
break;
+ case M32R_OPERAND_UIMM8 :
+ value = fields->f_uimm8;
+ break;
case M32R_OPERAND_ULO16 :
value = fields->f_uimm16;
break;
case M32R_OPERAND_UIMM24 :
value = fields->f_uimm24;
break;
+ case M32R_OPERAND_UIMM3 :
+ value = fields->f_uimm3;
+ break;
case M32R_OPERAND_UIMM4 :
value = fields->f_uimm4;
break;
case M32R_OPERAND_UIMM5 :
value = fields->f_uimm5;
break;
+ case M32R_OPERAND_UIMM8 :
+ value = fields->f_uimm8;
+ break;
case M32R_OPERAND_ULO16 :
value = fields->f_uimm16;
break;
case M32R_OPERAND_UIMM24 :
fields->f_uimm24 = value;
break;
+ case M32R_OPERAND_UIMM3 :
+ fields->f_uimm3 = value;
+ break;
case M32R_OPERAND_UIMM4 :
fields->f_uimm4 = value;
break;
case M32R_OPERAND_UIMM5 :
fields->f_uimm5 = value;
break;
+ case M32R_OPERAND_UIMM8 :
+ fields->f_uimm8 = value;
+ break;
case M32R_OPERAND_ULO16 :
fields->f_uimm16 = value;
break;
case M32R_OPERAND_UIMM24 :
fields->f_uimm24 = value;
break;
+ case M32R_OPERAND_UIMM3 :
+ fields->f_uimm3 = value;
+ break;
case M32R_OPERAND_UIMM4 :
fields->f_uimm4 = value;
break;
case M32R_OPERAND_UIMM5 :
fields->f_uimm5 = value;
break;
+ case M32R_OPERAND_UIMM8 :
+ fields->f_uimm8 = value;
+ break;
case M32R_OPERAND_ULO16 :
fields->f_uimm16 = value;
break;
#include "m32r-opc.h"
#include "libiberty.h"
+/* -- opc.c */
+unsigned int
+m32r_cgen_dis_hash (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value;
+{
+ unsigned int x;
+
+ if (value & 0xffff0000) /* 32bit instructions */
+ value = (value >> 16) & 0xffff;
+
+ x = (value>>8) & 0xf0;
+ if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+ return x;
+
+ if (x == 0x70 || x == 0xf0)
+ return x | ((value>>8) & 0x0f);
+
+ if (x == 0x30)
+ return x | ((value & 0x70) >> 4);
+ else
+ return x | ((value & 0xf0) >> 4);
+}
+
+/* -- */
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
};
+static const CGEN_IFMT ifmt_clrpsw = {
+ 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bset = {
+ 32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_btst = {
+ 16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
+};
+
#undef F
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
& ifmt_div, { 0x90300000 }
},
+/* remh $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90200010 }
+ },
+/* remuh $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90300010 }
+ },
+/* remb $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90200018 }
+ },
+/* remub $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90300018 }
+ },
+/* divuh $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90100010 }
+ },
+/* divb $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90000018 }
+ },
+/* divub $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90100018 }
+ },
/* divh $dr,$sr */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
& ifmt_cmp, { 0x2060 }
},
+/* sth $src1,@$src2+ */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+ & ifmt_cmp, { 0x2030 }
+ },
+/* stb $src1,@$src2+ */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+ & ifmt_cmp, { 0x2010 }
+ },
/* st $src1,@-$src2 */
{
{ 0, 0, 0, 0 },
{ { MNEM, 0 } },
& ifmt_nop, { 0x7501 }
},
+/* clrpsw $uimm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM8), 0 } },
+ & ifmt_clrpsw, { 0x7200 }
+ },
+/* setpsw $uimm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM8), 0 } },
+ & ifmt_clrpsw, { 0x7100 }
+ },
+/* bset $uimm3,@($slo16,$sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ & ifmt_bset, { 0xa0600000 }
+ },
+/* bclr $uimm3,@($slo16,$sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ & ifmt_bset, { 0xa0700000 }
+ },
+/* btst $uimm3,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
+ & ifmt_btst, { 0xf0 }
+ },
};
#undef A
/* bcl $disp8 */
{
-1, "bcl8r", "bcl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bcl $disp24 */
{
-1, "bcl24r", "bcl", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* bnc $disp8 */
{
/* bncl $disp8 */
{
-1, "bncl8r", "bncl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bncl $disp24 */
{
-1, "bncl24r", "bncl", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* ld $dr,@($sr) */
{
/* rac $accd */
{
-1, "rac-d", "rac", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rac $accd,$accs */
{
-1, "rac-ds", "rac", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rach $accd */
{
-1, "rach-d", "rach", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rach $accd,$accs */
{
-1, "rach-ds", "rach", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* st $src1,@($src2) */
{
/* push $src1 */
{
-1, "push", "push", 16,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
};
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
+#if 0
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+#else
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
+extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+#endif
/* -- */
/* Enum declaration for m32r instruction types. */
, M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
, M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
, M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
- , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH
- , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP
- , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D
- , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D
- , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24
- , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI
- , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI
- , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL
- , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A
- , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A
- , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO
- , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC
- , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A
- , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
- , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI
- , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
- , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
- , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
- , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
- , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
- , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
- , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ
- , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1
- , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH
+ , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH
+ , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC
+ , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD
+ , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH
+ , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH
+ , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8
+ , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A
+ , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A
+ , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI
+ , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI
+ , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV
+ , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A
+ , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI
+ , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC
+ , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC
+ , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE
+ , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI
+ , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL
+ , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D
+ , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D
+ , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS
+ , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
+ , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT
+ , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO
+ , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR
+ , M32R_INSN_BTST
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID M32R_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) M32R_INSN_SNC + 1)
+#define MAX_INSNS ((int) M32R_INSN_BTST + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
long f_simm8;
long f_simm16;
long f_shift_op2;
+ long f_uimm3;
long f_uimm4;
long f_uimm5;
+ long f_uimm8;
long f_uimm16;
long f_uimm24;
long f_hi16;
long f_accs;
long f_accd;
long f_bits67;
+ long f_bit4;
long f_bit14;
long f_imm1;
};
#define COND_REF CGEN_OPINST_COND_REF
static const CGEN_OPINST sfmt_empty_ops[] = {
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_add_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_add3_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_and3_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_or3_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addi_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addv_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addv3_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addx_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bc8_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bc24_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_beq_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_beqz_ops[] = {
{ INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bl8_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bl24_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bcl8_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bcl24_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bra8_ops[] = {
{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bra24_ops[] = {
{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_cmp_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_cmpi_ops[] = {
{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_cmpz_ops[] = {
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_div_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_jc_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_jl_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_jmp_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld_ops[] = {
{ INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld_d_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldb_ops[] = {
{ INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldb_d_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldh_ops[] = {
{ INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldh_d_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld_plus_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld24_ops[] = {
{ INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldi8_ops[] = {
{ INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldi16_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_lock_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_machi_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_machi_a_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mulhi_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mv_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvfachi_ops[] = {
{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
{ INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvfc_ops[] = {
{ INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvtachi_ops[] = {
{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
{ INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvtc_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_nop_ops[] = {
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_rac_ops[] = {
{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
{ INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
{ INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
{ OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_rte_ops[] = {
{ OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
{ OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_seth_ops[] = {
{ INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sll3_ops[] = {
{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_slli_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_st_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_st_d_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_stb_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_stb_d_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sth_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sth_d_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_st_plus_ops[] = {
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
{ OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sth_plus_ops[] = {
+ { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "h_memory_HI_new_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+ { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_plus_ops[] = {
+ { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "h_memory_QI_new_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+ { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_trap_ops[] = {
{ OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
{ OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_unlock_ops[] = {
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
{ OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_satb_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sat_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sadd_ops[] = {
{ INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
{ INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
{ OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_macwu1_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mulwu1_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sc_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_clrpsw_ops[] = {
+ { INPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
+ { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_setpsw_ops[] = {
+ { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
+ { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bset_ops[] = {
+ { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+ { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
+ { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
+ { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+ { OUTPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_btst_ops[] = {
+ { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
+ { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+ { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
#undef OP_ENT
& sfmt_div_ops[0],
& sfmt_div_ops[0],
& sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
& sfmt_jc_ops[0],
& sfmt_jc_ops[0],
& sfmt_jl_ops[0],
& sfmt_sth_ops[0],
& sfmt_sth_d_ops[0],
& sfmt_st_plus_ops[0],
+ & sfmt_sth_plus_ops[0],
+ & sfmt_stb_plus_ops[0],
& sfmt_st_plus_ops[0],
& sfmt_add_ops[0],
& sfmt_addv_ops[0],
& sfmt_macwu1_ops[0],
& sfmt_sc_ops[0],
& sfmt_sc_ops[0],
+ & sfmt_clrpsw_ops[0],
+ & sfmt_setpsw_ops[0],
+ & sfmt_bset_ops[0],
+ & sfmt_bset_ops[0],
+ & sfmt_btst_ops[0],
};
/* Function to call before using the operand instance table. */
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