Similarly "Opcode" not "OpCode".
This appears to be the general worldwide consensus on the matter. Other
residents of my office didn't seem to mind one way or the other how it's
spelled in our code, but for whatever reason, it really bugged me.
Change-Id: Ia0b73d19c54aefc0f543a9c9451dda22ee876a59
u4 width;
/* TODO: Make the index *always* be in field B, to simplify this code. */
- switch (dexGetInstrFormat(pDecInsn->opCode)) {
+ switch (dexGetInstrFormat(pDecInsn->opcode)) {
case kFmt20bc:
case kFmt21c:
case kFmt35c:
}
}
- if (pDecInsn->opCode == OP_NOP) {
+ if (pDecInsn->opcode == OP_NOP) {
u2 instr = get2LE((const u1*) &insns[insnIdx]);
if (instr == kPackedSwitchSignature) {
printf("|%04x: packed-switch-data (%d units)",
printf("|%04x: nop // spacer", insnIdx);
}
} else {
- printf("|%04x: %s", insnIdx, dexGetOpcodeName(pDecInsn->opCode));
+ printf("|%04x: %s", insnIdx, dexGetOpcodeName(pDecInsn->opcode));
}
if (pDecInsn->indexType != kIndexNone) {
indexBufChars, sizeof(indexBufChars));
}
- switch (dexGetInstrFormat(pDecInsn->opCode)) {
+ switch (dexGetInstrFormat(pDecInsn->opcode)) {
case kFmt10x: // op
break;
case kFmt12x: // op vA, vB
break;
case kFmt21h: // op vAA, #+BBBB0000[00000000]
// The printed format varies a bit based on the actual opcode.
- if (pDecInsn->opCode == OP_CONST_HIGH16) {
+ if (pDecInsn->opcode == OP_CONST_HIGH16) {
s4 value = pDecInsn->vB << 16;
printf(" v%d, #int %d // #%x",
pDecInsn->vA, value, (u2)pDecInsn->vB);
// The plus 1 is to round up for odd size and width.
insnWidth = 4 + ((size * width) + 1) / 2;
} else {
- OpCode opCode = dexOpCodeFromCodeUnit(instr);
- insnWidth = dexGetInstrWidth(opCode);
+ Opcode opcode = dexOpcodeFromCodeUnit(instr);
+ insnWidth = dexGetInstrWidth(opcode);
if (insnWidth == 0) {
fprintf(stderr,
"GLITCH: zero-width instruction at idx=0x%04x\n", insnIdx);
/*
* Return the name of an opcode.
*/
-const char* dexGetOpcodeName(OpCode op)
+const char* dexGetOpcodeName(Opcode op)
{
assert(op >= 0 && op < kNumDalvikInstructions);
return gOpNames[op];
* Enumeration of all Dalvik opcodes, where the enumeration value
* associated with each is the corresponding packed opcode number.
* This is different than the opcode value from the Dalvik bytecode
- * spec for opcode values >= 0xff; see dexOpCodeFromCodeUnit() below.
+ * spec for opcode values >= 0xff; see dexOpcodeFromCodeUnit() below.
*
* A note about the "breakpoint" opcode. This instruction is special,
* in that it should never be seen by anything but the debug
* can find the next instruction" aren't possible. (This is
* correctable, but probably not useful.)
*/
-typedef enum OpCode {
+typedef enum Opcode {
// BEGIN(libdex-opcode-enum); GENERATED AUTOMATICALLY BY opcode-gen
OP_NOP = 0x00,
OP_MOVE = 0x01,
OP_SPUT_OBJECT_VOLATILE = 0xfe,
OP_UNUSED_FF = 0xff,
// END(libdex-opcode-enum)
-} OpCode;
+} Opcode;
/*
* Macro used to generate a computed goto table for use in implementing
};
/*
- * Return the OpCode for a given raw opcode code unit (which may
+ * Return the Opcode for a given raw opcode code unit (which may
* include data payload). The packed index is a zero-based index which
* can be used to point into various opcode-related tables. The Dalvik
* opcode space is inherently sparse, in that the opcode unit is 16
* bits wide, but for most opcodes, eight of those bits are for data.
*/
-DEX_INLINE OpCode dexOpCodeFromCodeUnit(u2 codeUnit) {
+DEX_INLINE Opcode dexOpcodeFromCodeUnit(u2 codeUnit) {
/*
* This will want to become table-driven should the opcode layout
* get more complicated.
*/
int lowByte = codeUnit & 0xff;
if (lowByte != 0xff) {
- return (OpCode) lowByte;
+ return (Opcode) lowByte;
} else {
- return (OpCode) ((codeUnit >> 8) | 0x100);
+ return (Opcode) ((codeUnit >> 8) | 0x100);
}
}
/*
* Return the name of an opcode.
*/
-const char* dexGetOpcodeName(OpCode op);
+const char* dexGetOpcodeName(Opcode op);
#endif /*_LIBDEX_DEXOPCODES*/
void dexDecodeInstruction(const u2* insns, DecodedInstruction* pDec)
{
u2 inst = *insns;
- OpCode opCode = dexOpCodeFromCodeUnit(inst);
- InstructionFormat format = dexGetInstrFormat(opCode);
+ Opcode opcode = dexOpcodeFromCodeUnit(inst);
+ InstructionFormat format = dexGetInstrFormat(opcode);
- pDec->opCode = opCode;
- pDec->indexType = dexGetInstrIndexType(opCode);
+ pDec->opcode = opcode;
+ pDec->indexType = dexGetInstrIndexType(opcode);
switch (format) {
case kFmt10x: // op
pDec->vC = FETCH(4);
break;
default:
- LOGW("Can't decode unexpected format %d (op=%d)\n", format, opCode);
+ LOGW("Can't decode unexpected format %d (op=%d)\n", format, opcode);
assert(false);
break;
}
// The plus 1 is to round up for odd size and width.
width = 4 + (elemWidth * len + 1) / 2;
} else {
- width = dexGetInstrWidth(dexOpCodeFromCodeUnit(insns[0]));
+ width = dexGetInstrWidth(dexOpcodeFromCodeUnit(insns[0]));
}
return width;
}
u8 vB_wide; /* for kFmt51l */
u4 vC;
u4 arg[5]; /* vC/D/E/F/G in invoke or filled-new-array */
- OpCode opCode;
+ Opcode opcode;
InstructionIndexType indexType;
} DecodedInstruction;
/*
* Return the width of the specified instruction, or 0 if not defined.
*/
-DEX_INLINE size_t dexGetInstrWidth(OpCode opCode)
+DEX_INLINE size_t dexGetInstrWidth(Opcode opcode)
{
- //assert(/*opCode >= 0 &&*/ opCode < kNumDalvikInstructions);
- return gDexOpcodeInfo.widths[opCode];
+ //assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
+ return gDexOpcodeInfo.widths[opcode];
}
/*
/*
* Returns the flags for the specified opcode.
*/
-DEX_INLINE int dexGetInstrFlags(OpCode opCode)
+DEX_INLINE int dexGetInstrFlags(Opcode opcode)
{
- //assert(/*opCode >= 0 &&*/ opCode < kNumDalvikInstructions);
- return gDexOpcodeInfo.flags[opCode];
+ //assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
+ return gDexOpcodeInfo.flags[opcode];
}
/*
/*
* Return the instruction format for the specified opcode.
*/
-DEX_INLINE InstructionFormat dexGetInstrFormat(OpCode opCode)
+DEX_INLINE InstructionFormat dexGetInstrFormat(Opcode opcode)
{
- //assert(/*opCode >= 0 &&*/ opCode < kNumDalvikInstructions);
- return gDexOpcodeInfo.formats[opCode];
+ //assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
+ return gDexOpcodeInfo.formats[opcode];
}
/*
* Return the instruction index type for the specified opcode.
*/
-DEX_INLINE InstructionIndexType dexGetInstrIndexType(OpCode opCode)
+DEX_INLINE InstructionIndexType dexGetInstrIndexType(Opcode opcode)
{
- //assert(/*opCode >= 0 &&*/ opCode < kNumDalvikInstructions);
- return gDexOpcodeInfo.indexTypes[opCode];
+ //assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
+ return gDexOpcodeInfo.indexTypes[opcode];
}
/*
#endif
dexDecodeInstruction(insns, &decInsn);
- int nextFlags = dexGetInstrFlags(decInsn.opCode);
+ int nextFlags = dexGetInstrFlags(decInsn.opcode);
/*
* Make a copy of the previous register state. If the instruction
#endif
}
- switch (decInsn.opCode) {
+ switch (decInsn.opcode) {
case OP_NOP:
/*
* A "pure" NOP has no effect on anything. Data tables start with
LOG_VFY("VFY: filled-new-array on non-array class\n");
failure = VERIFY_ERROR_GENERIC;
} else {
- bool isRange = (decInsn.opCode == OP_FILLED_NEW_ARRAY_RANGE);
+ bool isRange = (decInsn.opcode == OP_FILLED_NEW_ARRAY_RANGE);
/* check the arguments to the instruction */
verifyFilledNewArrayRegs(meth, workLine, &decInsn,
bool isRange;
bool isSuper;
- isRange = (decInsn.opCode == OP_INVOKE_VIRTUAL_RANGE ||
- decInsn.opCode == OP_INVOKE_SUPER_RANGE);
- isSuper = (decInsn.opCode == OP_INVOKE_SUPER ||
- decInsn.opCode == OP_INVOKE_SUPER_RANGE);
+ isRange = (decInsn.opcode == OP_INVOKE_VIRTUAL_RANGE ||
+ decInsn.opcode == OP_INVOKE_SUPER_RANGE);
+ isSuper = (decInsn.opcode == OP_INVOKE_SUPER ||
+ decInsn.opcode == OP_INVOKE_SUPER_RANGE);
calledMethod = verifyInvocationArgs(meth, workLine, insnRegCount,
&decInsn, uninitMap, METHOD_VIRTUAL, isRange,
Method* calledMethod;
bool isRange;
- isRange = (decInsn.opCode == OP_INVOKE_DIRECT_RANGE);
+ isRange = (decInsn.opcode == OP_INVOKE_DIRECT_RANGE);
calledMethod = verifyInvocationArgs(meth, workLine, insnRegCount,
&decInsn, uninitMap, METHOD_DIRECT, isRange,
false, &failure);
Method* calledMethod;
bool isRange;
- isRange = (decInsn.opCode == OP_INVOKE_STATIC_RANGE);
+ isRange = (decInsn.opcode == OP_INVOKE_STATIC_RANGE);
calledMethod = verifyInvocationArgs(meth, workLine, insnRegCount,
&decInsn, uninitMap, METHOD_STATIC, isRange,
false, &failure);
Method* absMethod;
bool isRange;
- isRange = (decInsn.opCode == OP_INVOKE_INTERFACE_RANGE);
+ isRange = (decInsn.opcode == OP_INVOKE_INTERFACE_RANGE);
absMethod = verifyInvocationArgs(meth, workLine, insnRegCount,
&decInsn, uninitMap, METHOD_INTERFACE, isRange,
false, &failure);
if (failure == VERIFY_ERROR_GENERIC || gDvm.optimizing) {
/* immediate failure, reject class */
LOG_VFY_METH(meth, "VFY: rejecting opcode 0x%02x at 0x%04x\n",
- decInsn.opCode, insnIdx);
+ decInsn.opcode, insnIdx);
goto bail;
} else {
/* replace opcode and continue on */
LOGD("VFY: replacing opcode 0x%02x at 0x%04x\n",
- decInsn.opCode, insnIdx);
+ decInsn.opcode, insnIdx);
if (!replaceFailingInstruction(meth, insnFlags, insnIdx, failure)) {
LOG_VFY_METH(meth, "VFY: rejecting opcode 0x%02x at 0x%04x\n",
- decInsn.opCode, insnIdx);
+ decInsn.opcode, insnIdx);
goto bail;
}
/* IMPORTANT: meth->insns may have been changed */
* stack was empty, we don't need a catch-all (if it throws,
* it will do so before grabbing the lock).
*/
- if (!(decInsn.opCode == OP_MONITOR_ENTER &&
+ if (!(decInsn.opcode == OP_MONITOR_ENTER &&
workLine->monitorStackTop == 1))
{
LOG_VFY_METH(meth,
"VFY: warning: unusually large instr width (%d)\n", width);
}
- OpCode opcode = dexOpCodeFromCodeUnit(*insns);
+ Opcode opcode = dexOpcodeFromCodeUnit(*insns);
if (opcode == OP_NEW_INSTANCE)
newInstanceCount++;
if (opcode == OP_MONITOR_ENTER)
* for out-of-range values. Do additional checks on branch targets
* and some special cases like new-instance and new-array.
*/
- switch (decInsn.opCode) {
+ switch (decInsn.opcode) {
case OP_NOP:
case OP_RETURN_VOID:
/* nothing to check */
case OP_UNUSED_79:
case OP_UNUSED_7A:
case OP_UNUSED_FF:
- LOGE("VFY: unexpected opcode %02x\n", decInsn.opCode);
+ LOGE("VFY: unexpected opcode %02x\n", decInsn.opcode);
okay = false;
break;
if (!okay) {
LOG_VFY_METH(meth, "VFY: rejecting opcode 0x%02x at 0x%04x\n",
- decInsn.opCode, codeOffset);
+ decInsn.opcode, codeOffset);
return false;
}
const int kGcMask = kInstrCanBranch | kInstrCanSwitch |
kInstrCanThrow | kInstrCanReturn;
- InstructionFlags opFlags = dexGetInstrFlags(decInsn.opCode);
+ InstructionFlags opFlags = dexGetInstrFlags(decInsn.opcode);
if ((opFlags & kGcMask) != 0) {
/*
* This instruction is probably a GC point. Branch instructions
{
/* should never happen */
LOGE("VFY: opcode %02x flagged as can branch, no target\n",
- decInsn.opCode);
+ decInsn.opcode);
dvmAbort();
}
if (offset <= 0) {
/* fwd */
static void optimizeMethod(Method* method, bool essentialOnly);
-static bool rewriteInstField(Method* method, u2* insns, OpCode quickOpc,
- OpCode volatileOpc);
-static bool rewriteStaticField(Method* method, u2* insns, OpCode volatileOpc);
-static bool rewriteVirtualInvoke(Method* method, u2* insns, OpCode newOpc);
+static bool rewriteInstField(Method* method, u2* insns, Opcode quickOpc,
+ Opcode volatileOpc);
+static bool rewriteStaticField(Method* method, u2* insns, Opcode volatileOpc);
+static bool rewriteVirtualInvoke(Method* method, u2* insns, Opcode newOpc);
static bool rewriteEmptyDirectInvoke(Method* method, u2* insns);
static bool rewriteExecuteInline(Method* method, u2* insns,
MethodType methodType);
insnsSize = dvmGetMethodInsnsSize(method);
while (insnsSize > 0) {
- OpCode quickOpc, volatileOpc = OP_NOP;
+ Opcode quickOpc, volatileOpc = OP_NOP;
int width;
bool notMatched = false;
/*
* Update the 8-bit opcode portion of a 16-bit code unit in "meth".
*/
-static inline void updateOpCode(const Method* meth, u2* ptr, OpCode opCode)
+static inline void updateOpcode(const Method* meth, u2* ptr, Opcode opcode)
{
- updateCodeUnit(meth, ptr, (ptr[0] & 0xff00) | (u2) opCode);
+ updateCodeUnit(meth, ptr, (ptr[0] & 0xff00) | (u2) opcode);
}
/*
*
* "method" is the referring method.
*/
-static bool rewriteInstField(Method* method, u2* insns, OpCode quickOpc,
- OpCode volatileOpc)
+static bool rewriteInstField(Method* method, u2* insns, Opcode quickOpc,
+ Opcode volatileOpc)
{
ClassObject* clazz = method->clazz;
u2 fieldIdx = insns[1];
}
if (volatileOpc != OP_NOP && dvmIsVolatileField(&instField->field)) {
- updateOpCode(method, insns, volatileOpc);
+ updateOpcode(method, insns, volatileOpc);
LOGV("DexOpt: rewrote ifield access %s.%s --> volatile\n",
instField->field.clazz->descriptor, instField->field.name);
} else if (quickOpc != OP_NOP) {
- updateOpCode(method, insns, quickOpc);
+ updateOpcode(method, insns, quickOpc);
updateCodeUnit(method, insns+1, (u2) instField->byteOffset);
LOGV("DexOpt: rewrote ifield access %s.%s --> %d\n",
instField->field.clazz->descriptor, instField->field.name,
*
* "method" is the referring method.
*/
-static bool rewriteStaticField(Method* method, u2* insns, OpCode volatileOpc)
+static bool rewriteStaticField(Method* method, u2* insns, Opcode volatileOpc)
{
ClassObject* clazz = method->clazz;
u2 fieldIdx = insns[1];
}
if (dvmIsVolatileField(&staticField->field)) {
- updateOpCode(method, insns, volatileOpc);
+ updateOpcode(method, insns, volatileOpc);
LOGV("DexOpt: rewrote sfield access %s.%s --> volatile\n",
staticField->field.clazz->descriptor, staticField->field.name);
}
* We want to replace the method constant pool index BBBB with the
* vtable index.
*/
-static bool rewriteVirtualInvoke(Method* method, u2* insns, OpCode newOpc)
+static bool rewriteVirtualInvoke(Method* method, u2* insns, Opcode newOpc)
{
ClassObject* clazz = method->clazz;
Method* baseMethod;
* Note: Method->methodIndex is a u2 and is range checked during the
* initial load.
*/
- updateOpCode(method, insns, newOpc);
+ updateOpcode(method, insns, newOpc);
updateCodeUnit(method, insns+1, baseMethod->methodIndex);
//LOGI("DexOpt: rewrote call to %s.%s --> %s.%s\n",
* OP_INVOKE_DIRECT when debugging is enabled.
*/
assert((insns[0] & 0xff) == OP_INVOKE_DIRECT);
- updateOpCode(method, insns, OP_INVOKE_DIRECT_EMPTY);
+ updateOpcode(method, insns, OP_INVOKE_DIRECT_EMPTY);
//LOGI("DexOpt: marked-empty call to %s.%s --> %s.%s\n",
// method->clazz->descriptor, method->name,
assert((insns[0] & 0xff) == OP_INVOKE_DIRECT ||
(insns[0] & 0xff) == OP_INVOKE_STATIC ||
(insns[0] & 0xff) == OP_INVOKE_VIRTUAL);
- updateOpCode(method, insns, OP_EXECUTE_INLINE);
+ updateOpcode(method, insns, OP_EXECUTE_INLINE);
updateCodeUnit(method, insns+1, (u2) inlineSubs->inlineIdx);
//LOGI("DexOpt: execute-inline %s.%s --> %s.%s\n",
assert((insns[0] & 0xff) == OP_INVOKE_DIRECT_RANGE ||
(insns[0] & 0xff) == OP_INVOKE_STATIC_RANGE ||
(insns[0] & 0xff) == OP_INVOKE_VIRTUAL_RANGE);
- updateOpCode(method, insns, OP_EXECUTE_INLINE_RANGE);
+ updateOpcode(method, insns, OP_EXECUTE_INLINE_RANGE);
updateCodeUnit(method, insns+1, (u2) inlineSubs->inlineIdx);
//LOGI("DexOpt: execute-inline/range %s.%s --> %s.%s\n",
static void rewriteReturnVoid(Method* method, u2* insns)
{
assert((insns[0] & 0xff) == OP_RETURN_VOID);
- updateOpCode(method, insns, OP_RETURN_VOID_BARRIER);
+ updateOpcode(method, insns, OP_RETURN_VOID_BARRIER);
}
char *note)
{
char buffer[256];
- int opcode = insn->opCode;
+ int opcode = insn->opcode;
int dfAttributes = dvmCompilerDataFlowAttributes[opcode];
char *ret;
for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
int dfAttributes =
- dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode];
+ dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
DecodedInstruction *dInsn = &mir->dalvikInsn;
if (dfAttributes & DF_HAS_USES) {
mir->ssaRep = dvmCompilerNew(sizeof(SSARepresentation), true);
int dfAttributes =
- dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode];
+ dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
int numUses = 0;
for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
int dfAttributes =
- dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode];
+ dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
DecodedInstruction *dInsn = &mir->dalvikInsn;
/* Handle instructions that set up constants directly */
if (dfAttributes & DF_SETS_CONST) {
if (dfAttributes & DF_DA) {
- switch (dInsn->opCode) {
+ switch (dInsn->opcode) {
case OP_CONST_4:
case OP_CONST_16:
case OP_CONST:
break;
}
} else if (dfAttributes & DF_DA_WIDE) {
- switch (dInsn->opCode) {
+ switch (dInsn->opcode) {
case OP_CONST_WIDE_16:
case OP_CONST_WIDE_32:
setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
/* If the bb doesn't have a phi it cannot contain an induction variable */
if (bb->firstMIRInsn == NULL ||
- bb->firstMIRInsn->dalvikInsn.opCode != kMirOpPhi) {
+ bb->firstMIRInsn->dalvikInsn.opcode != kMirOpPhi) {
return;
}
/* Find basic induction variable first */
for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
int dfAttributes =
- dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode];
+ dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
if (!(dfAttributes & DF_IS_LINEAR)) continue;
*/
MIR *phi;
for (phi = bb->firstMIRInsn; phi; phi = phi->next) {
- if (phi->dalvikInsn.opCode != kMirOpPhi) break;
+ if (phi->dalvikInsn.opcode != kMirOpPhi) break;
if (phi->ssaRep->defs[0] == mir->ssaRep->uses[0] &&
phi->ssaRep->uses[1] == mir->ssaRep->defs[0]) {
bool deltaIsConstant = false;
int deltaValue;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_INT:
if (dvmIsBitSet(isConstantV,
mir->ssaRep->uses[1])) {
/* Find dependent induction variable now */
for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
int dfAttributes =
- dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode];
+ dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
if (!(dfAttributes & DF_IS_LINEAR)) continue;
bool cIsConstant = false;
int c = 0;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_INT:
if (dvmIsBitSet(isConstantV,
mir->ssaRep->uses[1])) {
bool printMe)
{
u2 instr = *codePtr;
- OpCode opcode = dexOpCodeFromCodeUnit(instr);
+ Opcode opcode = dexOpcodeFromCodeUnit(instr);
int insnWidth;
// Don't parse instruction data
unsigned int *target, bool *isInvoke,
const Method **callee)
{
- switch (insn->dalvikInsn.opCode) {
+ switch (insn->dalvikInsn.opcode) {
/* Target is not compile-time constant */
case OP_RETURN_VOID:
case OP_RETURN:
static inline bool isGoto(MIR *insn)
{
- switch (insn->dalvikInsn.opCode) {
+ switch (insn->dalvikInsn.opcode) {
case OP_GOTO:
case OP_GOTO_16:
case OP_GOTO_32:
*/
static inline bool isUnconditionalBranch(MIR *insn)
{
- switch (insn->dalvikInsn.opCode) {
+ switch (insn->dalvikInsn.opcode) {
case OP_RETURN_VOID:
case OP_RETURN:
case OP_RETURN_WIDE:
static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes,
int offset)
{
- int flags = dexGetInstrFlags(dalvikInsn->opCode);
- int dalvikOpCode = dalvikInsn->opCode;
+ int flags = dexGetInstrFlags(dalvikInsn->opcode);
+ int dalvikOpcode = dalvikInsn->opcode;
if (flags & kInstrInvoke) {
attributes &= ~METHOD_IS_LEAF;
}
if (!(flags & kInstrCanReturn)) {
- if (!(dvmCompilerDataFlowAttributes[dalvikOpCode] &
+ if (!(dvmCompilerDataFlowAttributes[dalvikOpcode] &
DF_IS_GETTER)) {
attributes &= ~METHOD_IS_GETTER;
}
- if (!(dvmCompilerDataFlowAttributes[dalvikOpCode] &
+ if (!(dvmCompilerDataFlowAttributes[dalvikOpcode] &
DF_IS_SETTER)) {
attributes &= ~METHOD_IS_SETTER;
}
* otherwise.
*/
if (flags & kInstrCanReturn) {
- if (dalvikOpCode == OP_RETURN_VOID) {
+ if (dalvikOpcode == OP_RETURN_VOID) {
attributes &= ~METHOD_IS_GETTER;
}
else {
attributes &= ~METHOD_IS_THROW_FREE;
}
- if (offset == 0 && dalvikOpCode == OP_RETURN_VOID) {
+ if (offset == 0 && dalvikOpcode == OP_RETURN_VOID) {
attributes |= METHOD_IS_EMPTY;
}
* If so, don't inline the callee as there is no stack frame for the
* interpreter to single-step through the instruction.
*/
- if (SINGLE_STEP_OP(dalvikOpCode)) {
+ if (SINGLE_STEP_OP(dalvikOpcode)) {
attributes &= ~(METHOD_IS_GETTER | METHOD_IS_SETTER);
}
dvmCompilerAppendMIR(curBB, insn);
cUnit.numInsts++;
- int flags = dexGetInstrFlags(insn->dalvikInsn.opCode);
+ int flags = dexGetInstrFlags(insn->dalvikInsn.opcode);
if (flags & kInstrInvoke) {
assert(numInsts == 1);
/* Link the taken and fallthrough blocks */
BasicBlock *searchBB;
- int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opCode);
+ int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opcode);
if (flags & kInstrInvoke) {
cUnit.hasInvoke = true;
cUnit.hasLoop = true;
}
- if (lastInsn->dalvikInsn.opCode == OP_PACKED_SWITCH ||
- lastInsn->dalvikInsn.opCode == OP_SPARSE_SWITCH) {
+ if (lastInsn->dalvikInsn.opcode == OP_PACKED_SWITCH ||
+ lastInsn->dalvikInsn.opcode == OP_SPARSE_SWITCH) {
int i;
const u2 *switchData = desc->method->insns + lastInsn->offset +
lastInsn->dalvikInsn.vB;
}
s4 *targets = (s4 *) (switchData + 2 +
- (lastInsn->dalvikInsn.opCode == OP_PACKED_SWITCH ?
+ (lastInsn->dalvikInsn.opcode == OP_PACKED_SWITCH ?
2 : size * 2));
/* One chaining cell for the first MAX_CHAINED_SWITCH_CASES cases */
bool dvmCompilerCanIncludeThisInstruction(const Method *method,
const DecodedInstruction *insn)
{
- switch (insn->opCode) {
+ switch (insn->opcode) {
case OP_NEW_INSTANCE:
case OP_CHECK_CAST: {
ClassObject *classPtr = (void*)
* aligned to 4-byte boundary (alignment instruction to be
* inserted later.
*/
- if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opCode)
+ if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opcode)
& kInstrInvoke) {
newBB->isFallThroughFromInvoke = true;
}
* by a move result.
*/
if ((moveResultMIR == NULL) ||
- (moveResultMIR->dalvikInsn.opCode != OP_MOVE_RESULT &&
- moveResultMIR->dalvikInsn.opCode != OP_MOVE_RESULT_OBJECT &&
- moveResultMIR->dalvikInsn.opCode != OP_MOVE_RESULT_WIDE)) {
+ (moveResultMIR->dalvikInsn.opcode != OP_MOVE_RESULT &&
+ moveResultMIR->dalvikInsn.opcode != OP_MOVE_RESULT_OBJECT &&
+ moveResultMIR->dalvikInsn.opcode != OP_MOVE_RESULT_WIDE)) {
return;
}
- int dfFlags = dvmCompilerDataFlowAttributes[getterInsn.opCode];
+ int dfFlags = dvmCompilerDataFlowAttributes[getterInsn.opcode];
/* Expecting vA to be the destination register */
if (dfFlags & (DF_UA | DF_UA_WIDE)) {
- LOGE("opcode %d has DF_UA set (not expected)", getterInsn.opCode);
+ LOGE("opcode %d has DF_UA set (not expected)", getterInsn.opcode);
dvmAbort();
}
/* Now setup the Dalvik instruction with converted src/dst registers */
newGetterMIR->dalvikInsn = getterInsn;
- newGetterMIR->width = dexGetInstrWidth(getterInsn.opCode);
+ newGetterMIR->width = dexGetInstrWidth(getterInsn.opcode);
newGetterMIR->OptimizationFlags |= MIR_CALLEE;
if (isPredicted) {
MIR *invokeMIRSlow = dvmCompilerNew(sizeof(MIR), true);
*invokeMIRSlow = *invokeMIR;
- invokeMIR->dalvikInsn.opCode = kMirOpCheckInlinePrediction;
+ invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction;
/* Use vC to denote the first argument (ie this) */
if (!isRange) {
if (!dvmCompilerCanIncludeThisInstruction(calleeMethod, &setterInsn))
return;
- int dfFlags = dvmCompilerDataFlowAttributes[setterInsn.opCode];
+ int dfFlags = dvmCompilerDataFlowAttributes[setterInsn.opcode];
if (dfFlags & (DF_UA | DF_UA_WIDE)) {
setterInsn.vA = convertRegId(&invokeMIR->dalvikInsn, calleeMethod,
/* Now setup the Dalvik instruction with converted src/dst registers */
newSetterMIR->dalvikInsn = setterInsn;
- newSetterMIR->width = dexGetInstrWidth(setterInsn.opCode);
+ newSetterMIR->width = dexGetInstrWidth(setterInsn.opcode);
newSetterMIR->OptimizationFlags |= MIR_CALLEE;
if (isPredicted) {
MIR *invokeMIRSlow = dvmCompilerNew(sizeof(MIR), true);
*invokeMIRSlow = *invokeMIR;
- invokeMIR->dalvikInsn.opCode = kMirOpCheckInlinePrediction;
+ invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction;
/* Use vC to denote the first argument (ie this) */
if (!isRange) {
{
MIR *invokeMIRSlow = dvmCompilerNew(sizeof(MIR), true);
*invokeMIRSlow = *invokeMIR;
- invokeMIR->dalvikInsn.opCode = kMirOpCheckInlinePrediction;
+ invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction;
dvmCompilerInsertMIRAfter(invokeBB, invokeMIR, invokeMIRSlow);
invokeMIRSlow->OptimizationFlags |= MIR_INLINED_PRED;
if (bb->blockType != kDalvikByteCode)
continue;
MIR *lastMIRInsn = bb->lastMIRInsn;
- int opCode = lastMIRInsn->dalvikInsn.opCode;
- int flags = dexGetInstrFlags(opCode);
+ int opcode = lastMIRInsn->dalvikInsn.opcode;
+ int flags = dexGetInstrFlags(opcode);
/* No invoke - continue */
if ((flags & kInstrInvoke) == 0)
* If the invoke itself is selected for single stepping, don't bother
* to inline it.
*/
- if (SINGLE_STEP_OP(opCode))
+ if (SINGLE_STEP_OP(opcode))
continue;
const Method *calleeMethod;
- switch (opCode) {
+ switch (opcode) {
case OP_INVOKE_SUPER:
case OP_INVOKE_DIRECT:
case OP_INVOKE_STATIC:
return;
}
- switch (opCode) {
+ switch (opcode) {
case OP_INVOKE_VIRTUAL:
case OP_INVOKE_VIRTUAL_QUICK:
case OP_INVOKE_INTERFACE:
continue;
}
MIR *phi = dvmCompilerNew(sizeof(MIR), true);
- phi->dalvikInsn.opCode = kMirOpPhi;
+ phi->dalvikInsn.opcode = kMirOpPhi;
phi->dalvikInsn.vA = i;
dvmCompilerPrependMIR(loopBody, phi);
}
MIR *mir;
for (mir = loopBody->firstMIRInsn; mir; mir = mir->next) {
- if (mir->dalvikInsn.opCode != kMirOpPhi) break;
+ if (mir->dalvikInsn.opcode != kMirOpPhi) break;
int dalvikReg = mir->dalvikInsn.vA;
mir->ssaRep->numUses = 2;
}
MIR *branch = loopBranch->lastMIRInsn;
- OpCode opCode = branch->dalvikInsn.opCode;
+ Opcode opcode = branch->dalvikInsn.opcode;
/*
* If the instruction is not accessing the IV as the first operand, return
* If the condition op is not > or >=, this is not an optimization
* candidate.
*/
- if (opCode != OP_IF_GT && opCode != OP_IF_GE) {
+ if (opcode != OP_IF_GT && opcode != OP_IF_GE) {
return false;
}
/*
* If the condition op is not < or <=, this is not an optimization
* candidate.
*/
- if (opCode == OP_IF_LT || opCode == OP_IF_LE) {
+ if (opcode == OP_IF_LT || opcode == OP_IF_LE) {
/*
* If the comparison is not between the BIV and a loop invariant,
* return false.
return false;
}
loopAnalysis->endConditionReg = DECODE_REG(endReg);
- } else if (opCode != OP_IF_LTZ && opCode != OP_IF_LEZ) {
+ } else if (opcode != OP_IF_LTZ && opcode != OP_IF_LEZ) {
return false;
}
}
- loopAnalysis->loopBranchOpcode = opCode;
+ loopAnalysis->loopBranchOpcode = opcode;
return true;
}
for (mir = loopBody->firstMIRInsn; mir; mir = mir->next) {
DecodedInstruction *dInsn = &mir->dalvikInsn;
int dfAttributes =
- dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode];
+ dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
/* Skip extended MIR instructions */
- if (dInsn->opCode >= kNumDalvikInstructions) continue;
+ if (dInsn->opcode >= kNumDalvikInstructions) continue;
- int instrFlags = dexGetInstrFlags(dInsn->opCode);
+ int instrFlags = dexGetInstrFlags(dInsn->opcode);
/* Instruction is clean */
if ((instrFlags & kInstrCanThrow) == 0) continue;
dvmConvertSSARegToDalvik(cUnit, arrayAccessInfo->ivReg));
MIR *rangeCheckMIR = dvmCompilerNew(sizeof(MIR), true);
- rangeCheckMIR->dalvikInsn.opCode = (loopAnalysis->isCountUpLoop) ?
+ rangeCheckMIR->dalvikInsn.opcode = (loopAnalysis->isCountUpLoop) ?
kMirOpNullNRangeUpCheck : kMirOpNullNRangeDownCheck;
rangeCheckMIR->dalvikInsn.vA = arrayReg;
rangeCheckMIR->dalvikInsn.vB = idxReg;
if (loopAnalysis->arrayAccessInfo->numUsed != 0) {
if (loopAnalysis->isCountUpLoop) {
MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true);
- boundCheckMIR->dalvikInsn.opCode = kMirOpLowerBound;
+ boundCheckMIR->dalvikInsn.opcode = kMirOpLowerBound;
boundCheckMIR->dalvikInsn.vA = idxReg;
boundCheckMIR->dalvikInsn.vB = globalMinC;
dvmCompilerAppendMIR(entry, boundCheckMIR);
if (loopAnalysis->loopBranchOpcode == OP_IF_LT ||
loopAnalysis->loopBranchOpcode == OP_IF_LE) {
MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true);
- boundCheckMIR->dalvikInsn.opCode = kMirOpLowerBound;
+ boundCheckMIR->dalvikInsn.opcode = kMirOpLowerBound;
boundCheckMIR->dalvikInsn.vA = loopAnalysis->endConditionReg;
boundCheckMIR->dalvikInsn.vB = globalMinC;
/*
/* Array index will fall below 0 */
if (globalMinC < 0) {
MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true);
- boundCheckMIR->dalvikInsn.opCode = kMirOpPunt;
+ boundCheckMIR->dalvikInsn.opcode = kMirOpPunt;
dvmCompilerAppendMIR(entry, boundCheckMIR);
}
} else if (loopAnalysis->loopBranchOpcode == OP_IF_LEZ) {
/* Array index will fall below 0 */
if (globalMinC < -1) {
MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true);
- boundCheckMIR->dalvikInsn.opCode = kMirOpPunt;
+ boundCheckMIR->dalvikInsn.opcode = kMirOpPunt;
dvmCompilerAppendMIR(entry, boundCheckMIR);
}
} else {
int numBasicIV; // number of basic induction variables
int ssaBIV; // basic IV in SSA name
bool isCountUpLoop; // count up or down loop
- OpCode loopBranchOpcode; // OP_IF_XXX for the loop back branch
+ Opcode loopBranchOpcode; // OP_IF_XXX for the loop back branch
int endConditionReg; // vB in "vA op vB"
LIR *branchToBody; // branch over to the body from entry
LIR *branchToPCR; // branch over to the PCR cell
* Jump to the out-of-line handler in ARM mode to finish executing the
* remaining of more complex instructions.
*/
-static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
+static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpcode opcode)
{
/*
* NOTE - In practice BLX only needs one operand, but since the assembler
*/
dvmCompilerClobberHandlerRegs(cUnit);
newLIR2(cUnit, kThumbBlx1,
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
newLIR2(cUnit, kThumbBlx2,
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
}
const bool dumpNop = false;
/* Handle pseudo-ops individually, and all regular insns as a group */
- switch(lir->opCode) {
+ switch(lir->opcode) {
case kArmChainingCellBottom:
LOGD("-------- end of chaining cells (0x%04x)\n", offset);
break;
if (lir->isNop && !dumpNop) {
break;
}
- buildInsnString(EncodingMap[lir->opCode].name, lir, opName,
+ buildInsnString(EncodingMap[lir->opcode].name, lir, opName,
baseAddr, 256);
- buildInsnString(EncodingMap[lir->opCode].fmt, lir, buf, baseAddr,
+ buildInsnString(EncodingMap[lir->opcode].fmt, lir, buf, baseAddr,
256);
LOGD("%p (%04x): %-8s%s%s\n",
baseAddr + offset, offset, opName, buf,
kArmCondNv = 0xf, /* 1111 */
} ArmConditionCode;
-#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
+#define isPseudoOpcode(opcode) ((int)(opcode) < 0)
/*
* The following enum defines the list of supported Thumb instructions by the
* assembler. Their corresponding snippet positions will be defined in
* Assemble.c.
*/
-typedef enum ArmOpCode {
+typedef enum ArmOpcode {
kArmChainingCellBottom = -18,
kArmPseudoBarrier = -17,
kArmPseudoExtended = -16,
kThumb2Dmb, /* dmb [1111001110111111100011110101] option[3-0] */
kArmLast,
-} ArmOpCode;
+} ArmOpcode;
/* DMB option encodings */
typedef enum ArmOpDmbOptions {
int end; /* end for kFmtBitBlt, 1-bit slice end for FP regs */
int start; /* start for kFmtBitBlt, 4-bit slice end for FP regs */
} fieldLoc[4];
- ArmOpCode opCode;
+ ArmOpcode opcode;
int flags;
char *name;
char* fmt;
*/
typedef struct ArmLIR {
LIR generic;
- ArmOpCode opCode;
+ ArmOpcode opcode;
int operands[4]; // [0..3] = [dest, src1, src2, extra]
bool isNop; // LIR is optimized away
bool branchInsertSV;// mark for insertion of branch before this instruction,
#define MAX_ASSEMBLER_RETRIES 10
/*
- * opcode: ArmOpCode enum
+ * opcode: ArmOpcode enum
* skeleton: pre-designated bit-pattern for this opcode
* k0: key to applying ds/de
* ds: dest start bit position
ArmLIR *lir;
for (lir = (ArmLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
- if (lir->opCode < 0) {
- if ((lir->opCode == kArmPseudoPseudoAlign4) &&
+ if (lir->opcode < 0) {
+ if ((lir->opcode == kArmPseudoPseudoAlign4) &&
/* 1 means padding is needed */
(lir->operands[0] == 1)) {
*bufferAddr++ = PADDING_MOV_R5_R5;
continue;
}
- if (lir->opCode == kThumbLdrPcRel ||
- lir->opCode == kThumb2LdrPcRel12 ||
- lir->opCode == kThumbAddPcRel ||
- ((lir->opCode == kThumb2Vldrs) && (lir->operands[1] == rpc))) {
+ if (lir->opcode == kThumbLdrPcRel ||
+ lir->opcode == kThumb2LdrPcRel12 ||
+ lir->opcode == kThumbAddPcRel ||
+ ((lir->opcode == kThumb2Vldrs) && (lir->operands[1] == rpc))) {
ArmLIR *lirTarget = (ArmLIR *) lir->generic.target;
intptr_t pc = (lir->generic.offset + 4) & ~3;
intptr_t target = lirTarget->generic.offset;
LOGE("PC-rel distance is not multiples of 4: %d\n", delta);
dvmCompilerAbort(cUnit);
}
- if ((lir->opCode == kThumb2LdrPcRel12) && (delta > 4091)) {
+ if ((lir->opcode == kThumb2LdrPcRel12) && (delta > 4091)) {
return kRetryHalve;
} else if (delta > 1020) {
return kRetryHalve;
}
- if (lir->opCode == kThumb2Vldrs) {
+ if (lir->opcode == kThumb2Vldrs) {
lir->operands[2] = delta >> 2;
} else {
- lir->operands[1] = (lir->opCode == kThumb2LdrPcRel12) ?
+ lir->operands[1] = (lir->opcode == kThumb2LdrPcRel12) ?
delta : delta >> 2;
}
- } else if (lir->opCode == kThumb2Cbnz || lir->opCode == kThumb2Cbz) {
+ } else if (lir->opcode == kThumb2Cbnz || lir->opcode == kThumb2Cbz) {
ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
intptr_t pc = lir->generic.offset + 4;
intptr_t target = targetLIR->generic.offset;
/* Convert to cmp rx,#0 / b[eq/ne] tgt pair */
ArmLIR *newInst = dvmCompilerNew(sizeof(ArmLIR), true);
/* Make new branch instruction and insert after */
- newInst->opCode = kThumbBCond;
+ newInst->opcode = kThumbBCond;
newInst->operands[0] = 0;
- newInst->operands[1] = (lir->opCode == kThumb2Cbz) ?
+ newInst->operands[1] = (lir->opcode == kThumb2Cbz) ?
kArmCondEq : kArmCondNe;
newInst->generic.target = lir->generic.target;
dvmCompilerSetupResourceMasks(newInst);
dvmCompilerInsertLIRAfter((LIR *)lir, (LIR *)newInst);
/* Convert the cb[n]z to a cmp rx, #0 ] */
- lir->opCode = kThumbCmpRI8;
+ lir->opcode = kThumbCmpRI8;
/* operand[0] is src1 in both cb[n]z & CmpRI8 */
lir->operands[1] = 0;
lir->generic.target = 0;
} else {
lir->operands[1] = delta >> 1;
}
- } else if (lir->opCode == kThumbBCond ||
- lir->opCode == kThumb2BCond) {
+ } else if (lir->opcode == kThumbBCond ||
+ lir->opcode == kThumb2BCond) {
ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
intptr_t pc = lir->generic.offset + 4;
intptr_t target = targetLIR->generic.offset;
int delta = target - pc;
- if ((lir->opCode == kThumbBCond) && (delta > 254 || delta < -256)) {
+ if ((lir->opcode == kThumbBCond) && (delta > 254 || delta < -256)) {
return kRetryHalve;
}
lir->operands[0] = delta >> 1;
- } else if (lir->opCode == kThumbBUncond) {
+ } else if (lir->opcode == kThumbBUncond) {
ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
intptr_t pc = lir->generic.offset + 4;
intptr_t target = targetLIR->generic.offset;
dvmCompilerAbort(cUnit);
}
lir->operands[0] = delta >> 1;
- } else if (lir->opCode == kThumbBlx1) {
- assert(NEXT_LIR(lir)->opCode == kThumbBlx2);
+ } else if (lir->opcode == kThumbBlx1) {
+ assert(NEXT_LIR(lir)->opcode == kThumbBlx2);
/* curPC is Thumb */
intptr_t curPC = (startAddr + lir->generic.offset + 4) & ~3;
intptr_t target = lir->operands[1];
NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff;
}
- ArmEncodingMap *encoder = &EncodingMap[lir->opCode];
+ ArmEncodingMap *encoder = &EncodingMap[lir->opcode];
u4 bits = encoder->skeleton;
int i;
for (i = 0; i < 4; i++) {
armLIR;
armLIR = NEXT_LIR(armLIR)) {
armLIR->generic.offset = offset;
- if (armLIR->opCode >= 0 && !armLIR->isNop) {
- armLIR->size = EncodingMap[armLIR->opCode].size * 2;
+ if (armLIR->opcode >= 0 && !armLIR->isNop) {
+ armLIR->size = EncodingMap[armLIR->opcode].size * 2;
offset += armLIR->size;
- } else if (armLIR->opCode == kArmPseudoPseudoAlign4) {
+ } else if (armLIR->opcode == kArmPseudoPseudoAlign4) {
if (offset & 0x2) {
offset += 2;
armLIR->operands[0] = 1;
ArmLIR *chainCellOffsetLIR = (ArmLIR *) cUnit->chainCellOffsetLIR;
assert(chainCellOffsetLIR);
assert(chainCellOffset < 0x10000);
- assert(chainCellOffsetLIR->opCode == kArm16BitData &&
+ assert(chainCellOffsetLIR->opcode == kArm16BitData &&
chainCellOffsetLIR->operands[0] == CHAIN_CELL_OFFSET_TAG);
/*
* Returns the skeleton bit pattern associated with an opcode. All
* variable fields are zeroed.
*/
-static u4 getSkeleton(ArmOpCode op)
+static u4 getSkeleton(ArmOpcode op)
{
return EncodingMap[op].skeleton;
}
{
u8 *maskPtr;
u8 mask;
- assert( EncodingMap[lir->opCode].flags & (IS_LOAD | IS_STORE));
+ assert( EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE));
if (isLoad) {
maskPtr = &lir->useMask;
mask = ENCODE_MEM_USE;
*/
static void setupResourceMasks(ArmLIR *lir)
{
- int opCode = lir->opCode;
+ int opcode = lir->opcode;
int flags;
- if (opCode <= 0) {
+ if (opcode <= 0) {
lir->useMask = lir->defMask = 0;
return;
}
- flags = EncodingMap[lir->opCode].flags;
+ flags = EncodingMap[lir->opcode].flags;
/* Set up the mask for resources that are updated */
if (flags & (IS_LOAD | IS_STORE)) {
* The following are building blocks to construct low-level IRs with 0 - 4
* operands.
*/
-static ArmLIR *newLIR0(CompilationUnit *cUnit, ArmOpCode opCode)
+static ArmLIR *newLIR0(CompilationUnit *cUnit, ArmOpcode opcode)
{
ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
- assert(isPseudoOpCode(opCode) || (EncodingMap[opCode].flags & NO_OPERAND));
- insn->opCode = opCode;
+ assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
+ insn->opcode = opcode;
setupResourceMasks(insn);
dvmCompilerAppendLIR(cUnit, (LIR *) insn);
return insn;
}
-static ArmLIR *newLIR1(CompilationUnit *cUnit, ArmOpCode opCode,
+static ArmLIR *newLIR1(CompilationUnit *cUnit, ArmOpcode opcode,
int dest)
{
ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
- assert(isPseudoOpCode(opCode) || (EncodingMap[opCode].flags & IS_UNARY_OP));
- insn->opCode = opCode;
+ assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP));
+ insn->opcode = opcode;
insn->operands[0] = dest;
setupResourceMasks(insn);
dvmCompilerAppendLIR(cUnit, (LIR *) insn);
return insn;
}
-static ArmLIR *newLIR2(CompilationUnit *cUnit, ArmOpCode opCode,
+static ArmLIR *newLIR2(CompilationUnit *cUnit, ArmOpcode opcode,
int dest, int src1)
{
ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
- assert(isPseudoOpCode(opCode) ||
- (EncodingMap[opCode].flags & IS_BINARY_OP));
- insn->opCode = opCode;
+ assert(isPseudoOpcode(opcode) ||
+ (EncodingMap[opcode].flags & IS_BINARY_OP));
+ insn->opcode = opcode;
insn->operands[0] = dest;
insn->operands[1] = src1;
setupResourceMasks(insn);
return insn;
}
-static ArmLIR *newLIR3(CompilationUnit *cUnit, ArmOpCode opCode,
+static ArmLIR *newLIR3(CompilationUnit *cUnit, ArmOpcode opcode,
int dest, int src1, int src2)
{
ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
- if (!(EncodingMap[opCode].flags & IS_TERTIARY_OP)) {
- LOGE("Bad LIR3: %s[%d]",EncodingMap[opCode].name,opCode);
+ if (!(EncodingMap[opcode].flags & IS_TERTIARY_OP)) {
+ LOGE("Bad LIR3: %s[%d]",EncodingMap[opcode].name,opcode);
}
- assert(isPseudoOpCode(opCode) ||
- (EncodingMap[opCode].flags & IS_TERTIARY_OP));
- insn->opCode = opCode;
+ assert(isPseudoOpcode(opcode) ||
+ (EncodingMap[opcode].flags & IS_TERTIARY_OP));
+ insn->opcode = opcode;
insn->operands[0] = dest;
insn->operands[1] = src1;
insn->operands[2] = src2;
}
#if defined(_ARMV7_A) || defined(_ARMV7_A_NEON)
-static ArmLIR *newLIR4(CompilationUnit *cUnit, ArmOpCode opCode,
+static ArmLIR *newLIR4(CompilationUnit *cUnit, ArmOpcode opcode,
int dest, int src1, int src2, int info)
{
ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
- assert(isPseudoOpCode(opCode) ||
- (EncodingMap[opCode].flags & IS_QUAD_OP));
- insn->opCode = opCode;
+ assert(isPseudoOpcode(opcode) ||
+ (EncodingMap[opcode].flags & IS_QUAD_OP));
+ insn->opcode = opcode;
insn->operands[0] = dest;
insn->operands[1] = src1;
insn->operands[2] = src2;
bool fpHint)
{
if (mir->next &&
- ((mir->next->dalvikInsn.opCode == OP_MOVE_RESULT) ||
- (mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_OBJECT))) {
- mir->next->dalvikInsn.opCode = OP_NOP;
+ ((mir->next->dalvikInsn.opcode == OP_MOVE_RESULT) ||
+ (mir->next->dalvikInsn.opcode == OP_MOVE_RESULT_OBJECT))) {
+ mir->next->dalvikInsn.opcode = OP_NOP;
return dvmCompilerGetDest(cUnit, mir->next, 0);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL;
bool fpHint)
{
if (mir->next &&
- (mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_WIDE)) {
- mir->next->dalvikInsn.opCode = OP_NOP;
+ (mir->next->dalvikInsn.opcode == OP_MOVE_RESULT_WIDE)) {
+ mir->next->dalvikInsn.opcode = OP_NOP;
return dvmCompilerGetDestWide(cUnit, mir->next, 0, 1);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL_WIDE;
if (pcrLabel == NULL) {
int dPC = (int) (cUnit->method->insns + dOffset);
pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
- pcrLabel->opCode = kArmPseudoPCReconstructionCell;
+ pcrLabel->opcode = kArmPseudoPCReconstructionCell;
pcrLabel->operands[0] = dPC;
pcrLabel->operands[1] = dOffset;
/* Insert the place holder to the growable list */
RegLocation rlResult;
void* funct;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_FLOAT_2ADDR:
case OP_ADD_FLOAT:
funct = (void*) __aeabi_fadd;
RegLocation rlResult;
void* funct;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_DOUBLE_2ADDR:
case OP_ADD_DOUBLE:
funct = (void*) __aeabi_dadd;
static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
- switch (opCode) {
+ switch (opcode) {
case OP_INT_TO_FLOAT:
return genConversionCall(cUnit, mir, (void*)__aeabi_i2f, 1, 1);
case OP_FLOAT_TO_INT:
}
#if defined(WITH_SELF_VERIFICATION)
-static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpCode opCode,
+static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpcode opcode,
int dest, int src1)
{
ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
- insn->opCode = opCode;
+ insn->opcode = opcode;
insn->operands[0] = dest;
insn->operands[1] = src1;
setupResourceMasks(insn);
static void selfVerificationBranchInsertPass(CompilationUnit *cUnit)
{
ArmLIR *thisLIR;
- TemplateOpCode opCode = TEMPLATE_MEM_OP_DECODE;
+ TemplateOpcode opcode = TEMPLATE_MEM_OP_DECODE;
for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn;
thisLIR != (ArmLIR *) cUnit->lastLIRInsn;
if (thisLIR->branchInsertSV) {
/* Branch to mem op decode template */
selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx1,
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx2,
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
+ (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
}
}
}
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirect(cUnit, rlShift, r2);
- switch( mir->dalvikInsn.opCode) {
+ switch( mir->dalvikInsn.opcode) {
case OP_SHL_LONG:
case OP_SHL_LONG_2ADDR:
genDispatchToHandler(cUnit, TEMPLATE_SHL_LONG);
void *callTgt;
int retReg = r0;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_NOT_LONG:
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
RegLocation rlResult;
bool shiftOp = false;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_NEG_INT:
op = kOpNeg;
unary = true;
break;
default:
LOGE("Invalid word arith op: 0x%x(%d)",
- mir->dalvikInsn.opCode, mir->dalvikInsn.opCode);
+ mir->dalvikInsn.opcode, mir->dalvikInsn.opcode);
dvmCompilerAbort(cUnit);
}
if (!callOut) {
static bool genArithOp(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
RegLocation rlDest;
RegLocation rlSrc1;
RegLocation rlSrc2;
rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
}
- if ((opCode >= OP_ADD_LONG_2ADDR) && (opCode <= OP_XOR_LONG_2ADDR)) {
+ if ((opcode >= OP_ADD_LONG_2ADDR) && (opcode <= OP_XOR_LONG_2ADDR)) {
return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_LONG) && (opCode <= OP_XOR_LONG)) {
+ if ((opcode >= OP_ADD_LONG) && (opcode <= OP_XOR_LONG)) {
return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_SHL_LONG_2ADDR) && (opCode <= OP_USHR_LONG_2ADDR)) {
+ if ((opcode >= OP_SHL_LONG_2ADDR) && (opcode <= OP_USHR_LONG_2ADDR)) {
return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_SHL_LONG) && (opCode <= OP_USHR_LONG)) {
+ if ((opcode >= OP_SHL_LONG) && (opcode <= OP_USHR_LONG)) {
return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_INT_2ADDR) && (opCode <= OP_USHR_INT_2ADDR)) {
+ if ((opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_USHR_INT_2ADDR)) {
return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_INT) && (opCode <= OP_USHR_INT)) {
+ if ((opcode >= OP_ADD_INT) && (opcode <= OP_USHR_INT)) {
return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_FLOAT_2ADDR) && (opCode <= OP_REM_FLOAT_2ADDR)) {
+ if ((opcode >= OP_ADD_FLOAT_2ADDR) && (opcode <= OP_REM_FLOAT_2ADDR)) {
return genArithOpFloat(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_FLOAT) && (opCode <= OP_REM_FLOAT)) {
+ if ((opcode >= OP_ADD_FLOAT) && (opcode <= OP_REM_FLOAT)) {
return genArithOpFloat(cUnit, mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_DOUBLE_2ADDR) && (opCode <= OP_REM_DOUBLE_2ADDR)) {
+ if ((opcode >= OP_ADD_DOUBLE_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) {
return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
- if ((opCode >= OP_ADD_DOUBLE) && (opCode <= OP_REM_DOUBLE)) {
+ if ((opcode >= OP_ADD_DOUBLE) && (opcode <= OP_REM_DOUBLE)) {
return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
}
return true;
ArmLIR *branch = genUnconditionalBranch(cUnit, NULL);
/* Set up the place holder to reconstruct this Dalvik PC */
ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
- pcrLabel->opCode = kArmPseudoPCReconstructionCell;
+ pcrLabel->opcode = kArmPseudoPCReconstructionCell;
pcrLabel->operands[0] = dPC;
pcrLabel->operands[1] = mir->offset;
/* Insert the place holder to the growable list */
if (pcrLabel == NULL) {
int dPC = (int) (cUnit->method->insns + mir->offset);
pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
- pcrLabel->opCode = kArmPseudoPCReconstructionCell;
+ pcrLabel->opcode = kArmPseudoPCReconstructionCell;
pcrLabel->operands[0] = dPC;
pcrLabel->operands[1] = mir->offset;
/* Insert the place holder to the growable list */
*/
static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
{
- int flags = dexGetInstrFlags(mir->dalvikInsn.opCode);
+ int flags = dexGetInstrFlags(mir->dalvikInsn.opcode);
int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn |
kInstrCanThrow;
//If already optimized out, just ignore
- if (mir->dalvikInsn.opCode == OP_NOP)
+ if (mir->dalvikInsn.opcode == OP_NOP)
return;
//Ugly, but necessary. Flush all Dalvik regs so Interp can find them
*/
static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir)
{
- bool isEnter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER);
+ bool isEnter = (mir->dalvikInsn.opcode == OP_MONITOR_ENTER);
genExportPC(cUnit, mir);
dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
- if ((dalvikOpCode >= OP_UNUSED_3E) && (dalvikOpCode <= OP_UNUSED_43)) {
- LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode);
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
+ if ((dalvikOpcode >= OP_UNUSED_3E) && (dalvikOpcode <= OP_UNUSED_43)) {
+ LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode);
return true;
}
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_RETURN_VOID_BARRIER:
dvmCompilerGenMemBarrier(cUnit, kST);
// Intentional fallthrough
case OP_UNUSED_79:
case OP_UNUSED_7A:
case OP_UNUSED_FF:
- LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode);
+ LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode);
return true;
case OP_NOP:
break;
rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_CONST:
case OP_CONST_4: {
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
}
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_CONST_HIGH16: {
loadConstantNoClobber(cUnit, rlResult.lowReg,
mir->dalvikInsn.vB << 16);
RegLocation rlDest;
RegLocation rlSrc;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_CONST_STRING_JUMBO:
case OP_CONST_STRING: {
void *strPtr = (void*)
dvmAbort();
}
- isVolatile = (mir->dalvikInsn.opCode == OP_SGET_VOLATILE) ||
- (mir->dalvikInsn.opCode == OP_SGET_OBJECT_VOLATILE) ||
+ isVolatile = (mir->dalvikInsn.opcode == OP_SGET_VOLATILE) ||
+ (mir->dalvikInsn.opcode == OP_SGET_OBJECT_VOLATILE) ||
dvmIsVolatileField(fieldPtr);
rlDest = dvmCompilerGetDest(cUnit, mir, 0);
void *fieldPtr = (void*)
(method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
- isVolatile = (mir->dalvikInsn.opCode == OP_SPUT_VOLATILE) ||
- (mir->dalvikInsn.opCode == OP_SPUT_OBJECT_VOLATILE) ||
+ isVolatile = (mir->dalvikInsn.opcode == OP_SPUT_VOLATILE) ||
+ (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE) ||
dvmIsVolatileField(fieldPtr);
- isSputObject = (mir->dalvikInsn.opCode == OP_SPUT_OBJECT) ||
- (mir->dalvikInsn.opCode == OP_SPUT_OBJECT_VOLATILE);
+ isSputObject = (mir->dalvikInsn.opcode == OP_SPUT_OBJECT) ||
+ (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE);
if (fieldPtr == NULL) {
LOGE("Unexpected null static field");
*/
static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
RegLocation rlResult;
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_MOVE_EXCEPTION: {
int offset = offsetof(InterpState, self);
int exOffset = offsetof(Thread, exception);
static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
RegLocation rlDest;
RegLocation rlSrc;
RegLocation rlResult;
- if ( (opCode >= OP_ADD_INT_2ADDR) && (opCode <= OP_REM_DOUBLE_2ADDR)) {
+ if ( (opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) {
return genArithOp( cUnit, mir );
}
else
rlDest = dvmCompilerGetDest(cUnit, mir, 0);
- switch (opCode) {
+ switch (opcode) {
case OP_DOUBLE_TO_INT:
case OP_INT_TO_FLOAT:
case OP_FLOAT_TO_INT:
static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
RegLocation rlDest;
RegLocation rlResult;
int BBBB = mir->dalvikInsn.vB;
- if (dalvikOpCode == OP_CONST_WIDE_16) {
+ if (dalvikOpcode == OP_CONST_WIDE_16) {
rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
//TUNING: do high separately to avoid load dependency
opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31);
storeValueWide(cUnit, rlDest, rlResult);
- } else if (dalvikOpCode == OP_CONST_16) {
+ } else if (dalvikOpcode == OP_CONST_16) {
rlDest = dvmCompilerGetDest(cUnit, mir, 0);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
ArmLIR *labelList)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
ArmConditionCode cond;
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0);
//TUNING: break this out to allow use of Thumb2 CB[N]Z
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_IF_EQZ:
cond = kArmCondEq;
break;
break;
default:
cond = 0;
- LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpCode);
+ LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpcode);
dvmCompilerAbort(cUnit);
}
genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
// Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit'
// and store the result in 'rlDest'.
-static bool handleEasyDivide(CompilationUnit *cUnit, OpCode dalvikOpCode,
+static bool handleEasyDivide(CompilationUnit *cUnit, Opcode dalvikOpcode,
RegLocation rlSrc, RegLocation rlDest, int lit)
{
if (lit < 2 || !isPowerOfTwo(lit)) {
// Avoid special cases.
return false;
}
- bool div = (dalvikOpCode == OP_DIV_INT_LIT8 || dalvikOpCode == OP_DIV_INT_LIT16);
+ bool div = (dalvikOpcode == OP_DIV_INT_LIT8 || dalvikOpcode == OP_DIV_INT_LIT16);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
if (div) {
static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
int shiftOp = false;
bool isDiv = false;
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_RSUB_INT_LIT8:
case OP_RSUB_INT: {
int tReg;
genInterpSingleStep(cUnit, mir);
return false;
}
- if (handleEasyDivide(cUnit, dalvikOpCode, rlSrc, rlDest, lit)) {
+ if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) {
return false;
}
dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0);
dvmCompilerClobber(cUnit, r0);
- if ((dalvikOpCode == OP_DIV_INT_LIT8) ||
- (dalvikOpCode == OP_DIV_INT_LIT16)) {
+ if ((dalvikOpcode == OP_DIV_INT_LIT8) ||
+ (dalvikOpcode == OP_DIV_INT_LIT16)) {
LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idiv);
isDiv = true;
} else {
static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
int fieldOffset = -1;
bool isVolatile = false;
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
/*
* Wide volatiles currently handled via single step.
* Add them here if generating in-line code.
break;
}
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_NEW_ARRAY: {
// Generates a call - use explicit registers
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
int fieldOffset = mir->dalvikInsn.vC;
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_IGET_QUICK:
case OP_IGET_OBJECT_QUICK:
genIGet(cUnit, mir, kWord, fieldOffset, false);
static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
ArmLIR *labelList)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
ArmConditionCode cond;
RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
- switch (dalvikOpCode) {
+ switch (dalvikOpcode) {
case OP_IF_EQ:
cond = kArmCondEq;
break;
break;
default:
cond = 0;
- LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpCode);
+ LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpcode);
dvmCompilerAbort(cUnit);
}
genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
- switch (opCode) {
+ switch (opcode) {
case OP_MOVE_16:
case OP_MOVE_OBJECT_16:
case OP_MOVE_FROM16:
static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
RegLocation rlSrc1;
RegLocation rlSrc2;
RegLocation rlDest;
- if ( (opCode >= OP_ADD_INT) && (opCode <= OP_REM_DOUBLE)) {
+ if ( (opcode >= OP_ADD_INT) && (opcode <= OP_REM_DOUBLE)) {
return genArithOp( cUnit, mir );
}
}
- switch (opCode) {
+ switch (opcode) {
case OP_CMPL_FLOAT:
case OP_CMPG_FLOAT:
case OP_CMPL_DOUBLE:
static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
{
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
- switch (dalvikOpCode) {
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
+ switch (dalvikOpcode) {
case OP_FILL_ARRAY_DATA: {
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
// Making a call - use explicit registers
dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r1);
dvmCompilerLockAllTemps(cUnit);
- if (dalvikOpCode == OP_PACKED_SWITCH) {
+ if (dalvikOpcode == OP_PACKED_SWITCH) {
LOAD_FUNC_ADDR(cUnit, r4PC, (int)findPackedSwitchIndex);
} else {
LOAD_FUNC_ADDR(cUnit, r4PC, (int)findSparseSwitchIndex);
retChainingCell = &labelList[bb->fallThrough->id];
DecodedInstruction *dInsn = &mir->dalvikInsn;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
/*
* calleeMethod = this->clazz->vtable[
* method->clazz->pDvmDex->pResMethods[BBBB]->methodIndex
genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
}
- if (mir->dalvikInsn.opCode == OP_INVOKE_VIRTUAL)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
else
genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
cUnit->method->clazz->pDvmDex->
pResMethods[dInsn->vB]->methodIndex]);
- if (mir->dalvikInsn.opCode == OP_INVOKE_SUPER)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
else
genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
assert(calleeMethod ==
cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
- if (mir->dalvikInsn.opCode == OP_INVOKE_DIRECT)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_DIRECT)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
else
genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
assert(calleeMethod ==
cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
- if (mir->dalvikInsn.opCode == OP_INVOKE_STATIC)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_STATIC)
genProcessArgsNoRange(cUnit, mir, dInsn,
NULL /* no null check */);
else
genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
}
- if (mir->dalvikInsn.opCode == OP_INVOKE_INTERFACE)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_INTERFACE)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
else
genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
if (pcrLabel == NULL) {
int dPC = (int) (cUnit->method->insns + mir->offset);
pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
- pcrLabel->opCode = kArmPseudoPCReconstructionCell;
+ pcrLabel->opcode = kArmPseudoPCReconstructionCell;
pcrLabel->operands[0] = dPC;
pcrLabel->operands[1] = mir->offset;
/* Insert the place holder to the growable list */
return false;
DecodedInstruction *dInsn = &mir->dalvikInsn;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
/* calleeMethod = this->clazz->vtable[BBBB] */
case OP_INVOKE_VIRTUAL_QUICK_RANGE:
case OP_INVOKE_VIRTUAL_QUICK: {
genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
}
- if (mir->dalvikInsn.opCode == OP_INVOKE_VIRTUAL_QUICK)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL_QUICK)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
else
genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
assert(calleeMethod ==
cUnit->method->clazz->super->vtable[dInsn->vB]);
- if (mir->dalvikInsn.opCode == OP_INVOKE_SUPER_QUICK)
+ if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER_QUICK)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
else
genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- switch( mir->dalvikInsn.opCode) {
+ switch( mir->dalvikInsn.opcode) {
case OP_EXECUTE_INLINE_RANGE:
case OP_EXECUTE_INLINE: {
unsigned int i;
/* Extended MIR instructions like PHI */
static void handleExtendedMIR(CompilationUnit *cUnit, MIR *mir)
{
- int opOffset = mir->dalvikInsn.opCode - kMirOpFirst;
+ int opOffset = mir->dalvikInsn.opcode - kMirOpFirst;
char *msg = dvmCompilerNew(strlen(extendedMIROpNames[opOffset]) + 1,
false);
strcpy(msg, extendedMIROpNames[opOffset]);
newLIR1(cUnit, kArmPseudoExtended, (int) msg);
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case kMirOpPhi: {
char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString);
{
/* Set up the place holder to reconstruct this Dalvik PC */
ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
- pcrLabel->opCode = kArmPseudoPCReconstructionCell;
+ pcrLabel->opcode = kArmPseudoPCReconstructionCell;
pcrLabel->operands[0] =
(int) (cUnit->method->insns + entry->startOffset);
pcrLabel->operands[1] = entry->startOffset;
* other branch to the PCR cell to punt.
*/
ArmLIR *branchToBody = dvmCompilerNew(sizeof(ArmLIR), true);
- branchToBody->opCode = kThumbBUncond;
+ branchToBody->opcode = kThumbBUncond;
branchToBody->generic.target = (LIR *) bodyLabel;
setupResourceMasks(branchToBody);
cUnit->loopAnalysis->branchToBody = (LIR *) branchToBody;
ArmLIR *branchToPCR = dvmCompilerNew(sizeof(ArmLIR), true);
- branchToPCR->opCode = kThumbBUncond;
+ branchToPCR->opcode = kThumbBUncond;
branchToPCR->generic.target = (LIR *) pcrLabel;
setupResourceMasks(branchToPCR);
cUnit->loopAnalysis->branchToPCR = (LIR *) branchToPCR;
static bool selfVerificationPuntOps(MIR *mir)
{
DecodedInstruction *decInsn = &mir->dalvikInsn;
- OpCode op = decInsn->opCode;
+ Opcode op = decInsn->opcode;
/*
* All opcodes that can throw exceptions and use the
}
if (blockList[i]->blockType == kTraceEntryBlock) {
- labelList[i].opCode = kArmPseudoEntryBlock;
+ labelList[i].opcode = kArmPseudoEntryBlock;
if (blockList[i]->firstMIRInsn == NULL) {
continue;
} else {
&labelList[blockList[i]->fallThrough->id]);
}
} else if (blockList[i]->blockType == kTraceExitBlock) {
- labelList[i].opCode = kArmPseudoExitBlock;
+ labelList[i].opcode = kArmPseudoExitBlock;
goto gen_fallthrough;
} else if (blockList[i]->blockType == kDalvikByteCode) {
- labelList[i].opCode = kArmPseudoNormalBlockLabel;
+ labelList[i].opcode = kArmPseudoNormalBlockLabel;
/* Reset the register state */
dvmCompilerResetRegPool(cUnit);
dvmCompilerClobberAllRegs(cUnit);
} else {
switch (blockList[i]->blockType) {
case kChainingCellNormal:
- labelList[i].opCode = kArmPseudoChainingCellNormal;
+ labelList[i].opcode = kArmPseudoChainingCellNormal;
/* handle the codegen later */
dvmInsertGrowableList(
&chainingListByType[kChainingCellNormal], (void *) i);
break;
case kChainingCellInvokeSingleton:
- labelList[i].opCode =
+ labelList[i].opcode =
kArmPseudoChainingCellInvokeSingleton;
labelList[i].operands[0] =
(int) blockList[i]->containingMethod;
(void *) i);
break;
case kChainingCellInvokePredicted:
- labelList[i].opCode =
+ labelList[i].opcode =
kArmPseudoChainingCellInvokePredicted;
/* handle the codegen later */
dvmInsertGrowableList(
(void *) i);
break;
case kChainingCellHot:
- labelList[i].opCode =
+ labelList[i].opcode =
kArmPseudoChainingCellHot;
/* handle the codegen later */
dvmInsertGrowableList(
break;
case kPCReconstruction:
/* Make sure exception handling block is next */
- labelList[i].opCode =
+ labelList[i].opcode =
kArmPseudoPCReconstructionBlockLabel;
assert (i == cUnit->numBlocks - 2);
handlePCReconstruction(cUnit, &labelList[i+1]);
break;
case kExceptionHandling:
- labelList[i].opCode = kArmPseudoEHBlockLabel;
+ labelList[i].opcode = kArmPseudoEHBlockLabel;
if (cUnit->pcReconstructionList.numUsed) {
loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
jitToInterpEntries.dvmJitToInterpPunt),
break;
#if defined(WITH_SELF_VERIFICATION) || defined(WITH_JIT_TUNING)
case kChainingCellBackwardBranch:
- labelList[i].opCode =
+ labelList[i].opcode =
kArmPseudoChainingCellBackwardBranch;
/* handle the codegen later */
dvmInsertGrowableList(
dvmCompilerResetDefTracking(cUnit);
}
- if (mir->dalvikInsn.opCode >= kMirOpFirst) {
+ if (mir->dalvikInsn.opcode >= kMirOpFirst) {
handleExtendedMIR(cUnit, mir);
continue;
}
- OpCode dalvikOpCode = mir->dalvikInsn.opCode;
- InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpCode);
+ Opcode dalvikOpcode = mir->dalvikInsn.opcode;
+ InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpcode);
char *note;
if (mir->OptimizationFlags & MIR_INLINED) {
note = " (I)";
* Debugging: screen the opcode first to see if it is in the
* do[-not]-compile list
*/
- bool singleStepMe = SINGLE_STEP_OP(dalvikOpCode);
+ bool singleStepMe = SINGLE_STEP_OP(dalvikOpcode);
#if defined(WITH_SELF_VERIFICATION)
if (singleStepMe == false) {
singleStepMe = selfVerificationPuntOps(mir);
notHandled = false;
genInterpSingleStep(cUnit, mir);
} else {
- opcodeCoverage[dalvikOpCode]++;
+ opcodeCoverage[dalvikOpcode]++;
switch (dalvikFormat) {
case kFmt10t:
case kFmt20t:
if (notHandled) {
LOGE("%#06x: Opcode 0x%x (%s) / Fmt %d not handled\n",
mir->offset,
- dalvikOpCode, dexGetOpcodeName(dalvikOpCode),
+ dalvikOpcode, dexGetOpcodeName(dalvikOpcode),
dalvikFormat);
dvmCompilerAbort(cUnit);
break;
int i;
for (i = 0; i < kArmLast; i++) {
- if (EncodingMap[i].opCode != i) {
+ if (EncodingMap[i].opcode != i) {
LOGE("Encoding order for %s is wrong: expecting %d, seeing %d",
- EncodingMap[i].name, i, EncodingMap[i].opCode);
+ EncodingMap[i].name, i, EncodingMap[i].opcode);
dvmAbort(); // OK to dvmAbort - build error
}
}
* Don't attempt to optimize register usage since these opcodes call out to
* the handlers.
*/
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_FLOAT_2ADDR:
case OP_ADD_FLOAT:
op = kThumb2Vadds;
int op = kThumbBkpt;
RegLocation rlResult;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_DOUBLE_2ADDR:
case OP_ADD_DOUBLE:
op = kThumb2Vaddd;
static bool genConversion(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
int op = kThumbBkpt;
bool longSrc = false;
bool longDest = false;
RegLocation rlDest;
RegLocation rlResult;
- switch (opCode) {
+ switch (opcode) {
case OP_INT_TO_FLOAT:
longSrc = false;
longDest = false;
int defaultResult;
RegLocation rlResult;
- switch(mir->dalvikInsn.opCode) {
+ switch(mir->dalvikInsn.opcode) {
case OP_CMPL_FLOAT:
isDouble = false;
defaultResult = -1;
* Don't attempt to optimize register usage since these opcodes call out to
* the handlers.
*/
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_CMPL_FLOAT:
loadValueDirectFixed(cUnit, rlSrc1, r0);
loadValueDirectFixed(cUnit, rlSrc2, r1);
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
- TemplateOpCode opCode;
+ TemplateOpcode opcode;
/*
* Don't attempt to optimize register usage since these opcodes call out to
* the handlers.
*/
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_FLOAT_2ADDR:
case OP_ADD_FLOAT:
- opCode = TEMPLATE_ADD_FLOAT_VFP;
+ opcode = TEMPLATE_ADD_FLOAT_VFP;
break;
case OP_SUB_FLOAT_2ADDR:
case OP_SUB_FLOAT:
- opCode = TEMPLATE_SUB_FLOAT_VFP;
+ opcode = TEMPLATE_SUB_FLOAT_VFP;
break;
case OP_DIV_FLOAT_2ADDR:
case OP_DIV_FLOAT:
- opCode = TEMPLATE_DIV_FLOAT_VFP;
+ opcode = TEMPLATE_DIV_FLOAT_VFP;
break;
case OP_MUL_FLOAT_2ADDR:
case OP_MUL_FLOAT:
- opCode = TEMPLATE_MUL_FLOAT_VFP;
+ opcode = TEMPLATE_MUL_FLOAT_VFP;
break;
case OP_REM_FLOAT_2ADDR:
case OP_REM_FLOAT:
loadValueAddressDirect(cUnit, rlDest, r0);
loadValueAddressDirect(cUnit, rlSrc1, r1);
loadValueAddressDirect(cUnit, rlSrc2, r2);
- genDispatchToHandler(cUnit, opCode);
+ genDispatchToHandler(cUnit, opcode);
rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
if (rlDest.location == kLocPhysReg) {
dvmCompilerClobber(cUnit, rlDest.lowReg);
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
- TemplateOpCode opCode;
+ TemplateOpcode opcode;
- switch (mir->dalvikInsn.opCode) {
+ switch (mir->dalvikInsn.opcode) {
case OP_ADD_DOUBLE_2ADDR:
case OP_ADD_DOUBLE:
- opCode = TEMPLATE_ADD_DOUBLE_VFP;
+ opcode = TEMPLATE_ADD_DOUBLE_VFP;
break;
case OP_SUB_DOUBLE_2ADDR:
case OP_SUB_DOUBLE:
- opCode = TEMPLATE_SUB_DOUBLE_VFP;
+ opcode = TEMPLATE_SUB_DOUBLE_VFP;
break;
case OP_DIV_DOUBLE_2ADDR:
case OP_DIV_DOUBLE:
- opCode = TEMPLATE_DIV_DOUBLE_VFP;
+ opcode = TEMPLATE_DIV_DOUBLE_VFP;
break;
case OP_MUL_DOUBLE_2ADDR:
case OP_MUL_DOUBLE:
- opCode = TEMPLATE_MUL_DOUBLE_VFP;
+ opcode = TEMPLATE_MUL_DOUBLE_VFP;
break;
case OP_REM_DOUBLE_2ADDR:
case OP_REM_DOUBLE:
loadValueAddressDirect(cUnit, rlDest, r0);
loadValueAddressDirect(cUnit, rlSrc1, r1);
loadValueAddressDirect(cUnit, rlSrc2, r2);
- genDispatchToHandler(cUnit, opCode);
+ genDispatchToHandler(cUnit, opcode);
rlDest = dvmCompilerUpdateLocWide(cUnit, rlDest);
if (rlDest.location == kLocPhysReg) {
dvmCompilerClobber(cUnit, rlDest.lowReg);
static bool genConversion(CompilationUnit *cUnit, MIR *mir)
{
- OpCode opCode = mir->dalvikInsn.opCode;
+ Opcode opcode = mir->dalvikInsn.opcode;
bool longSrc = false;
bool longDest = false;
RegLocation rlSrc;
RegLocation rlDest;
- TemplateOpCode template;
- switch (opCode) {
+ TemplateOpcode template;
+ switch (opcode) {
case OP_INT_TO_FLOAT:
longSrc = false;
longDest = false;
static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
- TemplateOpCode template;
+ TemplateOpcode template;
RegLocation rlResult = dvmCompilerGetReturn(cUnit);
bool wide = true;
- switch(mir->dalvikInsn.opCode) {
+ switch(mir->dalvikInsn.opcode) {
case OP_CMPL_FLOAT:
template = TEMPLATE_CMPL_FLOAT_VFP;
wide = false;
thisLIR = NEXT_LIR(thisLIR)) {
/* Branch to the next instruction */
- if (thisLIR->opCode == kThumbBUncond) {
+ if (thisLIR->opcode == kThumbBUncond) {
ArmLIR *nextLIR = thisLIR;
while (true) {
/*
* Found real useful stuff between the branch and the target
*/
- if (!isPseudoOpCode(nextLIR->opCode))
+ if (!isPseudoOpcode(nextLIR->opcode))
break;
}
}
/*
* Saw a real instruction that the store can be sunk after
*/
- if (!isPseudoOpCode(checkLIR->opCode)) {
+ if (!isPseudoOpcode(checkLIR->opcode)) {
sinkDistance++;
}
}
continue;
}
- if (firstLoad && (EncodingMap[thisLIR->opCode].flags & IS_LOAD)) {
+ if (firstLoad && (EncodingMap[thisLIR->opcode].flags & IS_LOAD)) {
/*
* Ensure nothing will be hoisted in front of this load because
* it's result will likely be needed soon.
* Saw a real instruction that hosting the load is
* beneficial
*/
- if (!isPseudoOpCode(checkLIR->opCode)) {
+ if (!isPseudoOpcode(checkLIR->opcode)) {
hoistDistance++;
}
}
* Saw a real instruction that hosting the load is
* beneficial
*/
- if (!isPseudoOpCode(checkLIR->opCode)) {
+ if (!isPseudoOpcode(checkLIR->opcode)) {
hoistDistance++;
}
}
dataTarget = addWordData(cUnit, value, false);
}
ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true);
- loadPcRel->opCode = kThumbLdrPcRel;
+ loadPcRel->opcode = kThumbLdrPcRel;
loadPcRel->generic.target = (LIR *) dataTarget;
loadPcRel->operands[0] = tDest;
setupResourceMasks(loadPcRel);
static ArmLIR *opNone(CompilationUnit *cUnit, OpKind op)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpUncondBr:
- opCode = kThumbBUncond;
+ opcode = kThumbBUncond;
break;
default:
LOGE("Jit: bad case in opNone");
dvmCompilerAbort(cUnit);
}
- return newLIR0(cUnit, opCode);
+ return newLIR0(cUnit, opcode);
}
static ArmLIR *opCondBranch(CompilationUnit *cUnit, ArmConditionCode cc)
static ArmLIR *opImm(CompilationUnit *cUnit, OpKind op, int value)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpPush:
- opCode = kThumbPush;
+ opcode = kThumbPush;
break;
case kOpPop:
- opCode = kThumbPop;
+ opcode = kThumbPop;
break;
default:
LOGE("Jit: bad case in opCondBranch");
dvmCompilerAbort(cUnit);
}
- return newLIR1(cUnit, opCode, value);
+ return newLIR1(cUnit, opcode, value);
}
static ArmLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpBlx:
- opCode = kThumbBlxR;
+ opcode = kThumbBlxR;
break;
default:
LOGE("Jit: bad case in opReg");
dvmCompilerAbort(cUnit);
}
- return newLIR1(cUnit, opCode, rDestSrc);
+ return newLIR1(cUnit, opcode, rDestSrc);
}
static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
bool shortForm = (absValue & 0xff) == absValue;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
if ( !neg && (rDestSrc1 == 13) && (value <= 508)) { /* sp */
assert((value & 0x3) == 0);
return newLIR1(cUnit, kThumbAddSpI7, value >> 2);
} else if (shortForm) {
- opCode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
+ opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
} else
- opCode = kThumbAddRRR;
+ opcode = kThumbAddRRR;
break;
case kOpSub:
if (!neg && (rDestSrc1 == 13) && (value <= 508)) { /* sp */
assert((value & 0x3) == 0);
return newLIR1(cUnit, kThumbSubSpI7, value >> 2);
} else if (shortForm) {
- opCode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
+ opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
} else
- opCode = kThumbSubRRR;
+ opcode = kThumbSubRRR;
break;
case kOpCmp:
if (neg)
shortForm = false;
if (LOWREG(rDestSrc1) && shortForm) {
- opCode = kThumbCmpRI8;
+ opcode = kThumbCmpRI8;
} else if (LOWREG(rDestSrc1)) {
- opCode = kThumbCmpRR;
+ opcode = kThumbCmpRR;
} else {
shortForm = false;
- opCode = kThumbCmpHL;
+ opcode = kThumbCmpHL;
}
break;
default:
break;
}
if (shortForm)
- res = newLIR2(cUnit, opCode, rDestSrc1, absValue);
+ res = newLIR2(cUnit, opcode, rDestSrc1, absValue);
else {
int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
if (op == kOpCmp)
- newLIR2(cUnit, opCode, rDestSrc1, rScratch);
+ newLIR2(cUnit, opcode, rDestSrc1, rScratch);
else
- newLIR3(cUnit, opCode, rDestSrc1, rDestSrc1, rScratch);
+ newLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rScratch);
}
return res;
}
static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
int rSrc1, int rSrc2)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
- opCode = kThumbAddRRR;
+ opcode = kThumbAddRRR;
break;
case kOpSub:
- opCode = kThumbSubRRR;
+ opcode = kThumbSubRRR;
break;
default:
if (rDest == rSrc1) {
}
break;
}
- return newLIR3(cUnit, opCode, rDest, rSrc1, rSrc2);
+ return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
}
static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
ArmLIR *res;
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool shortForm = (absValue & 0x7) == absValue;
switch(op) {
case kOpAdd:
if ((rSrc1 == 13) && (value <= 1020)) { /* sp */
assert((value & 0x3) == 0);
shortForm = true;
- opCode = kThumbAddSpRel;
+ opcode = kThumbAddSpRel;
value >>= 2;
} else if ((rSrc1 == 15) && (value <= 1020)) { /* pc */
assert((value & 0x3) == 0);
shortForm = true;
- opCode = kThumbAddPcRel;
+ opcode = kThumbAddPcRel;
value >>= 2;
} else if (shortForm) {
- opCode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3;
+ opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3;
} else if ((absValue > 0) && (absValue <= (255 + 7))) {
/* Two shots - 1st handle the 7 */
- opCode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3;
- res = newLIR3(cUnit, opCode, rDest, rSrc1, 7);
- opCode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
- newLIR2(cUnit, opCode, rDest, absValue - 7);
+ opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3;
+ res = newLIR3(cUnit, opcode, rDest, rSrc1, 7);
+ opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
+ newLIR2(cUnit, opcode, rDest, absValue - 7);
return res;
} else
- opCode = kThumbAddRRR;
+ opcode = kThumbAddRRR;
break;
case kOpSub:
if (rDest == rSrc1)
return opRegImm(cUnit, op, rDest, value);
if (shortForm) {
- opCode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3;
+ opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3;
} else if ((absValue > 0) && (absValue <= (255 + 7))) {
/* Two shots - 1st handle the 7 */
- opCode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3;
- res = newLIR3(cUnit, opCode, rDest, rSrc1, 7);
- opCode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
- newLIR2(cUnit, opCode, rDest, absValue - 7);
+ opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3;
+ res = newLIR3(cUnit, opcode, rDest, rSrc1, 7);
+ opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
+ newLIR2(cUnit, opcode, rDest, absValue - 7);
return res;
} else
- opCode = kThumbSubRRR;
+ opcode = kThumbSubRRR;
break;
case kOpLsl:
shortForm = (!neg && value <= 31);
- opCode = kThumbLslRRI5;
+ opcode = kThumbLslRRI5;
break;
case kOpLsr:
shortForm = (!neg && value <= 31);
- opCode = kThumbLsrRRI5;
+ opcode = kThumbLsrRRI5;
break;
case kOpAsr:
shortForm = (!neg && value <= 31);
- opCode = kThumbAsrRRI5;
+ opcode = kThumbAsrRRI5;
break;
case kOpMul:
case kOpAnd:
break;
}
if (shortForm)
- res = newLIR3(cUnit, opCode, rDest, rSrc1, absValue);
+ res = newLIR3(cUnit, opcode, rDest, rSrc1, absValue);
else {
if (rDest != rSrc1) {
res = loadConstant(cUnit, rDest, value);
- newLIR3(cUnit, opCode, rDest, rSrc1, rDest);
+ newLIR3(cUnit, opcode, rDest, rSrc1, rDest);
} else {
int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
- newLIR3(cUnit, opCode, rDest, rSrc1, rScratch);
+ newLIR3(cUnit, opcode, rDest, rSrc1, rScratch);
}
}
return res;
int rSrc2)
{
ArmLIR *res;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdc:
- opCode = kThumbAdcRR;
+ opcode = kThumbAdcRR;
break;
case kOpAnd:
- opCode = kThumbAndRR;
+ opcode = kThumbAndRR;
break;
case kOpBic:
- opCode = kThumbBicRR;
+ opcode = kThumbBicRR;
break;
case kOpCmn:
- opCode = kThumbCmnRR;
+ opcode = kThumbCmnRR;
break;
case kOpCmp:
- opCode = kThumbCmpRR;
+ opcode = kThumbCmpRR;
break;
case kOpXor:
- opCode = kThumbEorRR;
+ opcode = kThumbEorRR;
break;
case kOpMov:
if (LOWREG(rDestSrc1) && LOWREG(rSrc2))
- opCode = kThumbMovRR;
+ opcode = kThumbMovRR;
else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2))
- opCode = kThumbMovRR_H2H;
+ opcode = kThumbMovRR_H2H;
else if (LOWREG(rDestSrc1))
- opCode = kThumbMovRR_H2L;
+ opcode = kThumbMovRR_H2L;
else
- opCode = kThumbMovRR_L2H;
+ opcode = kThumbMovRR_L2H;
break;
case kOpMul:
- opCode = kThumbMul;
+ opcode = kThumbMul;
break;
case kOpMvn:
- opCode = kThumbMvn;
+ opcode = kThumbMvn;
break;
case kOpNeg:
- opCode = kThumbNeg;
+ opcode = kThumbNeg;
break;
case kOpOr:
- opCode = kThumbOrr;
+ opcode = kThumbOrr;
break;
case kOpSbc:
- opCode = kThumbSbc;
+ opcode = kThumbSbc;
break;
case kOpTst:
- opCode = kThumbTst;
+ opcode = kThumbTst;
break;
case kOpLsl:
- opCode = kThumbLslRR;
+ opcode = kThumbLslRR;
break;
case kOpLsr:
- opCode = kThumbLsrRR;
+ opcode = kThumbLsrRR;
break;
case kOpAsr:
- opCode = kThumbAsrRR;
+ opcode = kThumbAsrRR;
break;
case kOpRor:
- opCode = kThumbRorRR;
+ opcode = kThumbRorRR;
case kOpAdd:
case kOpSub:
return opRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2);
dvmCompilerAbort(cUnit);
break;
}
- return newLIR2(cUnit, opCode, rDestSrc1, rSrc2);
+ return newLIR2(cUnit, opcode, rDestSrc1, rSrc2);
}
static ArmLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
{
ArmLIR *first = NULL;
ArmLIR *res;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
int rNewIndex = rIndex;
if (scale) {
// Scale the index, but can't trash the original.
}
switch (size) {
case kWord:
- opCode = kThumbLdrRRR;
+ opcode = kThumbLdrRRR;
break;
case kUnsignedHalf:
- opCode = kThumbLdrhRRR;
+ opcode = kThumbLdrhRRR;
break;
case kSignedHalf:
- opCode = kThumbLdrshRRR;
+ opcode = kThumbLdrshRRR;
break;
case kUnsignedByte:
- opCode = kThumbLdrbRRR;
+ opcode = kThumbLdrbRRR;
break;
case kSignedByte:
- opCode = kThumbLdrsbRRR;
+ opcode = kThumbLdrsbRRR;
break;
default:
LOGE("Jit: bad case in loadBaseIndexed");
dvmCompilerAbort(cUnit);
}
- res = newLIR3(cUnit, opCode, rDest, rBase, rNewIndex);
+ res = newLIR3(cUnit, opcode, rDest, rBase, rNewIndex);
#if defined(WITH_SELF_VERIFICATION)
if (cUnit->heapMemOp)
res->branchInsertSV = true;
{
ArmLIR *first = NULL;
ArmLIR *res;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
int rNewIndex = rIndex;
if (scale) {
rNewIndex = dvmCompilerAllocTemp(cUnit);
}
switch (size) {
case kWord:
- opCode = kThumbStrRRR;
+ opcode = kThumbStrRRR;
break;
case kUnsignedHalf:
case kSignedHalf:
- opCode = kThumbStrhRRR;
+ opcode = kThumbStrhRRR;
break;
case kUnsignedByte:
case kSignedByte:
- opCode = kThumbStrbRRR;
+ opcode = kThumbStrbRRR;
break;
default:
LOGE("Jit: bad case in storeBaseIndexed");
dvmCompilerAbort(cUnit);
}
- res = newLIR3(cUnit, opCode, rSrc, rBase, rNewIndex);
+ res = newLIR3(cUnit, opcode, rSrc, rBase, rNewIndex);
#if defined(WITH_SELF_VERIFICATION)
if (cUnit->heapMemOp)
res->branchInsertSV = true;
ArmLIR *res;
ArmLIR *load = NULL;
ArmLIR *load2 = NULL;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
int encodedDisp = displacement;
bool pair = false;
assert((displacement & 0x3) == 0);
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrRRI5;
+ opcode = kThumbLdrRRI5;
} else {
- opCode = kThumbLdrRRR;
+ opcode = kThumbLdrRRR;
}
break;
case kWord:
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrPcRel;
+ opcode = kThumbLdrPcRel;
} else if (LOWREG(rDest) && (rBase == r13) &&
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrSpRel;
+ opcode = kThumbLdrSpRel;
} else if (displacement < 128 && displacement >= 0) {
assert((displacement & 0x3) == 0);
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrRRI5;
+ opcode = kThumbLdrRRI5;
} else {
- opCode = kThumbLdrRRR;
+ opcode = kThumbLdrRRR;
}
break;
case kUnsignedHalf:
assert((displacement & 0x1) == 0);
shortForm = true;
encodedDisp >>= 1;
- opCode = kThumbLdrhRRI5;
+ opcode = kThumbLdrhRRI5;
} else {
- opCode = kThumbLdrhRRR;
+ opcode = kThumbLdrhRRR;
}
break;
case kSignedHalf:
- opCode = kThumbLdrshRRR;
+ opcode = kThumbLdrshRRR;
break;
case kUnsignedByte:
if (displacement < 32 && displacement >= 0) {
shortForm = true;
- opCode = kThumbLdrbRRI5;
+ opcode = kThumbLdrbRRI5;
} else {
- opCode = kThumbLdrbRRR;
+ opcode = kThumbLdrbRRR;
}
break;
case kSignedByte:
- opCode = kThumbLdrsbRRR;
+ opcode = kThumbLdrsbRRR;
break;
default:
LOGE("Jit: bad case in loadBaseIndexedBody");
dvmCompilerAbort(cUnit);
}
if (shortForm) {
- load = res = newLIR3(cUnit, opCode, rDest, rBase, encodedDisp);
+ load = res = newLIR3(cUnit, opcode, rDest, rBase, encodedDisp);
if (pair) {
- load2 = newLIR3(cUnit, opCode, rDestHi, rBase, encodedDisp+1);
+ load2 = newLIR3(cUnit, opcode, rDestHi, rBase, encodedDisp+1);
}
} else {
if (pair) {
int rTmp = (rBase == rDest) ? dvmCompilerAllocFreeTemp(cUnit)
: rDest;
res = loadConstant(cUnit, rTmp, displacement);
- load = newLIR3(cUnit, opCode, rDest, rBase, rTmp);
+ load = newLIR3(cUnit, opcode, rDest, rBase, rTmp);
if (rBase == rFP)
annotateDalvikRegAccess(load, displacement >> 2,
true /* isLoad */);
ArmLIR *res;
ArmLIR *store = NULL;
ArmLIR *store2 = NULL;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
int encodedDisp = displacement;
bool pair = false;
pair = true;
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbStrRRI5;
+ opcode = kThumbStrRRI5;
} else {
- opCode = kThumbStrRRR;
+ opcode = kThumbStrRRR;
}
break;
case kWord:
assert((displacement & 0x3) == 0);
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbStrRRI5;
+ opcode = kThumbStrRRI5;
} else {
- opCode = kThumbStrRRR;
+ opcode = kThumbStrRRR;
}
break;
case kUnsignedHalf:
assert((displacement & 0x1) == 0);
shortForm = true;
encodedDisp >>= 1;
- opCode = kThumbStrhRRI5;
+ opcode = kThumbStrhRRI5;
} else {
- opCode = kThumbStrhRRR;
+ opcode = kThumbStrhRRR;
}
break;
case kUnsignedByte:
case kSignedByte:
if (displacement < 32 && displacement >= 0) {
shortForm = true;
- opCode = kThumbStrbRRI5;
+ opcode = kThumbStrbRRI5;
} else {
- opCode = kThumbStrbRRR;
+ opcode = kThumbStrbRRR;
}
break;
default:
dvmCompilerAbort(cUnit);
}
if (shortForm) {
- store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp);
+ store = res = newLIR3(cUnit, opcode, rSrc, rBase, encodedDisp);
if (pair) {
- store2 = newLIR3(cUnit, opCode, rSrcHi, rBase, encodedDisp + 1);
+ store2 = newLIR3(cUnit, opcode, rSrcHi, rBase, encodedDisp + 1);
}
} else {
int rScratch = dvmCompilerAllocTemp(cUnit);
store2 = newLIR3(cUnit, kThumbStrRRI5, rSrcHi, rScratch, 1);
} else {
res = loadConstant(cUnit, rScratch, displacement);
- store = newLIR3(cUnit, opCode, rSrc, rBase, rScratch);
+ store = newLIR3(cUnit, opcode, rSrc, rBase, rScratch);
}
dvmCompilerFreeTemp(cUnit, rScratch);
}
static ArmLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
ArmLIR* res;
- ArmOpCode opCode;
+ ArmOpcode opcode;
res = dvmCompilerNew(sizeof(ArmLIR), true);
if (LOWREG(rDest) && LOWREG(rSrc))
- opCode = kThumbMovRR;
+ opcode = kThumbMovRR;
else if (!LOWREG(rDest) && !LOWREG(rSrc))
- opCode = kThumbMovRR_H2H;
+ opcode = kThumbMovRR_H2H;
else if (LOWREG(rDest))
- opCode = kThumbMovRR_H2L;
+ opcode = kThumbMovRR_H2L;
else
- opCode = kThumbMovRR_L2H;
+ opcode = kThumbMovRR_L2H;
res->operands[0] = rDest;
res->operands[1] = rSrc;
- res->opCode = opCode;
+ res->opcode = opcode;
setupResourceMasks(res);
if (rDest == rSrc) {
res->isNop = true;
dataTarget = addWordData(cUnit, value, false);
}
ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true);
- loadPcRel->opCode = kThumb2Vldrs;
+ loadPcRel->opcode = kThumb2Vldrs;
loadPcRel->generic.target = (LIR *) dataTarget;
loadPcRel->operands[0] = rDest;
loadPcRel->operands[1] = rpc;
dataTarget = addWordData(cUnit, value, false);
}
ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true);
- loadPcRel->opCode = kThumb2LdrPcRel12;
+ loadPcRel->opcode = kThumb2LdrPcRel12;
loadPcRel->generic.target = (LIR *) dataTarget;
loadPcRel->operands[0] = rDest;
setupResourceMasks(loadPcRel);
static ArmLIR *opNone(CompilationUnit *cUnit, OpKind op)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpUncondBr:
- opCode = kThumbBUncond;
+ opcode = kThumbBUncond;
break;
default:
assert(0);
}
- return newLIR0(cUnit, opCode);
+ return newLIR0(cUnit, opcode);
}
static ArmLIR *opCondBranch(CompilationUnit *cUnit, ArmConditionCode cc)
static ArmLIR *opImm(CompilationUnit *cUnit, OpKind op, int value)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpPush:
- opCode = ((value & 0xff00) != 0) ? kThumb2Push : kThumbPush;
+ opcode = ((value & 0xff00) != 0) ? kThumb2Push : kThumbPush;
break;
case kOpPop:
- opCode = ((value & 0xff00) != 0) ? kThumb2Pop : kThumbPop;
+ opcode = ((value & 0xff00) != 0) ? kThumb2Pop : kThumbPop;
break;
default:
assert(0);
}
- return newLIR1(cUnit, opCode, value);
+ return newLIR1(cUnit, opcode, value);
}
static ArmLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpBlx:
- opCode = kThumbBlxR;
+ opcode = kThumbBlxR;
break;
default:
assert(0);
}
- return newLIR1(cUnit, opCode, rDestSrc);
+ return newLIR1(cUnit, opcode, rDestSrc);
}
static ArmLIR *opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
int rSrc2, int shift)
{
bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2));
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdc:
- opCode = (thumbForm) ? kThumbAdcRR : kThumb2AdcRRR;
+ opcode = (thumbForm) ? kThumbAdcRR : kThumb2AdcRRR;
break;
case kOpAnd:
- opCode = (thumbForm) ? kThumbAndRR : kThumb2AndRRR;
+ opcode = (thumbForm) ? kThumbAndRR : kThumb2AndRRR;
break;
case kOpBic:
- opCode = (thumbForm) ? kThumbBicRR : kThumb2BicRRR;
+ opcode = (thumbForm) ? kThumbBicRR : kThumb2BicRRR;
break;
case kOpCmn:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbCmnRR : kThumb2CmnRR;
+ opcode = (thumbForm) ? kThumbCmnRR : kThumb2CmnRR;
break;
case kOpCmp:
if (thumbForm)
- opCode = kThumbCmpRR;
+ opcode = kThumbCmpRR;
else if ((shift == 0) && !LOWREG(rDestSrc1) && !LOWREG(rSrc2))
- opCode = kThumbCmpHH;
+ opcode = kThumbCmpHH;
else if ((shift == 0) && LOWREG(rDestSrc1))
- opCode = kThumbCmpLH;
+ opcode = kThumbCmpLH;
else if (shift == 0)
- opCode = kThumbCmpHL;
+ opcode = kThumbCmpHL;
else
- opCode = kThumb2CmpRR;
+ opcode = kThumb2CmpRR;
break;
case kOpXor:
- opCode = (thumbForm) ? kThumbEorRR : kThumb2EorRRR;
+ opcode = (thumbForm) ? kThumbEorRR : kThumb2EorRRR;
break;
case kOpMov:
assert(shift == 0);
if (LOWREG(rDestSrc1) && LOWREG(rSrc2))
- opCode = kThumbMovRR;
+ opcode = kThumbMovRR;
else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2))
- opCode = kThumbMovRR_H2H;
+ opcode = kThumbMovRR_H2H;
else if (LOWREG(rDestSrc1))
- opCode = kThumbMovRR_H2L;
+ opcode = kThumbMovRR_H2L;
else
- opCode = kThumbMovRR_L2H;
+ opcode = kThumbMovRR_L2H;
break;
case kOpMul:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbMul : kThumb2MulRRR;
+ opcode = (thumbForm) ? kThumbMul : kThumb2MulRRR;
break;
case kOpMvn:
- opCode = (thumbForm) ? kThumbMvn : kThumb2MnvRR;
+ opcode = (thumbForm) ? kThumbMvn : kThumb2MnvRR;
break;
case kOpNeg:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbNeg : kThumb2NegRR;
+ opcode = (thumbForm) ? kThumbNeg : kThumb2NegRR;
break;
case kOpOr:
- opCode = (thumbForm) ? kThumbOrr : kThumb2OrrRRR;
+ opcode = (thumbForm) ? kThumbOrr : kThumb2OrrRRR;
break;
case kOpSbc:
- opCode = (thumbForm) ? kThumbSbc : kThumb2SbcRRR;
+ opcode = (thumbForm) ? kThumbSbc : kThumb2SbcRRR;
break;
case kOpTst:
- opCode = (thumbForm) ? kThumbTst : kThumb2TstRR;
+ opcode = (thumbForm) ? kThumbTst : kThumb2TstRR;
break;
case kOpLsl:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbLslRR : kThumb2LslRRR;
+ opcode = (thumbForm) ? kThumbLslRR : kThumb2LslRRR;
break;
case kOpLsr:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbLsrRR : kThumb2LsrRRR;
+ opcode = (thumbForm) ? kThumbLsrRR : kThumb2LsrRRR;
break;
case kOpAsr:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbAsrRR : kThumb2AsrRRR;
+ opcode = (thumbForm) ? kThumbAsrRR : kThumb2AsrRRR;
break;
case kOpRor:
assert(shift == 0);
- opCode = (thumbForm) ? kThumbRorRR : kThumb2RorRRR;
+ opcode = (thumbForm) ? kThumbRorRR : kThumb2RorRRR;
break;
case kOpAdd:
- opCode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
+ opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
break;
case kOpSub:
- opCode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR;
+ opcode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR;
break;
case kOp2Byte:
assert(shift == 0);
assert(0);
break;
}
- assert(opCode >= 0);
- if (EncodingMap[opCode].flags & IS_BINARY_OP)
- return newLIR2(cUnit, opCode, rDestSrc1, rSrc2);
- else if (EncodingMap[opCode].flags & IS_TERTIARY_OP) {
- if (EncodingMap[opCode].fieldLoc[2].kind == kFmtShift)
- return newLIR3(cUnit, opCode, rDestSrc1, rSrc2, shift);
+ assert(opcode >= 0);
+ if (EncodingMap[opcode].flags & IS_BINARY_OP)
+ return newLIR2(cUnit, opcode, rDestSrc1, rSrc2);
+ else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) {
+ if (EncodingMap[opcode].fieldLoc[2].kind == kFmtShift)
+ return newLIR3(cUnit, opcode, rDestSrc1, rSrc2, shift);
else
- return newLIR3(cUnit, opCode, rDestSrc1, rDestSrc1, rSrc2);
- } else if (EncodingMap[opCode].flags & IS_QUAD_OP)
- return newLIR4(cUnit, opCode, rDestSrc1, rDestSrc1, rSrc2, shift);
+ return newLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rSrc2);
+ } else if (EncodingMap[opcode].flags & IS_QUAD_OP)
+ return newLIR4(cUnit, opcode, rDestSrc1, rDestSrc1, rSrc2, shift);
else {
assert(0);
return NULL;
static ArmLIR *opRegRegRegShift(CompilationUnit *cUnit, OpKind op,
int rDest, int rSrc1, int rSrc2, int shift)
{
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (shift == 0) && LOWREG(rDest) && LOWREG(rSrc1) &&
LOWREG(rSrc2);
switch (op) {
case kOpAdd:
- opCode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
+ opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
break;
case kOpSub:
- opCode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR;
+ opcode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR;
break;
case kOpAdc:
- opCode = kThumb2AdcRRR;
+ opcode = kThumb2AdcRRR;
break;
case kOpAnd:
- opCode = kThumb2AndRRR;
+ opcode = kThumb2AndRRR;
break;
case kOpBic:
- opCode = kThumb2BicRRR;
+ opcode = kThumb2BicRRR;
break;
case kOpXor:
- opCode = kThumb2EorRRR;
+ opcode = kThumb2EorRRR;
break;
case kOpMul:
assert(shift == 0);
- opCode = kThumb2MulRRR;
+ opcode = kThumb2MulRRR;
break;
case kOpOr:
- opCode = kThumb2OrrRRR;
+ opcode = kThumb2OrrRRR;
break;
case kOpSbc:
- opCode = kThumb2SbcRRR;
+ opcode = kThumb2SbcRRR;
break;
case kOpLsl:
assert(shift == 0);
- opCode = kThumb2LslRRR;
+ opcode = kThumb2LslRRR;
break;
case kOpLsr:
assert(shift == 0);
- opCode = kThumb2LsrRRR;
+ opcode = kThumb2LsrRRR;
break;
case kOpAsr:
assert(shift == 0);
- opCode = kThumb2AsrRRR;
+ opcode = kThumb2AsrRRR;
break;
case kOpRor:
assert(shift == 0);
- opCode = kThumb2RorRRR;
+ opcode = kThumb2RorRRR;
break;
default:
assert(0);
break;
}
- assert(opCode >= 0);
- if (EncodingMap[opCode].flags & IS_QUAD_OP)
- return newLIR4(cUnit, opCode, rDest, rSrc1, rSrc2, shift);
+ assert(opcode >= 0);
+ if (EncodingMap[opcode].flags & IS_QUAD_OP)
+ return newLIR4(cUnit, opcode, rDest, rSrc1, rSrc2, shift);
else {
- assert(EncodingMap[opCode].flags & IS_TERTIARY_OP);
- return newLIR3(cUnit, opCode, rDest, rSrc1, rSrc2);
+ assert(EncodingMap[opcode].flags & IS_TERTIARY_OP);
+ return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
}
}
ArmLIR *res;
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
- ArmOpCode opCode = kThumbBkpt;
- ArmOpCode altOpCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
+ ArmOpcode altOpcode = kThumbBkpt;
bool allLowRegs = (LOWREG(rDest) && LOWREG(rSrc1));
int modImm = modifiedImmediate(value);
int modImmNeg = modifiedImmediate(-value);
return newLIR3(cUnit, kThumbAddPcRel, rDest, rSrc1,
value >> 2);
}
- opCode = kThumb2AddRRI8;
- altOpCode = kThumb2AddRRR;
+ opcode = kThumb2AddRRI8;
+ altOpcode = kThumb2AddRRR;
// Note: intentional fallthrough
case kOpSub:
if (allLowRegs && ((absValue & 0x7) == absValue)) {
if (op == kOpAdd)
- opCode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3;
+ opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3;
else
- opCode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3;
- return newLIR3(cUnit, opCode, rDest, rSrc1, absValue);
+ opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3;
+ return newLIR3(cUnit, opcode, rDest, rSrc1, absValue);
} else if ((absValue & 0xff) == absValue) {
if (op == kOpAdd)
- opCode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12;
+ opcode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12;
else
- opCode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12;
- return newLIR3(cUnit, opCode, rDest, rSrc1, absValue);
+ opcode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12;
+ return newLIR3(cUnit, opcode, rDest, rSrc1, absValue);
}
if (modImmNeg >= 0) {
op = (op == kOpAdd) ? kOpSub : kOpAdd;
modImm = modImmNeg;
}
if (op == kOpSub) {
- opCode = kThumb2SubRRI8;
- altOpCode = kThumb2SubRRR;
+ opcode = kThumb2SubRRI8;
+ altOpcode = kThumb2SubRRR;
}
break;
case kOpAdc:
- opCode = kThumb2AdcRRI8;
- altOpCode = kThumb2AdcRRR;
+ opcode = kThumb2AdcRRI8;
+ altOpcode = kThumb2AdcRRR;
break;
case kOpSbc:
- opCode = kThumb2SbcRRI8;
- altOpCode = kThumb2SbcRRR;
+ opcode = kThumb2SbcRRI8;
+ altOpcode = kThumb2SbcRRR;
break;
case kOpOr:
- opCode = kThumb2OrrRRI8;
- altOpCode = kThumb2OrrRRR;
+ opcode = kThumb2OrrRRI8;
+ altOpcode = kThumb2OrrRRR;
break;
case kOpAnd:
- opCode = kThumb2AndRRI8;
- altOpCode = kThumb2AndRRR;
+ opcode = kThumb2AndRRI8;
+ altOpcode = kThumb2AndRRR;
break;
case kOpXor:
- opCode = kThumb2EorRRI8;
- altOpCode = kThumb2EorRRR;
+ opcode = kThumb2EorRRI8;
+ altOpcode = kThumb2EorRRR;
break;
case kOpMul:
//TUNING: power of 2, shift & add
modImm = -1;
- altOpCode = kThumb2MulRRR;
+ altOpcode = kThumb2MulRRR;
break;
case kOpCmp: {
int modImm = modifiedImmediate(value);
}
if (modImm >= 0) {
- return newLIR3(cUnit, opCode, rDest, rSrc1, modImm);
+ return newLIR3(cUnit, opcode, rDest, rSrc1, modImm);
} else {
int rScratch = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, rScratch, value);
- if (EncodingMap[altOpCode].flags & IS_QUAD_OP)
- res = newLIR4(cUnit, altOpCode, rDest, rSrc1, rScratch, 0);
+ if (EncodingMap[altOpcode].flags & IS_QUAD_OP)
+ res = newLIR4(cUnit, altOpcode, rDest, rSrc1, rScratch, 0);
else
- res = newLIR3(cUnit, altOpCode, rDest, rSrc1, rScratch);
+ res = newLIR3(cUnit, altOpcode, rDest, rSrc1, rScratch);
dvmCompilerFreeTemp(cUnit, rScratch);
return res;
}
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
bool shortForm = (((absValue & 0xff) == absValue) && LOWREG(rDestSrc1));
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
if ( !neg && (rDestSrc1 == 13) && (value <= 508)) { /* sp */
assert((value & 0x3) == 0);
return newLIR1(cUnit, kThumbAddSpI7, value >> 2);
} else if (shortForm) {
- opCode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
+ opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
}
break;
case kOpSub:
assert((value & 0x3) == 0);
return newLIR1(cUnit, kThumbSubSpI7, value >> 2);
} else if (shortForm) {
- opCode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
+ opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
}
break;
case kOpCmp:
if (LOWREG(rDestSrc1) && shortForm)
- opCode = (shortForm) ? kThumbCmpRI8 : kThumbCmpRR;
+ opcode = (shortForm) ? kThumbCmpRI8 : kThumbCmpRR;
else if (LOWREG(rDestSrc1))
- opCode = kThumbCmpRR;
+ opcode = kThumbCmpRR;
else {
shortForm = false;
- opCode = kThumbCmpHL;
+ opcode = kThumbCmpHL;
}
break;
default:
break;
}
if (shortForm)
- return newLIR2(cUnit, opCode, rDestSrc1, absValue);
+ return newLIR2(cUnit, opcode, rDestSrc1, absValue);
else {
return opRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value);
}
{
bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
ArmLIR *load;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (allLowRegs && (scale == 0));
int regPtr;
if (FPREG(rDest)) {
assert(SINGLEREG(rDest));
assert((size == kWord) || (size == kSingle));
- opCode = kThumb2Vldrs;
+ opcode = kThumb2Vldrs;
size = kSingle;
} else {
if (size == kSingle)
} else {
opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
}
- load = newLIR3(cUnit, opCode, rDest, regPtr, 0);
+ load = newLIR3(cUnit, opcode, rDest, regPtr, 0);
#if defined(WITH_SELF_VERIFICATION)
if (cUnit->heapMemOp)
load->branchInsertSV = true;
#endif
return load;
case kWord:
- opCode = (thumbForm) ? kThumbLdrRRR : kThumb2LdrRRR;
+ opcode = (thumbForm) ? kThumbLdrRRR : kThumb2LdrRRR;
break;
case kUnsignedHalf:
- opCode = (thumbForm) ? kThumbLdrhRRR : kThumb2LdrhRRR;
+ opcode = (thumbForm) ? kThumbLdrhRRR : kThumb2LdrhRRR;
break;
case kSignedHalf:
- opCode = (thumbForm) ? kThumbLdrshRRR : kThumb2LdrshRRR;
+ opcode = (thumbForm) ? kThumbLdrshRRR : kThumb2LdrshRRR;
break;
case kUnsignedByte:
- opCode = (thumbForm) ? kThumbLdrbRRR : kThumb2LdrbRRR;
+ opcode = (thumbForm) ? kThumbLdrbRRR : kThumb2LdrbRRR;
break;
case kSignedByte:
- opCode = (thumbForm) ? kThumbLdrsbRRR : kThumb2LdrsbRRR;
+ opcode = (thumbForm) ? kThumbLdrsbRRR : kThumb2LdrsbRRR;
break;
default:
assert(0);
}
if (thumbForm)
- load = newLIR3(cUnit, opCode, rDest, rBase, rIndex);
+ load = newLIR3(cUnit, opcode, rDest, rBase, rIndex);
else
- load = newLIR4(cUnit, opCode, rDest, rBase, rIndex, scale);
+ load = newLIR4(cUnit, opcode, rDest, rBase, rIndex, scale);
#if defined(WITH_SELF_VERIFICATION)
if (cUnit->heapMemOp)
{
bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
ArmLIR *store;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (allLowRegs && (scale == 0));
int regPtr;
if (FPREG(rSrc)) {
assert(SINGLEREG(rSrc));
assert((size == kWord) || (size == kSingle));
- opCode = kThumb2Vstrs;
+ opcode = kThumb2Vstrs;
size = kSingle;
} else {
if (size == kSingle)
} else {
opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
}
- store = newLIR3(cUnit, opCode, rSrc, regPtr, 0);
+ store = newLIR3(cUnit, opcode, rSrc, regPtr, 0);
#if defined(WITH_SELF_VERIFICATION)
if (cUnit->heapMemOp)
store->branchInsertSV = true;
#endif
return store;
case kWord:
- opCode = (thumbForm) ? kThumbStrRRR : kThumb2StrRRR;
+ opcode = (thumbForm) ? kThumbStrRRR : kThumb2StrRRR;
break;
case kUnsignedHalf:
case kSignedHalf:
- opCode = (thumbForm) ? kThumbStrhRRR : kThumb2StrhRRR;
+ opcode = (thumbForm) ? kThumbStrhRRR : kThumb2StrhRRR;
break;
case kUnsignedByte:
case kSignedByte:
- opCode = (thumbForm) ? kThumbStrbRRR : kThumb2StrbRRR;
+ opcode = (thumbForm) ? kThumbStrbRRR : kThumb2StrbRRR;
break;
default:
assert(0);
}
if (thumbForm)
- store = newLIR3(cUnit, opCode, rSrc, rBase, rIndex);
+ store = newLIR3(cUnit, opcode, rSrc, rBase, rIndex);
else
- store = newLIR4(cUnit, opCode, rSrc, rBase, rIndex, scale);
+ store = newLIR4(cUnit, opcode, rSrc, rBase, rIndex, scale);
#if defined(WITH_SELF_VERIFICATION)
if (cUnit->heapMemOp)
OpSize size, int sReg)
{
ArmLIR *res, *load;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
bool allLowRegs = (LOWREG(rBase) && LOWREG(rDest));
assert(FPREG(rDestHi));
rDest = S2D(rDest, rDestHi);
}
- opCode = kThumb2Vldrd;
+ opcode = kThumb2Vldrd;
if (displacement <= 1020) {
shortForm = true;
encodedDisp >>= 2;
case kSingle:
case kWord:
if (FPREG(rDest)) {
- opCode = kThumb2Vldrs;
+ opcode = kThumb2Vldrs;
if (displacement <= 1020) {
shortForm = true;
encodedDisp >>= 2;
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrPcRel;
+ opcode = kThumbLdrPcRel;
} else if (LOWREG(rDest) && (rBase == r13) &&
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrSpRel;
+ opcode = kThumbLdrSpRel;
} else if (allLowRegs && displacement < 128 && displacement >= 0) {
assert((displacement & 0x3) == 0);
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbLdrRRI5;
+ opcode = kThumbLdrRRI5;
} else if (thumb2Form) {
shortForm = true;
- opCode = kThumb2LdrRRI12;
+ opcode = kThumb2LdrRRI12;
}
break;
case kUnsignedHalf:
assert((displacement & 0x1) == 0);
shortForm = true;
encodedDisp >>= 1;
- opCode = kThumbLdrhRRI5;
+ opcode = kThumbLdrhRRI5;
} else if (displacement < 4092 && displacement >= 0) {
shortForm = true;
- opCode = kThumb2LdrhRRI12;
+ opcode = kThumb2LdrhRRI12;
}
break;
case kSignedHalf:
if (thumb2Form) {
shortForm = true;
- opCode = kThumb2LdrshRRI12;
+ opcode = kThumb2LdrshRRI12;
}
break;
case kUnsignedByte:
if (allLowRegs && displacement < 32 && displacement >= 0) {
shortForm = true;
- opCode = kThumbLdrbRRI5;
+ opcode = kThumbLdrbRRI5;
} else if (thumb2Form) {
shortForm = true;
- opCode = kThumb2LdrbRRI12;
+ opcode = kThumb2LdrbRRI12;
}
break;
case kSignedByte:
if (thumb2Form) {
shortForm = true;
- opCode = kThumb2LdrsbRRI12;
+ opcode = kThumb2LdrsbRRI12;
}
break;
default:
}
if (shortForm) {
- load = res = newLIR3(cUnit, opCode, rDest, rBase, encodedDisp);
+ load = res = newLIR3(cUnit, opcode, rDest, rBase, encodedDisp);
} else {
int regOffset = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, regOffset, encodedDisp);
OpSize size)
{
ArmLIR *res, *store;
- ArmOpCode opCode = kThumbBkpt;
+ ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
assert(FPREG(rSrcHi));
rSrc = S2D(rSrc, rSrcHi);
}
- opCode = kThumb2Vstrd;
+ opcode = kThumb2Vstrd;
if (displacement <= 1020) {
shortForm = true;
encodedDisp >>= 2;
case kWord:
if (FPREG(rSrc)) {
assert(SINGLEREG(rSrc));
- opCode = kThumb2Vstrs;
+ opcode = kThumb2Vstrs;
if (displacement <= 1020) {
shortForm = true;
encodedDisp >>= 2;
assert((displacement & 0x3) == 0);
shortForm = true;
encodedDisp >>= 2;
- opCode = kThumbStrRRI5;
+ opcode = kThumbStrRRI5;
} else if (thumb2Form) {
shortForm = true;
- opCode = kThumb2StrRRI12;
+ opcode = kThumb2StrRRI12;
}
break;
case kUnsignedHalf:
assert((displacement & 0x1) == 0);
shortForm = true;
encodedDisp >>= 1;
- opCode = kThumbStrhRRI5;
+ opcode = kThumbStrhRRI5;
} else if (thumb2Form) {
shortForm = true;
- opCode = kThumb2StrhRRI12;
+ opcode = kThumb2StrhRRI12;
}
break;
case kUnsignedByte:
case kSignedByte:
if (allLowRegs && displacement < 32 && displacement >= 0) {
shortForm = true;
- opCode = kThumbStrbRRI5;
+ opcode = kThumbStrbRRI5;
} else if (thumb2Form) {
shortForm = true;
- opCode = kThumb2StrbRRI12;
+ opcode = kThumb2StrbRRI12;
}
break;
default:
assert(0);
}
if (shortForm) {
- store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp);
+ store = res = newLIR3(cUnit, opcode, rSrc, rBase, encodedDisp);
} else {
int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, encodedDisp);
} else {
assert(DOUBLEREG(rDest) == DOUBLEREG(rSrc));
if (DOUBLEREG(rDest)) {
- res->opCode = kThumb2Vmovd;
+ res->opcode = kThumb2Vmovd;
} else {
if (SINGLEREG(rDest)) {
- res->opCode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
+ res->opcode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
} else {
assert(SINGLEREG(rSrc));
- res->opCode = kThumb2Fmrs;
+ res->opcode = kThumb2Fmrs;
}
}
res->operands[0] = rDest;
static ArmLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
ArmLIR* res;
- ArmOpCode opCode;
+ ArmOpcode opcode;
if (FPREG(rDest) || FPREG(rSrc))
return fpRegCopy(cUnit, rDest, rSrc);
res = dvmCompilerNew(sizeof(ArmLIR), true);
if (LOWREG(rDest) && LOWREG(rSrc))
- opCode = kThumbMovRR;
+ opcode = kThumbMovRR;
else if (!LOWREG(rDest) && !LOWREG(rSrc))
- opCode = kThumbMovRR_H2H;
+ opcode = kThumbMovRR_H2H;
else if (LOWREG(rDest))
- opCode = kThumbMovRR_H2L;
+ opcode = kThumbMovRR_H2L;
else
- opCode = kThumbMovRR_L2H;
+ opcode = kThumbMovRR_L2H;
res->operands[0] = rDest;
res->operands[1] = rSrc;
- res->opCode = opCode;
+ res->opcode = opcode;
setupResourceMasks(res);
if (rDest == rSrc) {
res->isNop = true;
static void genMonitor(CompilationUnit *cUnit, MIR *mir)
{
- if (mir->dalvikInsn.opCode == OP_MONITOR_ENTER)
+ if (mir->dalvikInsn.opcode == OP_MONITOR_ENTER)
genMonitorEnter(cUnit, mir);
else
genMonitorExit(cUnit, mir);
* ...
*/
TEMPLATE_LAST_MARK,
-} TemplateOpCode;
+} TemplateOpcode;
#undef JIT_TEMPLATE
#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */
* ...
*/
TEMPLATE_LAST_MARK,
-} TemplateOpCode;
+} TemplateOpcode;
#undef JIT_TEMPLATE
#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_ARCHVARIANT_H */
* ...
*/
TEMPLATE_LAST_MARK,
-} TemplateOpCode;
+} TemplateOpcode;
#undef JIT_TEMPLATE
#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */
* ...
*/
TEMPLATE_LAST_MARK,
-} TemplateOpCode;
+} TemplateOpcode;
#undef JIT_TEMPLATE
#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */
typedef struct X86LIR {
LIR generic;
- //X86OpCode opCode;
+ //X86Opcode opcode;
int operands[4]; // [0..3] = [dest, src1, src2, extra]
bool isNop; // LIR is optimized away
bool branchInsertSV;// mark for insertion of branch before this instruction,
* ...
*/
TEMPLATE_LAST_MARK,
-} TemplateOpCode;
+} TemplateOpcode;
#undef JIT_TEMPLATE
#endif /* _DALVIK_VM_COMPILER_CODEGEN_X86_IA32_ARCHVARIANT_H */
# with overflow here.
outfp.write(" .balign 4\n")
# Emit a label so that gdb will say the right thing. We prepend an
- # underscore so the symbol name doesn't clash with the OpCode enum.
+ # underscore so the symbol name doesn't clash with the Opcode enum.
template_name = "dvmCompiler_%(opcode)s" % dict
outfp.write(" .global %s\n" % template_name);
outfp.write("%s:\n" % template_name);
typedef struct {
Method* method; /* method we're associated with */
u2* addr; /* absolute memory address */
- u1 originalOpCode; /* original 8-bit opcode value */
+ u1 originalOpcode; /* original 8-bit opcode value */
int setCount; /* #of times this breakpoint was set */
} Breakpoint;
*
* Returns "true" with the opcode in *pOrig on success.
*/
-static bool dvmBreakpointSetOriginalOpCode(const BreakpointSet* pSet,
+static bool dvmBreakpointSetOriginalOpcode(const BreakpointSet* pSet,
const u2* addr, u1* pOrig)
{
int idx = dvmBreakpointSetFind(pSet, addr);
if (idx < 0)
return false;
- *pOrig = pSet->breakpoints[idx].originalOpCode;
+ *pOrig = pSet->breakpoints[idx].originalOpcode;
return true;
}
pBreak = &pSet->breakpoints[pSet->count++];
pBreak->method = method;
pBreak->addr = (u2*)addr;
- pBreak->originalOpCode = *(u1*)addr;
+ pBreak->originalOpcode = *(u1*)addr;
pBreak->setCount = 1;
/*
* need to. (Not worth worrying about.)
*/
dvmDexChangeDex1(method->clazz->pDvmDex, (u1*)addr,
- pBreak->originalOpCode);
+ pBreak->originalOpcode);
ANDROID_MEMBAR_FULL();
if (idx != pSet->count-1) {
* the restoration of the original opcode. The fact that we're holding
* the lock prevents other threads from confusing things further.)
*/
-u1 dvmGetOriginalOpCode(const u2* addr)
+u1 dvmGetOriginalOpcode(const u2* addr)
{
BreakpointSet* pSet = gDvm.breakpointSet;
u1 orig = 0;
dvmBreakpointSetLock(pSet);
- if (!dvmBreakpointSetOriginalOpCode(pSet, addr, &orig)) {
+ if (!dvmBreakpointSetOriginalOpcode(pSet, addr, &orig)) {
orig = *(u1*)addr;
if (orig == OP_BREAKPOINT) {
LOGE("GLITCH: can't find breakpoint, opcode is still set\n");
/*
* Recover the opcode that was replaced by a breakpoint.
*/
-u1 dvmGetOriginalOpCode(const u2* addr);
+u1 dvmGetOriginalOpcode(const u2* addr);
/*
* Flush any breakpoints associated with methods in "clazz".
decInsn = &(shadowSpace->trace[i].decInsn);
/* Not properly decoding instruction, some registers may be garbage */
LOGD("0x%x: (0x%04x) %s",
- addr, offset, dexGetOpcodeName(decInsn->opCode));
+ addr, offset, dexGetOpcodeName(decInsn->opcode));
}
}
//LOGD("### DbgIntp(%d): PC: 0x%x endPC: 0x%x state: %d len: %d %s",
// self->threadId, (int)pc, (int)shadowSpace->endPC, state,
- // shadowSpace->traceLength, dexGetOpcodeName(decInsn.opCode));
+ // shadowSpace->traceLength, dexGetOpcodeName(decInsn.opcode));
if (state == kSVSIdle || state == kSVSStart) {
LOGD("~~~ DbgIntrp: INCORRECT PREVIOUS STATE(%d): %d",
const u2 *moveResultPC = lastPC + len;
dexDecodeInstruction(moveResultPC, &nextDecInsn);
- if ((nextDecInsn.opCode != OP_MOVE_RESULT) &&
- (nextDecInsn.opCode != OP_MOVE_RESULT_WIDE) &&
- (nextDecInsn.opCode != OP_MOVE_RESULT_OBJECT))
+ if ((nextDecInsn.opcode != OP_MOVE_RESULT) &&
+ (nextDecInsn.opcode != OP_MOVE_RESULT_WIDE) &&
+ (nextDecInsn.opcode != OP_MOVE_RESULT_OBJECT))
return;
/* We need to start a new trace run */
* cells.
*/
if (interpState->totalTraceLen != 0 &&
- (decInsn.opCode == OP_PACKED_SWITCH ||
- decInsn.opCode == OP_SPARSE_SWITCH)) {
+ (decInsn.opcode == OP_PACKED_SWITCH ||
+ decInsn.opcode == OP_SPARSE_SWITCH)) {
interpState->jitState = kJitTSelectEnd;
break;
}
#if defined(SHOW_TRACE)
- LOGD("TraceGen: adding %s", dexGetOpcodeName(decInsn.opCode));
+ LOGD("TraceGen: adding %s", dexGetOpcodeName(decInsn.opcode));
#endif
- flags = dexGetInstrFlags(decInsn.opCode);
+ flags = dexGetInstrFlags(decInsn.opcode);
len = dexGetInstrOrTableWidth(lastPC);
offset = lastPC - interpState->method->insns;
assert((unsigned) offset <
interpState->jitState = kJitTSelectEnd;
#if defined(SHOW_TRACE)
LOGD("TraceGen: ending on %s, basic block end",
- dexGetOpcodeName(decInsn.opCode));
+ dexGetOpcodeName(decInsn.opcode));
#endif
/*
}
}
/* Break on throw or self-loop */
- if ((decInsn.opCode == OP_THROW) || (lastPC == pc)){
+ if ((decInsn.opcode == OP_THROW) || (lastPC == pc)){
interpState->jitState = kJitTSelectEnd;
}
if (interpState->totalTraceLen >= JIT_MAX_TRACE_LEN) {
* instruction (which is already included in the trace
* containing the invoke.
*/
- if (decInsn.opCode != OP_RETURN_VOID) {
+ if (decInsn.opcode != OP_RETURN_VOID) {
stayOneMoreInst = true;
}
}
* time we get here, the breakpoint has already been handled and
* the thread resumed.
*/
- u1 originalOpCode = dvmGetOriginalOpCode(pc);
- LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpCode, inst,
- INST_REPLACE_OP(inst, originalOpCode));
- inst = INST_REPLACE_OP(inst, originalOpCode);
- FINISH_BKPT(originalOpCode);
+ u1 originalOpcode = dvmGetOriginalOpcode(pc);
+ LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpcode, inst,
+ INST_REPLACE_OP(inst, originalOpcode));
+ inst = INST_REPLACE_OP(inst, originalOpcode);
+ FINISH_BKPT(originalOpcode);
}
#else
LOGE("Breakpoint hit in non-debug interpreter\n");
# with overflow here.
outfp.write(" .balign %d\n" % handler_size_bytes)
# Emit a label so that gdb will say the right thing. We prepend an
- # underscore so the symbol name doesn't clash with the OpCode enum.
+ # underscore so the symbol name doesn't clash with the Opcode enum.
outfp.write(label_prefix + "_%(opcode)s: /* 0x%(opnum)02x */\n" % dict)
#
* time we get here, the breakpoint has already been handled and
* the thread resumed.
*/
- u1 originalOpCode = dvmGetOriginalOpCode(pc);
- LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpCode, inst,
- INST_REPLACE_OP(inst, originalOpCode));
- inst = INST_REPLACE_OP(inst, originalOpCode);
- FINISH_BKPT(originalOpCode);
+ u1 originalOpcode = dvmGetOriginalOpcode(pc);
+ LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpcode, inst,
+ INST_REPLACE_OP(inst, originalOpcode));
+ inst = INST_REPLACE_OP(inst, originalOpcode);
+ FINISH_BKPT(originalOpcode);
}
#else
LOGE("Breakpoint hit in non-debug interpreter\n");
* time we get here, the breakpoint has already been handled and
* the thread resumed.
*/
- u1 originalOpCode = dvmGetOriginalOpCode(pc);
- LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpCode, inst,
- INST_REPLACE_OP(inst, originalOpCode));
- inst = INST_REPLACE_OP(inst, originalOpCode);
- FINISH_BKPT(originalOpCode);
+ u1 originalOpcode = dvmGetOriginalOpcode(pc);
+ LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpcode, inst,
+ INST_REPLACE_OP(inst, originalOpcode));
+ inst = INST_REPLACE_OP(inst, originalOpcode);
+ FINISH_BKPT(originalOpcode);
}
#else
LOGE("Breakpoint hit in non-debug interpreter\n");
* time we get here, the breakpoint has already been handled and
* the thread resumed.
*/
- u1 originalOpCode = dvmGetOriginalOpCode(pc);
- LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpCode, inst,
- INST_REPLACE_OP(inst, originalOpCode));
- inst = INST_REPLACE_OP(inst, originalOpCode);
- FINISH_BKPT(originalOpCode);
+ u1 originalOpcode = dvmGetOriginalOpcode(pc);
+ LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpcode, inst,
+ INST_REPLACE_OP(inst, originalOpcode));
+ inst = INST_REPLACE_OP(inst, originalOpcode);
+ FINISH_BKPT(originalOpcode);
}
#else
LOGE("Breakpoint hit in non-debug interpreter\n");
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