drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1

Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE
register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's
CR0 and CR1 registers by passing an id of 4 to these macros.

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717021316.18610-1-vivek.kasireddy@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 319a26a..f9bdf85 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3127,8 +3127,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
                hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
                hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
        } else {
-               hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
-               hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+               if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+                       hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
+                       hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
+               } else {
+                       hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+                       hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+               }
        }
 
        ret = true;
@@ -3169,8 +3174,13 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
                cfgcr0_reg = TGL_DPLL_CFGCR0(id);
                cfgcr1_reg = TGL_DPLL_CFGCR1(id);
        } else {
-               cfgcr0_reg = ICL_DPLL_CFGCR0(id);
-               cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+               if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+                       cfgcr0_reg = ICL_DPLL_CFGCR0(4);
+                       cfgcr1_reg = ICL_DPLL_CFGCR1(4);
+               } else {
+                       cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+                       cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+               }
        }
 
        I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);