r600g: fixup texture state on evergreen.

This whole set of state just seems wrong, another cut-n-paste nightmare.

diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
index ccc7895..ae03994 100644 (file)
--- a/src/gallium/drivers/r600/eg_hw_states.c
+++ b/src/gallium/drivers/r600/eg_hw_states.c
@@ -1006,6 +1006,149 @@ static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rp
        return radeon_state_pm4(state);
 }
 
+static void eg_texture_state_scissor(struct r600_screen *rscreen,
+                                       struct r600_resource_texture *rtexture,
+                                       unsigned level)
+{
+       struct radeon_state *rstate = &rtexture->scissor[level];
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
+       rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
+       rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
+       rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
+
+       radeon_state_pm4(rstate);
+}
+
+static void eg_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
+{
+       struct radeon_state *rstate;
+       struct r600_resource *rbuffer;
+       unsigned pitch, slice;
+       unsigned color_info;
+       unsigned format, swap, ntype, attrib;
+       const struct util_format_description *desc;
+
+       rstate = &rtexture->cb[cb][level];
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
+       rbuffer = &rtexture->resource;
+
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
+       slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
+       ntype = 0;
+       attrib = 0;
+       desc = util_format_description(rbuffer->base.b.format);
+       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+               ntype = V_028C70_NUMBER_SRGB;
+       format = r600_translate_colorformat(rtexture->resource.base.b.format);
+       swap = r600_translate_colorswap(rtexture->resource.base.b.format);
+       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
+               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+               rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+               rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+               rstate->nbo = 3;
+               color_info = 0;
+       } else {
+               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+               rstate->nbo = 3;
+               color_info = S_028C70_SOURCE_FORMAT(1);
+       }
+       color_info |= S_028C70_FORMAT(format) |
+               S_028C70_COMP_SWAP(swap) |
+               S_028C70_BLEND_CLAMP(1) |
+               S_028C70_NUMBER_TYPE(ntype);
+       rstate->states[EG_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
+       rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
+       rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
+       rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
+       rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
+       rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
+
+       radeon_state_pm4(rstate);
+}
+
+static void eg_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
+{
+       struct radeon_state *rstate = &rtexture->db[level];
+       struct r600_resource *rbuffer;
+       unsigned pitch, slice, format;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
+       rbuffer = &rtexture->resource;
+       rtexture->tilled = 1;
+       rtexture->array_mode = 2;
+       rtexture->tile_type = 1;
+       rtexture->depth = 1;
+
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
+       slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
+       format = r600_translate_dbformat(rbuffer->base.b.format);
+       rstate->states[EG_DB__DB_Z_READ_BASE] = rtexture->offset[level] >> 8;
+       rstate->states[EG_DB__DB_Z_WRITE_BASE] = rtexture->offset[level] >> 8;
+       rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtexture->array_mode) | S_028040_FORMAT(format);
+       rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
+       rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
+       rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
+       rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+       rstate->nbo = 1;
+
+       radeon_state_pm4(rstate);
+}
+
+static void eg_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
+{
+       struct radeon_state *rstate = &rtexture->viewport[level];
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
+
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
+       rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
+       rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+       rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+
+       radeon_state_pm4(rstate);
+}
+
 struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
        .blend = eg_blend,
        .ucp = eg_ucp,
@@ -1025,6 +1168,10 @@ struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
        .vs_shader = eg_vs_shader,
        .ps_shader = eg_ps_shader,
        .init_config = eg_init_config,
+       .texture_state_viewport = eg_texture_state_viewport,
+       .texture_state_db = eg_texture_state_db,
+       .texture_state_cb = eg_texture_state_cb,
+       .texture_state_scissor = eg_texture_state_scissor,
 };
 
 void eg_set_constant_buffer(struct pipe_context *ctx,

diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index e89cab3..6d4a554 100644 (file)
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -150,7 +150,9 @@ struct r600_shader_sampler_states {
 };
 
 struct r600_context;
+struct r600_screen;
 struct r600_resource;
+struct r600_resource_texture;
 
 struct r600_context_hw_state_vtbl {
        void (*blend)(struct r600_context *rctx,
@@ -185,6 +187,21 @@ struct r600_context_hw_state_vtbl {
        int (*vs_shader)(struct r600_context *rctx, struct r600_context_state *rpshader,
                         struct radeon_state *state);
        void (*init_config)(struct r600_context *rctx);
+
+
+       void (*texture_state_viewport)(struct r600_screen *rscreen,
+                                      struct r600_resource_texture *rtexture,
+                                      unsigned level);
+       void (*texture_state_cb)(struct r600_screen *rscreen,
+                                struct r600_resource_texture *rtexture,
+                                unsigned cb,
+                                unsigned level);
+       void (*texture_state_db)(struct r600_screen *rscreen,
+                                struct r600_resource_texture *rtexture,
+                                unsigned level);
+       void (*texture_state_scissor)(struct r600_screen *rscreen,
+                                struct r600_resource_texture *rtexture,
+                                unsigned level);
 };
 extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl;
 extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl;

diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
index e188fb2..b7070d7 100644 (file)
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ b/src/gallium/drivers/r600/r600_hw_states.c
@@ -1013,6 +1013,147 @@ static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *
        return radeon_state_pm4(state);
 }
 
+static void r600_texture_state_scissor(struct r600_screen *rscreen,
+                                       struct r600_resource_texture *rtexture,
+                                       unsigned level)
+{
+       struct radeon_state *rstate = &rtexture->scissor[level];
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
+       rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
+       rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
+       rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+       rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
+
+       radeon_state_pm4(rstate);
+}
+
+static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
+{
+       struct radeon_state *rstate;
+       struct r600_resource *rbuffer;
+       unsigned pitch, slice;
+       unsigned color_info;
+       unsigned format, swap, ntype;
+       const struct util_format_description *desc;
+
+       rstate = &rtexture->cb[cb][level];
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
+       rbuffer = &rtexture->resource;
+
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
+       slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
+       ntype = 0;
+       desc = util_format_description(rbuffer->base.b.format);
+       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+               ntype = V_0280A0_NUMBER_SRGB;
+       format = r600_translate_colorformat(rtexture->resource.base.b.format);
+       swap = r600_translate_colorswap(rtexture->resource.base.b.format);
+       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
+               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+               rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+               rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+               rstate->nbo = 3;
+               color_info = 0;
+       } else {
+               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+               rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+               rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+               rstate->nbo = 3;
+               color_info = S_0280A0_SOURCE_FORMAT(1);
+       }
+       color_info |= S_0280A0_FORMAT(format) |
+               S_0280A0_COMP_SWAP(swap) |
+               S_0280A0_BLEND_CLAMP(1) |
+               S_0280A0_NUMBER_TYPE(ntype);
+       rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
+       rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+       rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+                                               S_028060_SLICE_TILE_MAX(slice);
+
+       radeon_state_pm4(rstate);
+}
+
+static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
+{
+       struct radeon_state *rstate = &rtexture->db[level];
+       struct r600_resource *rbuffer;
+       unsigned pitch, slice, format;
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
+       rbuffer = &rtexture->resource;
+       rtexture->tilled = 1;
+       rtexture->array_mode = 2;
+       rtexture->tile_type = 1;
+       rtexture->depth = 1;
+
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
+       slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
+       format = r600_translate_dbformat(rbuffer->base.b.format);
+       rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
+       rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
+                                       S_028010_FORMAT(format);
+       rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
+       rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
+       rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
+                                               S_028000_SLICE_TILE_MAX(slice);
+       rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+       rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+       rstate->nbo = 1;
+
+       radeon_state_pm4(rstate);
+}
+
+static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
+{
+       struct radeon_state *rstate = &rtexture->viewport[level];
+
+       radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
+
+       /* set states (most default value are 0 and struct already
+        * initialized to 0, thus avoid resetting them)
+        */
+       rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
+       rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
+       rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
+       rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
+       rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
+       rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
+       rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+       rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+
+       radeon_state_pm4(rstate);
+}
+
 struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
        .blend = r600_blend,
        .ucp = r600_ucp,
@@ -1032,6 +1173,10 @@ struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
        .vs_shader = r600_vs_shader,
        .ps_shader = r600_ps_shader,
        .init_config = r600_init_config,
+       .texture_state_viewport = r600_texture_state_viewport,
+       .texture_state_db = r600_texture_state_db,
+       .texture_state_cb = r600_texture_state_cb,
+       .texture_state_scissor = r600_texture_state_scissor,
 };
 
 void r600_set_constant_buffer_file(struct pipe_context *ctx,

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 6c21abd..158ae22 100644 (file)
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -669,163 +669,26 @@ int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_textu
        return 0;
 }
 
-static void r600_texture_state_scissor(struct r600_screen *rscreen,
-                                       struct r600_resource_texture *rtexture,
-                                       unsigned level)
-{
-       struct radeon_state *rstate = &rtexture->scissor[level];
-
-       radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-       /* set states (most default value are 0 and struct already
-        * initialized to 0, thus avoid resetting them)
-        */
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-       rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-       rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
-       rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-       rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
-
-       radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-       struct radeon_state *rstate;
-       struct r600_resource *rbuffer;
-       unsigned pitch, slice;
-       unsigned color_info;
-       unsigned format, swap, ntype;
-       const struct util_format_description *desc;
-
-       rstate = &rtexture->cb[cb][level];
-       radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
-       rbuffer = &rtexture->resource;
-
-       /* set states (most default value are 0 and struct already
-        * initialized to 0, thus avoid resetting them)
-        */
-       pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-       slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-       ntype = 0;
-       desc = util_format_description(rbuffer->base.b.format);
-       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-               ntype = V_0280A0_NUMBER_SRGB;
-       format = r600_translate_colorformat(rtexture->resource.base.b.format);
-       swap = r600_translate_colorswap(rtexture->resource.base.b.format);
-       if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
-               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
-               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
-               rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
-               rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-               rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-               rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-               rstate->nbo = 3;
-               color_info = 0;
-       } else {
-               rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-               rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-               rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-               rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-               rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-               rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-               rstate->nbo = 3;
-               color_info = S_0280A0_SOURCE_FORMAT(1);
-       }
-       color_info |= S_0280A0_FORMAT(format) |
-               S_0280A0_COMP_SWAP(swap) |
-               S_0280A0_BLEND_CLAMP(1) |
-               S_0280A0_NUMBER_TYPE(ntype);
-       rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-       rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-       rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-                                               S_028060_SLICE_TILE_MAX(slice);
-
-       radeon_state_pm4(rstate);
-}
 
-static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-       struct radeon_state *rstate = &rtexture->db[level];
-       struct r600_resource *rbuffer;
-       unsigned pitch, slice, format;
-
-       radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-       rbuffer = &rtexture->resource;
-       rtexture->tilled = 1;
-       rtexture->array_mode = 2;
-       rtexture->tile_type = 1;
-       rtexture->depth = 1;
-
-       /* set states (most default value are 0 and struct already
-        * initialized to 0, thus avoid resetting them)
-        */
-       pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-       slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-       format = r600_translate_dbformat(rbuffer->base.b.format);
-       rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
-       rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
-                                       S_028010_FORMAT(format);
-       rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-       rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
-       rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-                                               S_028000_SLICE_TILE_MAX(slice);
-       rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-       rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-       rstate->nbo = 1;
-
-       radeon_state_pm4(rstate);
-}
 
 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
        struct r600_screen *rscreen = r600_screen(ctx->screen);
+       struct r600_context *rctx = r600_context(ctx);
 
        if (!rtexture->scissor[level].cpm4) {
-               r600_texture_state_scissor(rscreen, rtexture, level);
+               rctx->vtbl->texture_state_scissor(rscreen, rtexture, level);
        }
        return 0;
 }
 
-static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-       struct radeon_state *rstate = &rtexture->viewport[level];
-
-       radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-
-       /* set states (most default value are 0 and struct already
-        * initialized to 0, thus avoid resetting them)
-        */
-       rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
-       rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
-       rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
-       rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
-       rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
-       rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
-       rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-       rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-
-       radeon_state_pm4(rstate);
-}
-
 int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
        struct r600_screen *rscreen = r600_screen(ctx->screen);
+       struct r600_context *rctx = r600_context(ctx);
 
        if (!rtexture->cb[cb][level].cpm4) {
-               r600_texture_state_cb(rscreen, rtexture, cb, level);
+               rctx->vtbl->texture_state_cb(rscreen, rtexture, cb, level);
        }
        return 0;
 }
@@ -833,9 +696,10 @@ int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtex
 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
        struct r600_screen *rscreen = r600_screen(ctx->screen);
+       struct r600_context *rctx = r600_context(ctx);
 
        if (!rtexture->db[level].cpm4) {
-               r600_texture_state_db(rscreen, rtexture, level);
+               rctx->vtbl->texture_state_db(rscreen, rtexture, level);
        }
        return 0;
 }
@@ -843,9 +707,10 @@ int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtex
 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
        struct r600_screen *rscreen = r600_screen(ctx->screen);
+       struct r600_context *rctx = r600_context(ctx);
 
        if (!rtexture->viewport[level].cpm4) {
-               r600_texture_state_viewport(rscreen, rtexture, level);
+               rctx->vtbl->texture_state_viewport(rscreen, rtexture, level);
        }
        return 0;
 }