clk: exynos5433: Fix parent clocks for FSYS block

The proper parent clock for FSYS block is "aclk_fsys_200"
according to the Exynos5433 reference manual.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 63379b0..ffff67a 100644 (file)
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -79,7 +79,7 @@ Required Properties:
        Input clocks for fsys clock controller:
                - oscclk
                - sclk_ufs_mphy
-               - div_aclk_fsys_200
+               - aclk_fsys_200
                - sclk_pcie_100_fsys
                - sclk_ufsunipro_fsys
                - sclk_mmc2_fsys
@@ -235,7 +235,7 @@ Example 2: Examples of clock controller nodes are listed below.
 
                clock-names = "oscclk",
                        "sclk_ufs_mphy",
-                       "div_aclk_fsys_200",
+                       "aclk_fsys_200",
                        "sclk_pcie_100_fsys",
                        "sclk_ufsunipro_fsys",
                        "sclk_mmc2_fsys",
@@ -245,7 +245,7 @@ Example 2: Examples of clock controller nodes are listed below.
                        "sclk_usbdrd30_fsys";
                clocks = <&xxti>,
                       <&cmu_cpif CLK_SCLK_UFS_MPHY>,
-                      <&cmu_top CLK_DIV_ACLK_FSYS_200>,
+                      <&cmu_top CLK_ACLK_FSYS_200>,
                       <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
                       <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
                       <&cmu_top CLK_SCLK_MMC2_FSYS>,

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index ea16086..a8bb60b 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -1929,7 +1929,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
 
 /* list of all parent clock list */
 PNAME(mout_sclk_ufs_mphy_user_p)       = { "oscclk", "sclk_ufs_mphy", };
-PNAME(mout_aclk_fsys_200_user_p)       = { "oscclk", "div_aclk_fsys_200", };
+PNAME(mout_aclk_fsys_200_user_p)       = { "oscclk", "aclk_fsys_200", };
 PNAME(mout_sclk_pcie_100_user_p)       = { "oscclk", "sclk_pcie_100_fsys",};
 PNAME(mout_sclk_ufsunipro_user_p)      = { "oscclk", "sclk_ufsunipro_fsys",};
 PNAME(mout_sclk_mmc2_user_p)           = { "oscclk", "sclk_mmc2_fsys", };