[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 6eb7367..3a1925d 100644 (file)
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -2001,7 +2001,7 @@ static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
     Inst.addOperand(MCOperand::CreateImm(index));
   }
 
-  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 
   switch (Inst.getOpcode()) {
   case ARM64::ST1i8_POST:
@@ -2162,7 +2162,7 @@ static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
   }
 
   Inst.addOperand(MCOperand::CreateImm(index));
-  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 
   switch (Inst.getOpcode()) {
   case ARM64::LD1i8_POST:

diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/ARM64/advsimd.txt
index 486dd16..a943aec 100644 (file)
--- a/test/MC/Disassembler/ARM64/advsimd.txt
+++ b/test/MC/Disassembler/ARM64/advsimd.txt
@@ -618,6 +618,7 @@
 0x0a 0x68 0x40 0x4c
 0x2d 0xac 0x40 0x0c
 0x4f 0x7c 0x40 0x4c
+0xe0 0x03 0x40 0x0d
 
 # CHECK: ld1.8b { v1 }, [x1]
 # CHECK: ld1.16b { v2, v3 }, [x2]
@@ -627,6 +628,7 @@
 # CHECK: ld1.4s { v10, v11, v12 }, [x0]
 # CHECK: ld1.1d { v13, v14 }, [x1]
 # CHECK: ld1.2d        { v15 }, [x2]
+# CHECK: ld1.b { v0 }[0], [sp]
 
 0x41 0x70 0xdf 0x0c
 0x41 0xa0 0xdf 0x0c